forked from Minki/linux
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
This commit is contained in:
commit
60b7379dc5
@ -64,7 +64,7 @@ is formed.
|
||||
At mount time, the two directories given as mount options "lowerdir" and
|
||||
"upperdir" are combined into a merged directory:
|
||||
|
||||
mount -t overlayfs overlayfs -olowerdir=/lower,upperdir=/upper,\
|
||||
mount -t overlay overlay -olowerdir=/lower,upperdir=/upper,\
|
||||
workdir=/work /merged
|
||||
|
||||
The "workdir" needs to be an empty directory on the same filesystem
|
||||
|
@ -136,7 +136,7 @@ SOF_TIMESTAMPING_OPT_ID:
|
||||
|
||||
This option is implemented only for transmit timestamps. There, the
|
||||
timestamp is always looped along with a struct sock_extended_err.
|
||||
The option modifies field ee_info to pass an id that is unique
|
||||
The option modifies field ee_data to pass an id that is unique
|
||||
among all possibly concurrently outstanding timestamp requests for
|
||||
that socket. In practice, it is a monotonically increasing u32
|
||||
(that wraps).
|
||||
|
@ -6908,11 +6908,12 @@ F: drivers/scsi/osd/
|
||||
F: include/scsi/osd_*
|
||||
F: fs/exofs/
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||||
|
||||
OVERLAYFS FILESYSTEM
|
||||
OVERLAY FILESYSTEM
|
||||
M: Miklos Szeredi <miklos@szeredi.hu>
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||||
L: linux-fsdevel@vger.kernel.org
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||||
L: linux-unionfs@vger.kernel.org
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||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/vfs.git
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||||
S: Supported
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||||
F: fs/overlayfs/*
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||||
F: fs/overlayfs/
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||||
F: Documentation/filesystems/overlayfs.txt
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||||
|
||||
P54 WIRELESS DRIVER
|
||||
|
2
Makefile
2
Makefile
@ -1,7 +1,7 @@
|
||||
VERSION = 3
|
||||
PATCHLEVEL = 18
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc5
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||||
EXTRAVERSION = -rc6
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||||
NAME = Diseased Newt
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||||
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||||
# *DOCUMENTATION*
|
||||
|
@ -624,4 +624,8 @@
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||||
num-cs = <1>;
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||||
};
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||||
|
||||
&usbdrd_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
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||||
|
||||
#include "cros-ec-keyboard.dtsi"
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||||
|
@ -555,7 +555,7 @@
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||||
#size-cells = <1>;
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||||
ranges;
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||||
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||||
dwc3 {
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||||
usbdrd_dwc3: dwc3 {
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||||
compatible = "synopsys,dwc3";
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||||
reg = <0x12000000 0x10000>;
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||||
interrupts = <0 72 0>;
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||||
|
@ -433,7 +433,7 @@
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||||
clocks = <&cpg_clocks R8A7740_CLK_S>,
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||||
<&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
|
||||
<&cpg_clocks R8A7740_CLK_B>,
|
||||
<&sub_clk>, <&sub_clk>,
|
||||
<&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
|
||||
<&cpg_clocks R8A7740_CLK_B>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
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||||
|
@ -666,9 +666,9 @@
|
||||
#clock-cells = <0>;
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||||
clock-output-names = "sd2";
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||||
};
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||||
sd3_clk: sd3_clk@e615007c {
|
||||
sd3_clk: sd3_clk@e615026c {
|
||||
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
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||||
reg = <0 0xe615007c 0 4>;
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||||
reg = <0 0xe615026c 0 4>;
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||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd3";
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||||
|
@ -361,6 +361,10 @@
|
||||
clocks = <&ahb1_gates 6>;
|
||||
resets = <&ahb1_rst 6>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
/* DMA controller requires AHB1 clocked from PLL6 */
|
||||
assigned-clocks = <&ahb1_mux>;
|
||||
assigned-clock-parents = <&pll6>;
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||||
};
|
||||
|
||||
mmc0: mmc@01c0f000 {
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||||
|
@ -15,6 +15,7 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps65913@58";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -15,6 +15,10 @@
|
||||
linux,initrd-end = <0x82800000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
firmware {
|
||||
trusted-foundations {
|
||||
compatible = "tlm,trusted-foundations";
|
||||
@ -916,8 +920,6 @@
|
||||
regulator-name = "vddio-sdmmc3";
|
||||
regulator-min-microvolt = <1800000>;
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||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldousb {
|
||||
@ -962,7 +964,7 @@
|
||||
sdhci@78000400 {
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||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vddio_sdmmc3>;
|
||||
vqmmc-supply = <&vddio_sdmmc3>;
|
||||
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
|
||||
power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
@ -971,7 +973,6 @@
|
||||
sdhci@78000600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <&vdd_1v8>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
|
@ -15,6 +15,10 @@
|
||||
linux,initrd-end = <0x82800000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
firmware {
|
||||
trusted-foundations {
|
||||
compatible = "tlm,trusted-foundations";
|
||||
@ -240,7 +244,6 @@
|
||||
sdhci@78000600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <&vdd_1v8>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
|
@ -9,13 +9,6 @@
|
||||
compatible = "nvidia,tegra114";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
compatible = "nvidia,tegra114-host1x", "simple-bus";
|
||||
reg = <0x50000000 0x00028000>;
|
||||
|
@ -10,6 +10,7 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@0,7000d000/pmic@40";
|
||||
rtc1 = "/rtc@0,7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -10,6 +10,7 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@0,7000d000/pmic@40";
|
||||
rtc1 = "/rtc@0,7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -10,6 +10,7 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@0,7000d000/pmic@40";
|
||||
rtc1 = "/rtc@0,7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -286,7 +286,7 @@
|
||||
* the APB DMA based serial driver, the comptible is
|
||||
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
|
||||
*/
|
||||
serial@0,70006000 {
|
||||
uarta: serial@0,70006000 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006000 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
@ -299,7 +299,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@0,70006040 {
|
||||
uartb: serial@0,70006040 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006040 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
@ -312,7 +312,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@0,70006200 {
|
||||
uartc: serial@0,70006200 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006200 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
@ -325,7 +325,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@0,70006300 {
|
||||
uartd: serial@0,70006300 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006300 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
|
@ -10,6 +10,7 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -6,6 +6,11 @@
|
||||
model = "Toradex Colibri T20 512MB on Iris";
|
||||
compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartd;
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
@ -6,6 +6,10 @@
|
||||
model = "Avionic Design Medcom-Wide board";
|
||||
compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
|
||||
|
||||
aliases {
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
pwm@7000a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -10,6 +10,8 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartc;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -10,6 +10,7 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -7,6 +7,7 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -10,6 +10,7 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@7000c500/rtc@56";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -10,6 +10,7 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -10,6 +10,7 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@7000d000/max8907@3c";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -9,14 +9,6 @@
|
||||
compatible = "nvidia,tegra20";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
serial4 = &uarte;
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
compatible = "nvidia,tegra20-host1x", "simple-bus";
|
||||
reg = <0x50000000 0x00024000>;
|
||||
|
@ -11,6 +11,10 @@
|
||||
rtc0 = "/i2c@7000c000/rtc@68";
|
||||
rtc1 = "/i2c@7000d000/tps65911@2d";
|
||||
rtc2 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
};
|
||||
|
||||
pcie-controller@00003000 {
|
||||
|
@ -9,6 +9,7 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps65911@2d";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -30,6 +30,8 @@
|
||||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps65911@2d";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartc;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -10,6 +10,9 @@
|
||||
rtc0 = "/i2c@7000c000/rtc@68";
|
||||
rtc1 = "/i2c@7000d000/tps65911@2d";
|
||||
rtc2 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartd;
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
|
@ -9,14 +9,6 @@
|
||||
compatible = "nvidia,tegra30";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
serial4 = &uarte;
|
||||
};
|
||||
|
||||
pcie-controller@00003000 {
|
||||
compatible = "nvidia,tegra30-pcie";
|
||||
device_type = "pci";
|
||||
|
@ -142,11 +142,13 @@ CONFIG_MMC_DW_IDMAC=y
|
||||
CONFIG_MMC_DW_EXYNOS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_MAX77686=y
|
||||
CONFIG_RTC_DRV_MAX77802=y
|
||||
CONFIG_RTC_DRV_S5M=y
|
||||
CONFIG_RTC_DRV_S3C=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_COMMON_CLK_MAX77686=y
|
||||
CONFIG_COMMON_CLK_MAX77802=y
|
||||
CONFIG_COMMON_CLK_S2MPS11=y
|
||||
CONFIG_EXYNOS_IOMMU=y
|
||||
CONFIG_IIO=y
|
||||
|
@ -217,6 +217,7 @@ CONFIG_I2C_CADENCE=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
CONFIG_I2C_EXYNOS5=y
|
||||
CONFIG_I2C_MV64XXX=y
|
||||
CONFIG_I2C_S3C2410=y
|
||||
CONFIG_I2C_SIRF=y
|
||||
CONFIG_I2C_TEGRA=y
|
||||
CONFIG_I2C_ST=y
|
||||
|
@ -44,16 +44,6 @@ struct cpu_context_save {
|
||||
__u32 extra[2]; /* Xscale 'acc' register, etc */
|
||||
};
|
||||
|
||||
struct arm_restart_block {
|
||||
union {
|
||||
/* For user cache flushing */
|
||||
struct {
|
||||
unsigned long start;
|
||||
unsigned long end;
|
||||
} cache;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* low level task data that entry.S needs immediate access to.
|
||||
* __switch_to() assumes cpu_context follows immediately after cpu_domain.
|
||||
@ -79,7 +69,6 @@ struct thread_info {
|
||||
unsigned long thumbee_state; /* ThumbEE Handler Base register */
|
||||
#endif
|
||||
struct restart_block restart_block;
|
||||
struct arm_restart_block arm_restart_block;
|
||||
};
|
||||
|
||||
#define INIT_THREAD_INFO(tsk) \
|
||||
|
@ -533,8 +533,6 @@ static int bad_syscall(int n, struct pt_regs *regs)
|
||||
return regs->ARM_r0;
|
||||
}
|
||||
|
||||
static long do_cache_op_restart(struct restart_block *);
|
||||
|
||||
static inline int
|
||||
__do_cache_op(unsigned long start, unsigned long end)
|
||||
{
|
||||
@ -543,24 +541,8 @@ __do_cache_op(unsigned long start, unsigned long end)
|
||||
do {
|
||||
unsigned long chunk = min(PAGE_SIZE, end - start);
|
||||
|
||||
if (signal_pending(current)) {
|
||||
struct thread_info *ti = current_thread_info();
|
||||
|
||||
ti->restart_block = (struct restart_block) {
|
||||
.fn = do_cache_op_restart,
|
||||
};
|
||||
|
||||
ti->arm_restart_block = (struct arm_restart_block) {
|
||||
{
|
||||
.cache = {
|
||||
.start = start,
|
||||
.end = end,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
return -ERESTART_RESTARTBLOCK;
|
||||
}
|
||||
if (fatal_signal_pending(current))
|
||||
return 0;
|
||||
|
||||
ret = flush_cache_user_range(start, start + chunk);
|
||||
if (ret)
|
||||
@ -573,15 +555,6 @@ __do_cache_op(unsigned long start, unsigned long end)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long do_cache_op_restart(struct restart_block *unused)
|
||||
{
|
||||
struct arm_restart_block *restart_block;
|
||||
|
||||
restart_block = ¤t_thread_info()->arm_restart_block;
|
||||
return __do_cache_op(restart_block->cache.start,
|
||||
restart_block->cache.end);
|
||||
}
|
||||
|
||||
static inline int
|
||||
do_cache_op(unsigned long start, unsigned long end, int flags)
|
||||
{
|
||||
|
@ -197,7 +197,8 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
|
||||
pgd = pgdp + pgd_index(addr);
|
||||
do {
|
||||
next = kvm_pgd_addr_end(addr, end);
|
||||
unmap_puds(kvm, pgd, addr, next);
|
||||
if (!pgd_none(*pgd))
|
||||
unmap_puds(kvm, pgd, addr, next);
|
||||
} while (pgd++, addr = next, addr != end);
|
||||
}
|
||||
|
||||
@ -834,6 +835,11 @@ static bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
|
||||
return kvm_vcpu_dabt_iswrite(vcpu);
|
||||
}
|
||||
|
||||
static bool kvm_is_device_pfn(unsigned long pfn)
|
||||
{
|
||||
return !pfn_valid(pfn);
|
||||
}
|
||||
|
||||
static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
|
||||
struct kvm_memory_slot *memslot, unsigned long hva,
|
||||
unsigned long fault_status)
|
||||
@ -904,7 +910,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
|
||||
if (is_error_pfn(pfn))
|
||||
return -EFAULT;
|
||||
|
||||
if (kvm_is_mmio_pfn(pfn))
|
||||
if (kvm_is_device_pfn(pfn))
|
||||
mem_type = PAGE_S2_DEVICE;
|
||||
|
||||
spin_lock(&kvm->mmu_lock);
|
||||
|
@ -400,6 +400,8 @@ int __init coherency_init(void)
|
||||
type == COHERENCY_FABRIC_TYPE_ARMADA_380)
|
||||
armada_375_380_coherency_init(np);
|
||||
|
||||
of_node_put(np);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -455,7 +455,7 @@ enum {
|
||||
MSTP128, MSTP127, MSTP125,
|
||||
MSTP116, MSTP111, MSTP100, MSTP117,
|
||||
|
||||
MSTP230,
|
||||
MSTP230, MSTP229,
|
||||
MSTP222,
|
||||
MSTP218, MSTP217, MSTP216, MSTP214,
|
||||
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
@ -474,11 +474,12 @@ static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */
|
||||
[MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
|
||||
[MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
|
||||
[MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
|
||||
[MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_HPP], SMSTPCR1, 16, 0), /* IIC0 */
|
||||
[MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
|
||||
[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
|
||||
|
||||
[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
|
||||
[MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 29, 0), /* INTCA */
|
||||
[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
|
||||
[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
|
||||
[MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
|
||||
@ -575,6 +576,10 @@ static struct clk_lookup lookups[] = {
|
||||
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
|
||||
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
|
||||
CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]),
|
||||
CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP229]),
|
||||
CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP229]),
|
||||
CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP229]),
|
||||
CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP229]),
|
||||
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
|
||||
CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]),
|
||||
|
||||
|
@ -68,7 +68,7 @@
|
||||
|
||||
#define SDCKCR 0xE6150074
|
||||
#define SD2CKCR 0xE6150078
|
||||
#define SD3CKCR 0xE615007C
|
||||
#define SD3CKCR 0xE615026C
|
||||
#define MMC0CKCR 0xE6150240
|
||||
#define MMC1CKCR 0xE6150244
|
||||
#define SSPCKCR 0xE6150248
|
||||
|
@ -26,6 +26,7 @@
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/i2c/i2c-sh_mobile.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_dma.h>
|
||||
@ -192,11 +193,18 @@ static struct resource i2c4_resources[] = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct i2c_sh_mobile_platform_data i2c_platform_data = {
|
||||
.clks_per_count = 2,
|
||||
};
|
||||
|
||||
static struct platform_device i2c0_device = {
|
||||
.name = "i2c-sh_mobile",
|
||||
.id = 0,
|
||||
.resource = i2c0_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c0_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c1_device = {
|
||||
@ -204,6 +212,9 @@ static struct platform_device i2c1_device = {
|
||||
.id = 1,
|
||||
.resource = i2c1_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c1_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c2_device = {
|
||||
@ -211,6 +222,9 @@ static struct platform_device i2c2_device = {
|
||||
.id = 2,
|
||||
.resource = i2c2_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c2_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c3_device = {
|
||||
@ -218,6 +232,9 @@ static struct platform_device i2c3_device = {
|
||||
.id = 3,
|
||||
.resource = i2c3_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c3_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c4_device = {
|
||||
@ -225,6 +242,9 @@ static struct platform_device i2c4_device = {
|
||||
.id = 4,
|
||||
.resource = i2c4_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c4_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
|
||||
|
@ -99,42 +99,42 @@ static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
|
||||
|
||||
static void tegra_mask(struct irq_data *d)
|
||||
{
|
||||
if (d->irq < FIRST_LEGACY_IRQ)
|
||||
if (d->hwirq < FIRST_LEGACY_IRQ)
|
||||
return;
|
||||
|
||||
tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
|
||||
tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IER_CLR);
|
||||
}
|
||||
|
||||
static void tegra_unmask(struct irq_data *d)
|
||||
{
|
||||
if (d->irq < FIRST_LEGACY_IRQ)
|
||||
if (d->hwirq < FIRST_LEGACY_IRQ)
|
||||
return;
|
||||
|
||||
tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
|
||||
tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IER_SET);
|
||||
}
|
||||
|
||||
static void tegra_ack(struct irq_data *d)
|
||||
{
|
||||
if (d->irq < FIRST_LEGACY_IRQ)
|
||||
if (d->hwirq < FIRST_LEGACY_IRQ)
|
||||
return;
|
||||
|
||||
tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
|
||||
tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IEP_FIR_CLR);
|
||||
}
|
||||
|
||||
static void tegra_eoi(struct irq_data *d)
|
||||
{
|
||||
if (d->irq < FIRST_LEGACY_IRQ)
|
||||
if (d->hwirq < FIRST_LEGACY_IRQ)
|
||||
return;
|
||||
|
||||
tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
|
||||
tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IEP_FIR_CLR);
|
||||
}
|
||||
|
||||
static int tegra_retrigger(struct irq_data *d)
|
||||
{
|
||||
if (d->irq < FIRST_LEGACY_IRQ)
|
||||
if (d->hwirq < FIRST_LEGACY_IRQ)
|
||||
return 0;
|
||||
|
||||
tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
|
||||
tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IEP_FIR_SET);
|
||||
|
||||
return 1;
|
||||
}
|
||||
@ -142,7 +142,7 @@ static int tegra_retrigger(struct irq_data *d)
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int tegra_set_wake(struct irq_data *d, unsigned int enable)
|
||||
{
|
||||
u32 irq = d->irq;
|
||||
u32 irq = d->hwirq;
|
||||
u32 index, mask;
|
||||
|
||||
if (irq < FIRST_LEGACY_IRQ ||
|
||||
|
@ -270,7 +270,6 @@ __v7_pj4b_setup:
|
||||
/* Auxiliary Debug Modes Control 1 Register */
|
||||
#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
|
||||
#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
|
||||
#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
|
||||
#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
|
||||
|
||||
/* Auxiliary Debug Modes Control 2 Register */
|
||||
@ -293,7 +292,6 @@ __v7_pj4b_setup:
|
||||
/* Auxiliary Debug Modes Control 1 Register */
|
||||
mrc p15, 1, r0, c15, c1, 1
|
||||
orr r0, r0, #PJ4B_CLEAN_LINE
|
||||
orr r0, r0, #PJ4B_BCK_OFF_STREX
|
||||
orr r0, r0, #PJ4B_INTER_PARITY
|
||||
bic r0, r0, #PJ4B_STATIC_BP
|
||||
mcr p15, 1, r0, c15, c1, 1
|
||||
|
@ -535,7 +535,7 @@ ENTRY(cpu_xscale_do_suspend)
|
||||
mrc p15, 0, r5, c15, c1, 0 @ CP access reg
|
||||
mrc p15, 0, r6, c13, c0, 0 @ PID
|
||||
mrc p15, 0, r7, c3, c0, 0 @ domain ID
|
||||
mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg
|
||||
mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
|
||||
mrc p15, 0, r9, c1, c0, 0 @ control reg
|
||||
bic r4, r4, #2 @ clear frequency change bit
|
||||
stmia r0, {r4 - r9} @ store cp regs
|
||||
@ -552,7 +552,7 @@ ENTRY(cpu_xscale_do_resume)
|
||||
mcr p15, 0, r6, c13, c0, 0 @ PID
|
||||
mcr p15, 0, r7, c3, c0, 0 @ domain ID
|
||||
mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
|
||||
mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
|
||||
mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
|
||||
mov r0, r9 @ control register
|
||||
b cpu_resume_mmu
|
||||
ENDPROC(cpu_xscale_do_resume)
|
||||
|
@ -424,6 +424,11 @@ static const struct sys_reg_desc sys_reg_descs[] = {
|
||||
/* VBAR_EL1 */
|
||||
{ Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
|
||||
NULL, reset_val, VBAR_EL1, 0 },
|
||||
|
||||
/* ICC_SRE_EL1 */
|
||||
{ Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
|
||||
trap_raz_wi },
|
||||
|
||||
/* CONTEXTIDR_EL1 */
|
||||
{ Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
|
||||
access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
|
||||
@ -690,6 +695,10 @@ static const struct sys_reg_desc cp15_regs[] = {
|
||||
{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
|
||||
{ Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
|
||||
{ Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
|
||||
|
||||
/* ICC_SRE */
|
||||
{ Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
|
||||
|
||||
{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
|
||||
};
|
||||
|
||||
|
@ -1563,7 +1563,7 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
|
||||
|
||||
for (i = 0; i < npages; i++) {
|
||||
pfn = gfn_to_pfn(kvm, base_gfn + i);
|
||||
if (!kvm_is_mmio_pfn(pfn)) {
|
||||
if (!kvm_is_reserved_pfn(pfn)) {
|
||||
kvm_set_pmt_entry(kvm, base_gfn + i,
|
||||
pfn << PAGE_SHIFT,
|
||||
_PAGE_AR_RWX | _PAGE_MA_WB);
|
||||
|
@ -2101,9 +2101,17 @@ config 64BIT_PHYS_ADDR
|
||||
config ARCH_PHYS_ADDR_T_64BIT
|
||||
def_bool 64BIT_PHYS_ADDR
|
||||
|
||||
choice
|
||||
prompt "SmartMIPS or microMIPS ASE support"
|
||||
|
||||
config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
|
||||
bool "None"
|
||||
help
|
||||
Select this if you want neither microMIPS nor SmartMIPS support
|
||||
|
||||
config CPU_HAS_SMARTMIPS
|
||||
depends on SYS_SUPPORTS_SMARTMIPS
|
||||
bool "Support for the SmartMIPS ASE"
|
||||
bool "SmartMIPS"
|
||||
help
|
||||
SmartMIPS is a extension of the MIPS32 architecture aimed at
|
||||
increased security at both hardware and software level for
|
||||
@ -2115,11 +2123,13 @@ config CPU_HAS_SMARTMIPS
|
||||
|
||||
config CPU_MICROMIPS
|
||||
depends on SYS_SUPPORTS_MICROMIPS
|
||||
bool "Build kernel using microMIPS ISA"
|
||||
bool "microMIPS"
|
||||
help
|
||||
When this option is enabled the kernel will be built using the
|
||||
microMIPS ISA
|
||||
|
||||
endchoice
|
||||
|
||||
config CPU_HAS_MSA
|
||||
bool "Support for the MIPS SIMD Architecture (EXPERIMENTAL)"
|
||||
depends on CPU_SUPPORTS_MSA
|
||||
|
@ -661,6 +661,8 @@
|
||||
#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
|
||||
/* proAptiv FTLB on/off bit */
|
||||
#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
|
||||
/* FTLB probability bits */
|
||||
#define MIPS_CONF6_FTLBP_SHIFT (16)
|
||||
|
||||
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
|
||||
|
||||
|
@ -257,7 +257,11 @@ static inline void protected_flush_icache_line(unsigned long addr)
|
||||
*/
|
||||
static inline void protected_writeback_dcache_line(unsigned long addr)
|
||||
{
|
||||
#ifdef CONFIG_EVA
|
||||
protected_cachee_op(Hit_Writeback_Inv_D, addr);
|
||||
#else
|
||||
protected_cache_op(Hit_Writeback_Inv_D, addr);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void protected_writeback_scache_line(unsigned long addr)
|
||||
|
@ -1422,7 +1422,7 @@ static inline long __strnlen_user(const char __user *s, long n)
|
||||
}
|
||||
|
||||
/*
|
||||
* strlen_user: - Get the size of a string in user space.
|
||||
* strnlen_user: - Get the size of a string in user space.
|
||||
* @str: The string to measure.
|
||||
*
|
||||
* Context: User context only. This function may sleep.
|
||||
@ -1431,9 +1431,7 @@ static inline long __strnlen_user(const char __user *s, long n)
|
||||
*
|
||||
* Returns the size of the string INCLUDING the terminating NUL.
|
||||
* On exception, returns 0.
|
||||
*
|
||||
* If there is a limit on the length of a valid string, you may wish to
|
||||
* consider using strnlen_user() instead.
|
||||
* If the string is too long, returns a value greater than @n.
|
||||
*/
|
||||
static inline long strnlen_user(const char __user *s, long n)
|
||||
{
|
||||
|
@ -1045,7 +1045,7 @@
|
||||
#define __NR_seccomp (__NR_Linux + 316)
|
||||
#define __NR_getrandom (__NR_Linux + 317)
|
||||
#define __NR_memfd_create (__NR_Linux + 318)
|
||||
#define __NR_memfd_create (__NR_Linux + 319)
|
||||
#define __NR_bpf (__NR_Linux + 319)
|
||||
|
||||
/*
|
||||
* Offset of the last N32 flavoured syscall
|
||||
|
@ -208,7 +208,6 @@ bmips_reset_nmi_vec_end:
|
||||
END(bmips_reset_nmi_vec)
|
||||
|
||||
.set pop
|
||||
.previous
|
||||
|
||||
/***********************************************************************
|
||||
* CPU1 warm restart vector (used for second and subsequent boots).
|
||||
@ -281,5 +280,3 @@ LEAF(bmips_enable_xks01)
|
||||
jr ra
|
||||
|
||||
END(bmips_enable_xks01)
|
||||
|
||||
.previous
|
||||
|
@ -229,6 +229,7 @@ LEAF(mips_cps_core_init)
|
||||
nop
|
||||
|
||||
.set push
|
||||
.set mips32r2
|
||||
.set mt
|
||||
|
||||
/* Only allow 1 TC per VPE to execute... */
|
||||
@ -345,6 +346,7 @@ LEAF(mips_cps_boot_vpes)
|
||||
nop
|
||||
|
||||
.set push
|
||||
.set mips32r2
|
||||
.set mt
|
||||
|
||||
1: /* Enter VPE configuration state */
|
||||
|
@ -193,6 +193,32 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
|
||||
static char unknown_isa[] = KERN_ERR \
|
||||
"Unsupported ISA type, c0.config0: %d.";
|
||||
|
||||
static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
|
||||
{
|
||||
|
||||
unsigned int probability = c->tlbsize / c->tlbsizevtlb;
|
||||
|
||||
/*
|
||||
* 0 = All TLBWR instructions go to FTLB
|
||||
* 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
|
||||
* FTLB and 1 goes to the VTLB.
|
||||
* 2 = 7:1: As above with 7:1 ratio.
|
||||
* 3 = 3:1: As above with 3:1 ratio.
|
||||
*
|
||||
* Use the linear midpoint as the probability threshold.
|
||||
*/
|
||||
if (probability >= 12)
|
||||
return 1;
|
||||
else if (probability >= 6)
|
||||
return 2;
|
||||
else
|
||||
/*
|
||||
* So FTLB is less than 4 times bigger than VTLB.
|
||||
* A 3:1 ratio can still be useful though.
|
||||
*/
|
||||
return 3;
|
||||
}
|
||||
|
||||
static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
|
||||
{
|
||||
unsigned int config6;
|
||||
@ -203,9 +229,14 @@ static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
|
||||
case CPU_P5600:
|
||||
/* proAptiv & related cores use Config6 to enable the FTLB */
|
||||
config6 = read_c0_config6();
|
||||
/* Clear the old probability value */
|
||||
config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
|
||||
if (enable)
|
||||
/* Enable FTLB */
|
||||
write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
|
||||
write_c0_config6(config6 |
|
||||
(calculate_ftlb_probability(c)
|
||||
<< MIPS_CONF6_FTLBP_SHIFT)
|
||||
| MIPS_CONF6_FTLBEN);
|
||||
else
|
||||
/* Disable FTLB */
|
||||
write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
|
||||
|
@ -94,12 +94,12 @@ int rtlx_open(int index, int can_sleep)
|
||||
int ret = 0;
|
||||
|
||||
if (index >= RTLX_CHANNELS) {
|
||||
pr_debug(KERN_DEBUG "rtlx_open index out of range\n");
|
||||
pr_debug("rtlx_open index out of range\n");
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
if (atomic_inc_return(&channel_wqs[index].in_open) > 1) {
|
||||
pr_debug(KERN_DEBUG "rtlx_open channel %d already opened\n", index);
|
||||
pr_debug("rtlx_open channel %d already opened\n", index);
|
||||
ret = -EBUSY;
|
||||
goto out_fail;
|
||||
}
|
||||
|
@ -485,7 +485,7 @@ static void __init bootmem_init(void)
|
||||
* NOTE: historically plat_mem_setup did the entire platform initialization.
|
||||
* This was rather impractical because it meant plat_mem_setup had to
|
||||
* get away without any kind of memory allocator. To keep old code from
|
||||
* breaking plat_setup was just renamed to plat_setup and a second platform
|
||||
* breaking plat_setup was just renamed to plat_mem_setup and a second platform
|
||||
* initialization hook for anything else was introduced.
|
||||
*/
|
||||
|
||||
@ -493,7 +493,7 @@ static int usermem __initdata;
|
||||
|
||||
static int __init early_parse_mem(char *p)
|
||||
{
|
||||
unsigned long start, size;
|
||||
phys_t start, size;
|
||||
|
||||
/*
|
||||
* If a user specifies memory size, we
|
||||
|
@ -658,13 +658,13 @@ static int signal_setup(void)
|
||||
save_fp_context = _save_fp_context;
|
||||
restore_fp_context = _restore_fp_context;
|
||||
} else {
|
||||
save_fp_context = copy_fp_from_sigcontext;
|
||||
restore_fp_context = copy_fp_to_sigcontext;
|
||||
save_fp_context = copy_fp_to_sigcontext;
|
||||
restore_fp_context = copy_fp_from_sigcontext;
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
#else
|
||||
save_fp_context = copy_fp_from_sigcontext;;
|
||||
restore_fp_context = copy_fp_to_sigcontext;
|
||||
save_fp_context = copy_fp_to_sigcontext;
|
||||
restore_fp_context = copy_fp_from_sigcontext;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
@ -11,7 +11,8 @@ obj-$(CONFIG_PCI) += pci.o
|
||||
# Serial port support
|
||||
#
|
||||
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||
obj-$(CONFIG_SERIAL_8250) += serial.o
|
||||
loongson-serial-$(CONFIG_SERIAL_8250) := serial.o
|
||||
obj-y += $(loongson-serial-m) $(loongson-serial-y)
|
||||
obj-$(CONFIG_LOONGSON_UART_BASE) += uart_base.o
|
||||
obj-$(CONFIG_LOONGSON_MC146818) += rtc.o
|
||||
|
||||
|
@ -1872,8 +1872,16 @@ build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
|
||||
uasm_l_smp_pgtable_change(l, *p);
|
||||
#endif
|
||||
iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
|
||||
if (!m4kc_tlbp_war())
|
||||
if (!m4kc_tlbp_war()) {
|
||||
build_tlb_probe_entry(p);
|
||||
if (cpu_has_htw) {
|
||||
/* race condition happens, leaving */
|
||||
uasm_i_ehb(p);
|
||||
uasm_i_mfc0(p, wr.r3, C0_INDEX);
|
||||
uasm_il_bltz(p, r, wr.r3, label_leave);
|
||||
uasm_i_nop(p);
|
||||
}
|
||||
}
|
||||
return wr;
|
||||
}
|
||||
|
||||
|
@ -5,7 +5,7 @@
|
||||
*
|
||||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
@ -76,8 +76,4 @@ static int __init led_init(void)
|
||||
return platform_device_register(&fled_device);
|
||||
}
|
||||
|
||||
module_init(led_init);
|
||||
|
||||
MODULE_AUTHOR("Chris Dearman <chris@mips.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("LED probe driver for SEAD-3");
|
||||
device_initcall(led_init);
|
||||
|
@ -1,6 +1,10 @@
|
||||
obj-y += setup.o nlm_hal.o cop2-ex.o dt.o
|
||||
obj-$(CONFIG_SMP) += wakeup.o
|
||||
obj-$(CONFIG_USB) += usb-init.o
|
||||
obj-$(CONFIG_USB) += usb-init-xlp2.o
|
||||
obj-$(CONFIG_SATA_AHCI) += ahci-init.o
|
||||
obj-$(CONFIG_SATA_AHCI) += ahci-init-xlp2.o
|
||||
ifdef CONFIG_USB
|
||||
obj-y += usb-init.o
|
||||
obj-y += usb-init-xlp2.o
|
||||
endif
|
||||
ifdef CONFIG_SATA_AHCI
|
||||
obj-y += ahci-init.o
|
||||
obj-y += ahci-init-xlp2.o
|
||||
endif
|
||||
|
@ -159,8 +159,6 @@ struct pci_dn {
|
||||
|
||||
int pci_ext_config_space; /* for pci devices */
|
||||
|
||||
bool force_32bit_msi;
|
||||
|
||||
struct pci_dev *pcidev; /* back-pointer to the pci device */
|
||||
#ifdef CONFIG_EEH
|
||||
struct eeh_dev *edev; /* eeh device */
|
||||
|
@ -65,7 +65,7 @@ static ssize_t eeh_pe_state_show(struct device *dev,
|
||||
return -ENODEV;
|
||||
|
||||
state = eeh_ops->get_state(edev->pe, NULL);
|
||||
return sprintf(buf, "%0x08x %0x08x\n",
|
||||
return sprintf(buf, "0x%08x 0x%08x\n",
|
||||
state, edev->pe->state);
|
||||
}
|
||||
|
||||
|
@ -266,13 +266,3 @@ int pcibus_to_node(struct pci_bus *bus)
|
||||
}
|
||||
EXPORT_SYMBOL(pcibus_to_node);
|
||||
#endif
|
||||
|
||||
static void quirk_radeon_32bit_msi(struct pci_dev *dev)
|
||||
{
|
||||
struct pci_dn *pdn = pci_get_pdn(dev);
|
||||
|
||||
if (pdn)
|
||||
pdn->force_32bit_msi = true;
|
||||
}
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x68f2, quirk_radeon_32bit_msi);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0xaa68, quirk_radeon_32bit_msi);
|
||||
|
@ -30,8 +30,8 @@
|
||||
V_FUNCTION_BEGIN(__kernel_getcpu)
|
||||
.cfi_startproc
|
||||
mfspr r5,SPRN_SPRG_VDSO_READ
|
||||
cmpdi cr0,r3,0
|
||||
cmpdi cr1,r4,0
|
||||
cmpwi cr0,r3,0
|
||||
cmpwi cr1,r4,0
|
||||
clrlwi r6,r5,16
|
||||
rlwinm r7,r5,16,31-15,31-0
|
||||
beq cr0,1f
|
||||
|
@ -57,7 +57,7 @@ static void print_hmi_event_info(struct OpalHMIEvent *hmi_evt)
|
||||
};
|
||||
|
||||
/* Print things out */
|
||||
if (hmi_evt->version != OpalHMIEvt_V1) {
|
||||
if (hmi_evt->version < OpalHMIEvt_V1) {
|
||||
pr_err("HMI Interrupt, Unknown event version %d !\n",
|
||||
hmi_evt->version);
|
||||
return;
|
||||
|
@ -1509,7 +1509,6 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
|
||||
unsigned int is_64, struct msi_msg *msg)
|
||||
{
|
||||
struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
|
||||
struct pci_dn *pdn = pci_get_pdn(dev);
|
||||
unsigned int xive_num = hwirq - phb->msi_base;
|
||||
__be32 data;
|
||||
int rc;
|
||||
@ -1523,7 +1522,7 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
|
||||
return -ENXIO;
|
||||
|
||||
/* Force 32-bit MSI on some broken devices */
|
||||
if (pdn && pdn->force_32bit_msi)
|
||||
if (dev->no_64bit_msi)
|
||||
is_64 = 0;
|
||||
|
||||
/* Assign XIVE to PE */
|
||||
@ -1997,7 +1996,7 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
|
||||
if (is_kdump_kernel()) {
|
||||
pr_info(" Issue PHB reset ...\n");
|
||||
ioda_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
|
||||
ioda_eeh_phb_reset(hose, OPAL_DEASSERT_RESET);
|
||||
ioda_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
|
||||
}
|
||||
|
||||
/* Configure M64 window */
|
||||
|
@ -50,7 +50,6 @@ static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
|
||||
{
|
||||
struct pci_controller *hose = pci_bus_to_host(pdev->bus);
|
||||
struct pnv_phb *phb = hose->private_data;
|
||||
struct pci_dn *pdn = pci_get_pdn(pdev);
|
||||
struct msi_desc *entry;
|
||||
struct msi_msg msg;
|
||||
int hwirq;
|
||||
@ -60,7 +59,7 @@ static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
|
||||
if (WARN_ON(!phb) || !phb->msi_bmp.bitmap)
|
||||
return -ENODEV;
|
||||
|
||||
if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
|
||||
if (pdev->no_64bit_msi && !phb->msi32_support)
|
||||
return -ENODEV;
|
||||
|
||||
list_for_each_entry(entry, &pdev->msi_list, list) {
|
||||
|
@ -420,7 +420,7 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec_in, int type)
|
||||
*/
|
||||
again:
|
||||
if (type == PCI_CAP_ID_MSI) {
|
||||
if (pdn->force_32bit_msi) {
|
||||
if (pdev->no_64bit_msi) {
|
||||
rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec);
|
||||
if (rc < 0) {
|
||||
/*
|
||||
|
@ -293,10 +293,10 @@ static inline void disable_surveillance(void)
|
||||
args.token = rtas_token("set-indicator");
|
||||
if (args.token == RTAS_UNKNOWN_SERVICE)
|
||||
return;
|
||||
args.nargs = 3;
|
||||
args.nret = 1;
|
||||
args.nargs = cpu_to_be32(3);
|
||||
args.nret = cpu_to_be32(1);
|
||||
args.rets = &args.args[3];
|
||||
args.args[0] = SURVEILLANCE_TOKEN;
|
||||
args.args[0] = cpu_to_be32(SURVEILLANCE_TOKEN);
|
||||
args.args[1] = 0;
|
||||
args.args[2] = 0;
|
||||
enter_rtas(__pa(&args));
|
||||
|
@ -12,6 +12,14 @@ int dma_supported(struct device *dev, u64 mask);
|
||||
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
|
||||
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
|
||||
|
||||
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
/* Since dma_{alloc,free}_noncoherent() allocated coherent memory, this
|
||||
* routine can be a nop.
|
||||
*/
|
||||
}
|
||||
|
||||
extern struct dma_map_ops *dma_ops;
|
||||
extern struct dma_map_ops *leon_dma_ops;
|
||||
extern struct dma_map_ops pci32_dma_ops;
|
||||
|
@ -20,7 +20,6 @@
|
||||
#define THREAD_SIZE_ORDER 1
|
||||
#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
|
||||
|
||||
#define STACKFAULT_STACK 0
|
||||
#define DOUBLEFAULT_STACK 1
|
||||
#define NMI_STACK 0
|
||||
#define DEBUG_STACK 0
|
||||
|
@ -14,12 +14,11 @@
|
||||
#define IRQ_STACK_ORDER 2
|
||||
#define IRQ_STACK_SIZE (PAGE_SIZE << IRQ_STACK_ORDER)
|
||||
|
||||
#define STACKFAULT_STACK 1
|
||||
#define DOUBLEFAULT_STACK 2
|
||||
#define NMI_STACK 3
|
||||
#define DEBUG_STACK 4
|
||||
#define MCE_STACK 5
|
||||
#define N_EXCEPTION_STACKS 5 /* hw limit: 7 */
|
||||
#define DOUBLEFAULT_STACK 1
|
||||
#define NMI_STACK 2
|
||||
#define DEBUG_STACK 3
|
||||
#define MCE_STACK 4
|
||||
#define N_EXCEPTION_STACKS 4 /* hw limit: 7 */
|
||||
|
||||
#define PUD_PAGE_SIZE (_AC(1, UL) << PUD_SHIFT)
|
||||
#define PUD_PAGE_MASK (~(PUD_PAGE_SIZE-1))
|
||||
|
@ -141,7 +141,7 @@ struct thread_info {
|
||||
/* Only used for 64 bit */
|
||||
#define _TIF_DO_NOTIFY_MASK \
|
||||
(_TIF_SIGPENDING | _TIF_MCE_NOTIFY | _TIF_NOTIFY_RESUME | \
|
||||
_TIF_USER_RETURN_NOTIFY)
|
||||
_TIF_USER_RETURN_NOTIFY | _TIF_UPROBE)
|
||||
|
||||
/* flags to check in __switch_to() */
|
||||
#define _TIF_WORK_CTXSW \
|
||||
|
@ -39,6 +39,7 @@ asmlinkage void simd_coprocessor_error(void);
|
||||
|
||||
#ifdef CONFIG_TRACING
|
||||
asmlinkage void trace_page_fault(void);
|
||||
#define trace_stack_segment stack_segment
|
||||
#define trace_divide_error divide_error
|
||||
#define trace_bounds bounds
|
||||
#define trace_invalid_op invalid_op
|
||||
|
@ -24,7 +24,6 @@ static char x86_stack_ids[][8] = {
|
||||
[ DEBUG_STACK-1 ] = "#DB",
|
||||
[ NMI_STACK-1 ] = "NMI",
|
||||
[ DOUBLEFAULT_STACK-1 ] = "#DF",
|
||||
[ STACKFAULT_STACK-1 ] = "#SS",
|
||||
[ MCE_STACK-1 ] = "#MC",
|
||||
#if DEBUG_STKSZ > EXCEPTION_STKSZ
|
||||
[ N_EXCEPTION_STACKS ...
|
||||
|
@ -828,9 +828,15 @@ ENTRY(native_iret)
|
||||
jnz native_irq_return_ldt
|
||||
#endif
|
||||
|
||||
.global native_irq_return_iret
|
||||
native_irq_return_iret:
|
||||
/*
|
||||
* This may fault. Non-paranoid faults on return to userspace are
|
||||
* handled by fixup_bad_iret. These include #SS, #GP, and #NP.
|
||||
* Double-faults due to espfix64 are handled in do_double_fault.
|
||||
* Other faults here are fatal.
|
||||
*/
|
||||
iretq
|
||||
_ASM_EXTABLE(native_irq_return_iret, bad_iret)
|
||||
|
||||
#ifdef CONFIG_X86_ESPFIX64
|
||||
native_irq_return_ldt:
|
||||
@ -858,25 +864,6 @@ native_irq_return_ldt:
|
||||
jmp native_irq_return_iret
|
||||
#endif
|
||||
|
||||
.section .fixup,"ax"
|
||||
bad_iret:
|
||||
/*
|
||||
* The iret traps when the %cs or %ss being restored is bogus.
|
||||
* We've lost the original trap vector and error code.
|
||||
* #GPF is the most likely one to get for an invalid selector.
|
||||
* So pretend we completed the iret and took the #GPF in user mode.
|
||||
*
|
||||
* We are now running with the kernel GS after exception recovery.
|
||||
* But error_entry expects us to have user GS to match the user %cs,
|
||||
* so swap back.
|
||||
*/
|
||||
pushq $0
|
||||
|
||||
SWAPGS
|
||||
jmp general_protection
|
||||
|
||||
.previous
|
||||
|
||||
/* edi: workmask, edx: work */
|
||||
retint_careful:
|
||||
CFI_RESTORE_STATE
|
||||
@ -922,37 +909,6 @@ ENTRY(retint_kernel)
|
||||
CFI_ENDPROC
|
||||
END(common_interrupt)
|
||||
|
||||
/*
|
||||
* If IRET takes a fault on the espfix stack, then we
|
||||
* end up promoting it to a doublefault. In that case,
|
||||
* modify the stack to make it look like we just entered
|
||||
* the #GP handler from user space, similar to bad_iret.
|
||||
*/
|
||||
#ifdef CONFIG_X86_ESPFIX64
|
||||
ALIGN
|
||||
__do_double_fault:
|
||||
XCPT_FRAME 1 RDI+8
|
||||
movq RSP(%rdi),%rax /* Trap on the espfix stack? */
|
||||
sarq $PGDIR_SHIFT,%rax
|
||||
cmpl $ESPFIX_PGD_ENTRY,%eax
|
||||
jne do_double_fault /* No, just deliver the fault */
|
||||
cmpl $__KERNEL_CS,CS(%rdi)
|
||||
jne do_double_fault
|
||||
movq RIP(%rdi),%rax
|
||||
cmpq $native_irq_return_iret,%rax
|
||||
jne do_double_fault /* This shouldn't happen... */
|
||||
movq PER_CPU_VAR(kernel_stack),%rax
|
||||
subq $(6*8-KERNEL_STACK_OFFSET),%rax /* Reset to original stack */
|
||||
movq %rax,RSP(%rdi)
|
||||
movq $0,(%rax) /* Missing (lost) #GP error code */
|
||||
movq $general_protection,RIP(%rdi)
|
||||
retq
|
||||
CFI_ENDPROC
|
||||
END(__do_double_fault)
|
||||
#else
|
||||
# define __do_double_fault do_double_fault
|
||||
#endif
|
||||
|
||||
/*
|
||||
* APIC interrupts.
|
||||
*/
|
||||
@ -1124,7 +1080,7 @@ idtentry overflow do_overflow has_error_code=0
|
||||
idtentry bounds do_bounds has_error_code=0
|
||||
idtentry invalid_op do_invalid_op has_error_code=0
|
||||
idtentry device_not_available do_device_not_available has_error_code=0
|
||||
idtentry double_fault __do_double_fault has_error_code=1 paranoid=1
|
||||
idtentry double_fault do_double_fault has_error_code=1 paranoid=1
|
||||
idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
|
||||
idtentry invalid_TSS do_invalid_TSS has_error_code=1
|
||||
idtentry segment_not_present do_segment_not_present has_error_code=1
|
||||
@ -1289,7 +1245,7 @@ apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
|
||||
|
||||
idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
|
||||
idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
|
||||
idtentry stack_segment do_stack_segment has_error_code=1 paranoid=1
|
||||
idtentry stack_segment do_stack_segment has_error_code=1
|
||||
#ifdef CONFIG_XEN
|
||||
idtentry xen_debug do_debug has_error_code=0
|
||||
idtentry xen_int3 do_int3 has_error_code=0
|
||||
@ -1399,17 +1355,16 @@ error_sti:
|
||||
|
||||
/*
|
||||
* There are two places in the kernel that can potentially fault with
|
||||
* usergs. Handle them here. The exception handlers after iret run with
|
||||
* kernel gs again, so don't set the user space flag. B stepping K8s
|
||||
* sometimes report an truncated RIP for IRET exceptions returning to
|
||||
* compat mode. Check for these here too.
|
||||
* usergs. Handle them here. B stepping K8s sometimes report a
|
||||
* truncated RIP for IRET exceptions returning to compat mode. Check
|
||||
* for these here too.
|
||||
*/
|
||||
error_kernelspace:
|
||||
CFI_REL_OFFSET rcx, RCX+8
|
||||
incl %ebx
|
||||
leaq native_irq_return_iret(%rip),%rcx
|
||||
cmpq %rcx,RIP+8(%rsp)
|
||||
je error_swapgs
|
||||
je error_bad_iret
|
||||
movl %ecx,%eax /* zero extend */
|
||||
cmpq %rax,RIP+8(%rsp)
|
||||
je bstep_iret
|
||||
@ -1420,7 +1375,15 @@ error_kernelspace:
|
||||
bstep_iret:
|
||||
/* Fix truncated RIP */
|
||||
movq %rcx,RIP+8(%rsp)
|
||||
jmp error_swapgs
|
||||
/* fall through */
|
||||
|
||||
error_bad_iret:
|
||||
SWAPGS
|
||||
mov %rsp,%rdi
|
||||
call fixup_bad_iret
|
||||
mov %rax,%rsp
|
||||
decl %ebx /* Return to usergs */
|
||||
jmp error_sti
|
||||
CFI_ENDPROC
|
||||
END(error_entry)
|
||||
|
||||
|
@ -233,32 +233,40 @@ DO_ERROR(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op)
|
||||
DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",coprocessor_segment_overrun)
|
||||
DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS)
|
||||
DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present)
|
||||
#ifdef CONFIG_X86_32
|
||||
DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment)
|
||||
#endif
|
||||
DO_ERROR(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check)
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
/* Runs on IST stack */
|
||||
dotraplinkage void do_stack_segment(struct pt_regs *regs, long error_code)
|
||||
{
|
||||
enum ctx_state prev_state;
|
||||
|
||||
prev_state = exception_enter();
|
||||
if (notify_die(DIE_TRAP, "stack segment", regs, error_code,
|
||||
X86_TRAP_SS, SIGBUS) != NOTIFY_STOP) {
|
||||
preempt_conditional_sti(regs);
|
||||
do_trap(X86_TRAP_SS, SIGBUS, "stack segment", regs, error_code, NULL);
|
||||
preempt_conditional_cli(regs);
|
||||
}
|
||||
exception_exit(prev_state);
|
||||
}
|
||||
|
||||
dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code)
|
||||
{
|
||||
static const char str[] = "double fault";
|
||||
struct task_struct *tsk = current;
|
||||
|
||||
#ifdef CONFIG_X86_ESPFIX64
|
||||
extern unsigned char native_irq_return_iret[];
|
||||
|
||||
/*
|
||||
* If IRET takes a non-IST fault on the espfix64 stack, then we
|
||||
* end up promoting it to a doublefault. In that case, modify
|
||||
* the stack to make it look like we just entered the #GP
|
||||
* handler from user space, similar to bad_iret.
|
||||
*/
|
||||
if (((long)regs->sp >> PGDIR_SHIFT) == ESPFIX_PGD_ENTRY &&
|
||||
regs->cs == __KERNEL_CS &&
|
||||
regs->ip == (unsigned long)native_irq_return_iret)
|
||||
{
|
||||
struct pt_regs *normal_regs = task_pt_regs(current);
|
||||
|
||||
/* Fake a #GP(0) from userspace. */
|
||||
memmove(&normal_regs->ip, (void *)regs->sp, 5*8);
|
||||
normal_regs->orig_ax = 0; /* Missing (lost) #GP error code */
|
||||
regs->ip = (unsigned long)general_protection;
|
||||
regs->sp = (unsigned long)&normal_regs->orig_ax;
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
exception_enter();
|
||||
/* Return not checked because double check cannot be ignored */
|
||||
notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
|
||||
@ -399,6 +407,35 @@ asmlinkage __visible struct pt_regs *sync_regs(struct pt_regs *eregs)
|
||||
return regs;
|
||||
}
|
||||
NOKPROBE_SYMBOL(sync_regs);
|
||||
|
||||
struct bad_iret_stack {
|
||||
void *error_entry_ret;
|
||||
struct pt_regs regs;
|
||||
};
|
||||
|
||||
asmlinkage __visible
|
||||
struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
|
||||
{
|
||||
/*
|
||||
* This is called from entry_64.S early in handling a fault
|
||||
* caused by a bad iret to user mode. To handle the fault
|
||||
* correctly, we want move our stack frame to task_pt_regs
|
||||
* and we want to pretend that the exception came from the
|
||||
* iret target.
|
||||
*/
|
||||
struct bad_iret_stack *new_stack =
|
||||
container_of(task_pt_regs(current),
|
||||
struct bad_iret_stack, regs);
|
||||
|
||||
/* Copy the IRET target to the new stack. */
|
||||
memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8);
|
||||
|
||||
/* Copy the remainder of the stack from the current stack. */
|
||||
memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip));
|
||||
|
||||
BUG_ON(!user_mode_vm(&new_stack->regs));
|
||||
return new_stack;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
@ -778,7 +815,7 @@ void __init trap_init(void)
|
||||
set_intr_gate(X86_TRAP_OLD_MF, coprocessor_segment_overrun);
|
||||
set_intr_gate(X86_TRAP_TS, invalid_TSS);
|
||||
set_intr_gate(X86_TRAP_NP, segment_not_present);
|
||||
set_intr_gate_ist(X86_TRAP_SS, &stack_segment, STACKFAULT_STACK);
|
||||
set_intr_gate(X86_TRAP_SS, stack_segment);
|
||||
set_intr_gate(X86_TRAP_GP, general_protection);
|
||||
set_intr_gate(X86_TRAP_SPURIOUS, spurious_interrupt_bug);
|
||||
set_intr_gate(X86_TRAP_MF, coprocessor_error);
|
||||
|
@ -630,7 +630,7 @@ static int mmu_spte_clear_track_bits(u64 *sptep)
|
||||
* kvm mmu, before reclaiming the page, we should
|
||||
* unmap it from mmu first.
|
||||
*/
|
||||
WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
|
||||
WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
|
||||
|
||||
if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
|
||||
kvm_set_pfn_accessed(pfn);
|
||||
@ -2461,7 +2461,7 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
|
||||
spte |= PT_PAGE_SIZE_MASK;
|
||||
if (tdp_enabled)
|
||||
spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
|
||||
kvm_is_mmio_pfn(pfn));
|
||||
kvm_is_reserved_pfn(pfn));
|
||||
|
||||
if (host_writable)
|
||||
spte |= SPTE_HOST_WRITEABLE;
|
||||
@ -2737,7 +2737,7 @@ static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
|
||||
* PT_PAGE_TABLE_LEVEL and there would be no adjustment done
|
||||
* here.
|
||||
*/
|
||||
if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
|
||||
if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
|
||||
level == PT_PAGE_TABLE_LEVEL &&
|
||||
PageTransCompound(pfn_to_page(pfn)) &&
|
||||
!has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
|
||||
|
@ -1225,11 +1225,13 @@ static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
|
||||
if (!card->config_regs) {
|
||||
dev_warn(&dev->dev, "Failed to ioremap config registers\n");
|
||||
err = -ENOMEM;
|
||||
goto out_release_regions;
|
||||
}
|
||||
card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
|
||||
if (!card->buffers) {
|
||||
dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
|
||||
err = -ENOMEM;
|
||||
goto out_unmap_config;
|
||||
}
|
||||
|
||||
|
@ -52,29 +52,26 @@ static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw,
|
||||
|
||||
tmp = pmc_read(pmc, AT91_PMC_USB);
|
||||
usbdiv = (tmp & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT;
|
||||
return parent_rate / (usbdiv + 1);
|
||||
|
||||
return DIV_ROUND_CLOSEST(parent_rate, (usbdiv + 1));
|
||||
}
|
||||
|
||||
static long at91sam9x5_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
unsigned long div;
|
||||
unsigned long bestrate;
|
||||
unsigned long tmp;
|
||||
|
||||
if (!rate)
|
||||
return -EINVAL;
|
||||
|
||||
if (rate >= *parent_rate)
|
||||
return *parent_rate;
|
||||
|
||||
div = *parent_rate / rate;
|
||||
if (div >= SAM9X5_USB_MAX_DIV)
|
||||
return *parent_rate / (SAM9X5_USB_MAX_DIV + 1);
|
||||
div = DIV_ROUND_CLOSEST(*parent_rate, rate);
|
||||
if (div > SAM9X5_USB_MAX_DIV + 1)
|
||||
div = SAM9X5_USB_MAX_DIV + 1;
|
||||
|
||||
bestrate = *parent_rate / div;
|
||||
tmp = *parent_rate / (div + 1);
|
||||
if (bestrate - rate > rate - tmp)
|
||||
bestrate = tmp;
|
||||
|
||||
return bestrate;
|
||||
return DIV_ROUND_CLOSEST(*parent_rate, div);
|
||||
}
|
||||
|
||||
static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index)
|
||||
@ -106,9 +103,13 @@ static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
u32 tmp;
|
||||
struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
|
||||
struct at91_pmc *pmc = usb->pmc;
|
||||
unsigned long div = parent_rate / rate;
|
||||
unsigned long div;
|
||||
|
||||
if (parent_rate % rate || div < 1 || div >= SAM9X5_USB_MAX_DIV)
|
||||
if (!rate)
|
||||
return -EINVAL;
|
||||
|
||||
div = DIV_ROUND_CLOSEST(parent_rate, rate);
|
||||
if (div > SAM9X5_USB_MAX_DIV + 1 || !div)
|
||||
return -EINVAL;
|
||||
|
||||
tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_OHCIUSBDIV;
|
||||
@ -253,7 +254,7 @@ static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
||||
tmp_parent_rate = rate * usb->divisors[i];
|
||||
tmp_parent_rate = __clk_round_rate(parent, tmp_parent_rate);
|
||||
tmprate = tmp_parent_rate / usb->divisors[i];
|
||||
tmprate = DIV_ROUND_CLOSEST(tmp_parent_rate, usb->divisors[i]);
|
||||
if (tmprate < rate)
|
||||
tmpdiff = rate - tmprate;
|
||||
else
|
||||
@ -281,10 +282,10 @@ static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
struct at91_pmc *pmc = usb->pmc;
|
||||
unsigned long div;
|
||||
|
||||
if (!rate || parent_rate % rate)
|
||||
if (!rate)
|
||||
return -EINVAL;
|
||||
|
||||
div = parent_rate / rate;
|
||||
div = DIV_ROUND_CLOSEST(parent_rate, rate);
|
||||
|
||||
for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) {
|
||||
if (usb->divisors[i] == div) {
|
||||
|
@ -263,6 +263,14 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
|
||||
if (!rate)
|
||||
rate = 1;
|
||||
|
||||
/* if read only, just return current value */
|
||||
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
|
||||
bestdiv = readl(divider->reg) >> divider->shift;
|
||||
bestdiv &= div_mask(divider);
|
||||
bestdiv = _get_div(divider, bestdiv);
|
||||
return bestdiv;
|
||||
}
|
||||
|
||||
maxdiv = _get_maxdiv(divider);
|
||||
|
||||
if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
|
||||
@ -361,11 +369,6 @@ const struct clk_ops clk_divider_ops = {
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_divider_ops);
|
||||
|
||||
const struct clk_ops clk_divider_ro_ops = {
|
||||
.recalc_rate = clk_divider_recalc_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
|
||||
|
||||
static struct clk *_register_divider(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
@ -391,10 +394,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
|
||||
init.ops = &clk_divider_ro_ops;
|
||||
else
|
||||
init.ops = &clk_divider_ops;
|
||||
init.ops = &clk_divider_ops;
|
||||
init.flags = flags | CLK_IS_BASIC;
|
||||
init.parent_names = (parent_name ? &parent_name: NULL);
|
||||
init.num_parents = (parent_name ? 1 : 0);
|
||||
|
@ -322,7 +322,7 @@ static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
|
||||
unsigned long ccsr = CCSR;
|
||||
|
||||
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
|
||||
a = cccr & CCCR_A_BIT;
|
||||
a = cccr & (1 << CCCR_A_BIT);
|
||||
l = ccsr & CCSR_L_MASK;
|
||||
|
||||
if (osc_forced || a)
|
||||
@ -341,7 +341,7 @@ static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
|
||||
unsigned long ccsr = CCSR;
|
||||
|
||||
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
|
||||
a = cccr & CCCR_A_BIT;
|
||||
a = cccr & (1 << CCCR_A_BIT);
|
||||
if (osc_forced)
|
||||
return PXA_MEM_13Mhz;
|
||||
if (a)
|
||||
|
@ -3122,7 +3122,7 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = {
|
||||
[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
|
||||
[HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
|
||||
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
|
||||
[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
|
||||
[MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
|
||||
[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
|
||||
[MAPLE_CLK_SRC] = &maple_clk_src.clkr,
|
||||
[VDP_CLK_SRC] = &vdp_clk_src.clkr,
|
||||
|
@ -90,9 +90,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
|
||||
div->width = div_width;
|
||||
div->lock = lock;
|
||||
div->table = div_table;
|
||||
div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
|
||||
? &clk_divider_ro_ops
|
||||
: &clk_divider_ops;
|
||||
div_ops = &clk_divider_ops;
|
||||
}
|
||||
|
||||
clk = clk_register_composite(NULL, name, parent_names, num_parents,
|
||||
|
@ -182,6 +182,12 @@ static void __init sun4i_timer_init(struct device_node *node)
|
||||
/* Make sure timer is stopped before playing with interrupts */
|
||||
sun4i_clkevt_time_stop(0);
|
||||
|
||||
sun4i_clockevent.cpumask = cpu_possible_mask;
|
||||
sun4i_clockevent.irq = irq;
|
||||
|
||||
clockevents_config_and_register(&sun4i_clockevent, rate,
|
||||
TIMER_SYNC_TICKS, 0xffffffff);
|
||||
|
||||
ret = setup_irq(irq, &sun4i_timer_irq);
|
||||
if (ret)
|
||||
pr_warn("failed to setup irq %d\n", irq);
|
||||
@ -189,12 +195,6 @@ static void __init sun4i_timer_init(struct device_node *node)
|
||||
/* Enable timer0 interrupt */
|
||||
val = readl(timer_base + TIMER_IRQ_EN_REG);
|
||||
writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
|
||||
|
||||
sun4i_clockevent.cpumask = cpu_possible_mask;
|
||||
sun4i_clockevent.irq = irq;
|
||||
|
||||
clockevents_config_and_register(&sun4i_clockevent, rate,
|
||||
TIMER_SYNC_TICKS, 0xffffffff);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
|
||||
sun4i_timer_init);
|
||||
|
@ -185,6 +185,16 @@ static bool radeon_msi_ok(struct radeon_device *rdev)
|
||||
if (rdev->flags & RADEON_IS_AGP)
|
||||
return false;
|
||||
|
||||
/*
|
||||
* Older chips have a HW limitation, they can only generate 40 bits
|
||||
* of address for "64-bit" MSIs which breaks on some platforms, notably
|
||||
* IBM POWER servers, so we limit them
|
||||
*/
|
||||
if (rdev->family < CHIP_BONAIRE) {
|
||||
dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
|
||||
rdev->pdev->no_64bit_msi = 1;
|
||||
}
|
||||
|
||||
/* force MSI on */
|
||||
if (radeon_msi == 1)
|
||||
return true;
|
||||
|
@ -1084,10 +1084,8 @@ static int g762_probe(struct i2c_client *client, const struct i2c_device_id *id)
|
||||
if (ret)
|
||||
goto clock_dis;
|
||||
|
||||
data->hwmon_dev = devm_hwmon_device_register_with_groups(dev,
|
||||
client->name,
|
||||
data,
|
||||
g762_groups);
|
||||
data->hwmon_dev = hwmon_device_register_with_groups(dev, client->name,
|
||||
data, g762_groups);
|
||||
if (IS_ERR(data->hwmon_dev)) {
|
||||
ret = PTR_ERR(data->hwmon_dev);
|
||||
goto clock_dis;
|
||||
|
@ -44,6 +44,9 @@
|
||||
|
||||
#define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
|
||||
#define BMC150_ACCEL_ANY_MOTION_MASK 0x07
|
||||
#define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
|
||||
#define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
|
||||
#define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
|
||||
#define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
|
||||
|
||||
#define BMC150_ACCEL_REG_PMU_LPW 0x11
|
||||
@ -92,9 +95,9 @@
|
||||
#define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
|
||||
|
||||
/* Slope duration in terms of number of samples */
|
||||
#define BMC150_ACCEL_DEF_SLOPE_DURATION 2
|
||||
#define BMC150_ACCEL_DEF_SLOPE_DURATION 1
|
||||
/* in terms of multiples of g's/LSB, based on range */
|
||||
#define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 5
|
||||
#define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
|
||||
|
||||
#define BMC150_ACCEL_REG_XOUT_L 0x02
|
||||
|
||||
@ -536,6 +539,9 @@ static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
|
||||
if (ret < 0) {
|
||||
dev_err(&data->client->dev,
|
||||
"Failed: bmc150_accel_set_power_state for %d\n", on);
|
||||
if (on)
|
||||
pm_runtime_put_noidle(&data->client->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -811,6 +817,7 @@ static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
|
||||
|
||||
ret = bmc150_accel_setup_any_motion_interrupt(data, state);
|
||||
if (ret < 0) {
|
||||
bmc150_accel_set_power_state(data, false);
|
||||
mutex_unlock(&data->mutex);
|
||||
return ret;
|
||||
}
|
||||
@ -846,7 +853,7 @@ static const struct attribute_group bmc150_accel_attrs_group = {
|
||||
|
||||
static const struct iio_event_spec bmc150_accel_event = {
|
||||
.type = IIO_EV_TYPE_ROC,
|
||||
.dir = IIO_EV_DIR_RISING | IIO_EV_DIR_FALLING,
|
||||
.dir = IIO_EV_DIR_EITHER,
|
||||
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
|
||||
BIT(IIO_EV_INFO_ENABLE) |
|
||||
BIT(IIO_EV_INFO_PERIOD)
|
||||
@ -1054,6 +1061,7 @@ static int bmc150_accel_data_rdy_trigger_set_state(struct iio_trigger *trig,
|
||||
else
|
||||
ret = bmc150_accel_setup_new_data_interrupt(data, state);
|
||||
if (ret < 0) {
|
||||
bmc150_accel_set_power_state(data, false);
|
||||
mutex_unlock(&data->mutex);
|
||||
return ret;
|
||||
}
|
||||
@ -1092,12 +1100,26 @@ static irqreturn_t bmc150_accel_event_handler(int irq, void *private)
|
||||
else
|
||||
dir = IIO_EV_DIR_RISING;
|
||||
|
||||
if (ret & BMC150_ACCEL_ANY_MOTION_MASK)
|
||||
if (ret & BMC150_ACCEL_ANY_MOTION_BIT_X)
|
||||
iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL,
|
||||
0,
|
||||
IIO_MOD_X_OR_Y_OR_Z,
|
||||
IIO_MOD_X,
|
||||
IIO_EV_TYPE_ROC,
|
||||
IIO_EV_DIR_EITHER),
|
||||
dir),
|
||||
data->timestamp);
|
||||
if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Y)
|
||||
iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL,
|
||||
0,
|
||||
IIO_MOD_Y,
|
||||
IIO_EV_TYPE_ROC,
|
||||
dir),
|
||||
data->timestamp);
|
||||
if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Z)
|
||||
iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL,
|
||||
0,
|
||||
IIO_MOD_Z,
|
||||
IIO_EV_TYPE_ROC,
|
||||
dir),
|
||||
data->timestamp);
|
||||
ack_intr_status:
|
||||
if (!data->dready_trigger_on)
|
||||
@ -1354,10 +1376,14 @@ static int bmc150_accel_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
|
||||
struct bmc150_accel_data *data = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
dev_dbg(&data->client->dev, __func__);
|
||||
ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
|
||||
if (ret < 0)
|
||||
return -EAGAIN;
|
||||
|
||||
return bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bmc150_accel_runtime_resume(struct device *dev)
|
||||
|
@ -269,6 +269,8 @@ static int kxcjk1013_set_range(struct kxcjk1013_data *data, int range_index)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret &= ~(KXCJK1013_REG_CTRL1_BIT_GSEL0 |
|
||||
KXCJK1013_REG_CTRL1_BIT_GSEL1);
|
||||
ret |= (KXCJK1013_scale_table[range_index].gsel_0 << 3);
|
||||
ret |= (KXCJK1013_scale_table[range_index].gsel_1 << 4);
|
||||
|
||||
|
@ -152,6 +152,7 @@ static void men_z188_remove(struct mcb_device *dev)
|
||||
|
||||
static const struct mcb_device_id men_z188_ids[] = {
|
||||
{ .device = 0xbc },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(mcb, men_z188_ids);
|
||||
|
||||
|
@ -67,6 +67,9 @@
|
||||
#define BMG160_REG_INT_EN_0 0x15
|
||||
#define BMG160_DATA_ENABLE_INT BIT(7)
|
||||
|
||||
#define BMG160_REG_INT_EN_1 0x16
|
||||
#define BMG160_INT1_BIT_OD BIT(1)
|
||||
|
||||
#define BMG160_REG_XOUT_L 0x02
|
||||
#define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2))
|
||||
|
||||
@ -82,6 +85,9 @@
|
||||
|
||||
#define BMG160_REG_INT_STATUS_2 0x0B
|
||||
#define BMG160_ANY_MOTION_MASK 0x07
|
||||
#define BMG160_ANY_MOTION_BIT_X BIT(0)
|
||||
#define BMG160_ANY_MOTION_BIT_Y BIT(1)
|
||||
#define BMG160_ANY_MOTION_BIT_Z BIT(2)
|
||||
|
||||
#define BMG160_REG_TEMP 0x08
|
||||
#define BMG160_TEMP_CENTER_VAL 23
|
||||
@ -222,6 +228,19 @@ static int bmg160_chip_init(struct bmg160_data *data)
|
||||
data->slope_thres = ret;
|
||||
|
||||
/* Set default interrupt mode */
|
||||
ret = i2c_smbus_read_byte_data(data->client, BMG160_REG_INT_EN_1);
|
||||
if (ret < 0) {
|
||||
dev_err(&data->client->dev, "Error reading reg_int_en_1\n");
|
||||
return ret;
|
||||
}
|
||||
ret &= ~BMG160_INT1_BIT_OD;
|
||||
ret = i2c_smbus_write_byte_data(data->client,
|
||||
BMG160_REG_INT_EN_1, ret);
|
||||
if (ret < 0) {
|
||||
dev_err(&data->client->dev, "Error writing reg_int_en_1\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = i2c_smbus_write_byte_data(data->client,
|
||||
BMG160_REG_INT_RST_LATCH,
|
||||
BMG160_INT_MODE_LATCH_INT |
|
||||
@ -250,6 +269,9 @@ static int bmg160_set_power_state(struct bmg160_data *data, bool on)
|
||||
if (ret < 0) {
|
||||
dev_err(&data->client->dev,
|
||||
"Failed: bmg160_set_power_state for %d\n", on);
|
||||
if (on)
|
||||
pm_runtime_put_noidle(&data->client->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
@ -705,6 +727,7 @@ static int bmg160_write_event_config(struct iio_dev *indio_dev,
|
||||
|
||||
ret = bmg160_setup_any_motion_interrupt(data, state);
|
||||
if (ret < 0) {
|
||||
bmg160_set_power_state(data, false);
|
||||
mutex_unlock(&data->mutex);
|
||||
return ret;
|
||||
}
|
||||
@ -743,7 +766,7 @@ static const struct attribute_group bmg160_attrs_group = {
|
||||
|
||||
static const struct iio_event_spec bmg160_event = {
|
||||
.type = IIO_EV_TYPE_ROC,
|
||||
.dir = IIO_EV_DIR_RISING | IIO_EV_DIR_FALLING,
|
||||
.dir = IIO_EV_DIR_EITHER,
|
||||
.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
|
||||
BIT(IIO_EV_INFO_ENABLE)
|
||||
};
|
||||
@ -871,6 +894,7 @@ static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig,
|
||||
else
|
||||
ret = bmg160_setup_new_data_interrupt(data, state);
|
||||
if (ret < 0) {
|
||||
bmg160_set_power_state(data, false);
|
||||
mutex_unlock(&data->mutex);
|
||||
return ret;
|
||||
}
|
||||
@ -908,10 +932,24 @@ static irqreturn_t bmg160_event_handler(int irq, void *private)
|
||||
else
|
||||
dir = IIO_EV_DIR_FALLING;
|
||||
|
||||
if (ret & BMG160_ANY_MOTION_MASK)
|
||||
if (ret & BMG160_ANY_MOTION_BIT_X)
|
||||
iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
|
||||
0,
|
||||
IIO_MOD_X_OR_Y_OR_Z,
|
||||
IIO_MOD_X,
|
||||
IIO_EV_TYPE_ROC,
|
||||
dir),
|
||||
data->timestamp);
|
||||
if (ret & BMG160_ANY_MOTION_BIT_Y)
|
||||
iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
|
||||
0,
|
||||
IIO_MOD_Y,
|
||||
IIO_EV_TYPE_ROC,
|
||||
dir),
|
||||
data->timestamp);
|
||||
if (ret & BMG160_ANY_MOTION_BIT_Z)
|
||||
iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
|
||||
0,
|
||||
IIO_MOD_Z,
|
||||
IIO_EV_TYPE_ROC,
|
||||
dir),
|
||||
data->timestamp);
|
||||
@ -1169,8 +1207,15 @@ static int bmg160_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
|
||||
struct bmg160_data *data = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
return bmg160_set_mode(data, BMG160_MODE_SUSPEND);
|
||||
ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND);
|
||||
if (ret < 0) {
|
||||
dev_err(&data->client->dev, "set mode failed\n");
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bmg160_runtime_resume(struct device *dev)
|
||||
|
@ -1179,9 +1179,19 @@ static int xpad_probe(struct usb_interface *intf, const struct usb_device_id *id
|
||||
}
|
||||
|
||||
ep_irq_in = &intf->cur_altsetting->endpoint[1].desc;
|
||||
usb_fill_bulk_urb(xpad->bulk_out, udev,
|
||||
usb_sndbulkpipe(udev, ep_irq_in->bEndpointAddress),
|
||||
xpad->bdata, XPAD_PKT_LEN, xpad_bulk_out, xpad);
|
||||
if (usb_endpoint_is_bulk_out(ep_irq_in)) {
|
||||
usb_fill_bulk_urb(xpad->bulk_out, udev,
|
||||
usb_sndbulkpipe(udev,
|
||||
ep_irq_in->bEndpointAddress),
|
||||
xpad->bdata, XPAD_PKT_LEN,
|
||||
xpad_bulk_out, xpad);
|
||||
} else {
|
||||
usb_fill_int_urb(xpad->bulk_out, udev,
|
||||
usb_sndintpipe(udev,
|
||||
ep_irq_in->bEndpointAddress),
|
||||
xpad->bdata, XPAD_PKT_LEN,
|
||||
xpad_bulk_out, xpad, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Submit the int URB immediately rather than waiting for open
|
||||
|
@ -428,14 +428,6 @@ static void elantech_report_trackpoint(struct psmouse *psmouse,
|
||||
int x, y;
|
||||
u32 t;
|
||||
|
||||
if (dev_WARN_ONCE(&psmouse->ps2dev.serio->dev,
|
||||
!tp_dev,
|
||||
psmouse_fmt("Unexpected trackpoint message\n"))) {
|
||||
if (etd->debug == 1)
|
||||
elantech_packet_dump(psmouse);
|
||||
return;
|
||||
}
|
||||
|
||||
t = get_unaligned_le32(&packet[0]);
|
||||
|
||||
switch (t & ~7U) {
|
||||
@ -793,7 +785,7 @@ static int elantech_packet_check_v4(struct psmouse *psmouse)
|
||||
unsigned char packet_type = packet[3] & 0x03;
|
||||
bool sanity_check;
|
||||
|
||||
if ((packet[3] & 0x0f) == 0x06)
|
||||
if (etd->tp_dev && (packet[3] & 0x0f) == 0x06)
|
||||
return PACKET_TRACKPOINT;
|
||||
|
||||
/*
|
||||
|
@ -143,6 +143,10 @@ static const struct min_max_quirk min_max_pnpid_table[] = {
|
||||
(const char * const []){"LEN2001", NULL},
|
||||
1024, 5022, 2508, 4832
|
||||
},
|
||||
{
|
||||
(const char * const []){"LEN2006", NULL},
|
||||
1264, 5675, 1171, 4688
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
|
@ -217,8 +217,9 @@ struct irq_domain *__init aic_common_of_init(struct device_node *node,
|
||||
}
|
||||
|
||||
ret = irq_alloc_domain_generic_chips(domain, 32, 1, name,
|
||||
handle_level_irq, 0, 0,
|
||||
IRQCHIP_SKIP_SET_WAKE);
|
||||
handle_fasteoi_irq,
|
||||
IRQ_NOREQUEST | IRQ_NOPROBE |
|
||||
IRQ_NOAUTOEN, 0, 0);
|
||||
if (ret)
|
||||
goto err_domain_remove;
|
||||
|
||||
@ -230,7 +231,6 @@ struct irq_domain *__init aic_common_of_init(struct device_node *node,
|
||||
gc->unused = 0;
|
||||
gc->wake_enabled = ~0;
|
||||
gc->chip_types[0].type = IRQ_TYPE_SENSE_MASK;
|
||||
gc->chip_types[0].handler = handle_fasteoi_irq;
|
||||
gc->chip_types[0].chip.irq_eoi = irq_gc_eoi;
|
||||
gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
|
||||
gc->chip_types[0].chip.irq_shutdown = aic_common_shutdown;
|
||||
|
@ -101,9 +101,9 @@ static int bcm7120_l2_intc_init_one(struct device_node *dn,
|
||||
int parent_irq;
|
||||
|
||||
parent_irq = irq_of_parse_and_map(dn, irq);
|
||||
if (parent_irq < 0) {
|
||||
if (!parent_irq) {
|
||||
pr_err("failed to map interrupt %d\n", irq);
|
||||
return parent_irq;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
data->irq_map_mask |= be32_to_cpup(map_mask + irq);
|
||||
|
@ -135,9 +135,9 @@ int __init brcmstb_l2_intc_of_init(struct device_node *np,
|
||||
__raw_writel(0xffffffff, data->base + CPU_CLEAR);
|
||||
|
||||
data->parent_irq = irq_of_parse_and_map(np, 0);
|
||||
if (data->parent_irq < 0) {
|
||||
if (!data->parent_irq) {
|
||||
pr_err("failed to find parent interrupt\n");
|
||||
ret = data->parent_irq;
|
||||
ret = -EINVAL;
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
|
@ -377,6 +377,29 @@ static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
|
||||
{
|
||||
unsigned int timeout = 1000;
|
||||
u32 reg;
|
||||
|
||||
reg = core_readl(priv, CORE_WATCHDOG_CTRL);
|
||||
reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
|
||||
core_writel(priv, reg, CORE_WATCHDOG_CTRL);
|
||||
|
||||
do {
|
||||
reg = core_readl(priv, CORE_WATCHDOG_CTRL);
|
||||
if (!(reg & SOFTWARE_RESET))
|
||||
break;
|
||||
|
||||
usleep_range(1000, 2000);
|
||||
} while (timeout-- > 0);
|
||||
|
||||
if (timeout == 0)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm_sf2_sw_setup(struct dsa_switch *ds)
|
||||
{
|
||||
const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
|
||||
@ -404,11 +427,18 @@ static int bcm_sf2_sw_setup(struct dsa_switch *ds)
|
||||
*base = of_iomap(dn, i);
|
||||
if (*base == NULL) {
|
||||
pr_err("unable to find register: %s\n", reg_names[i]);
|
||||
return -ENODEV;
|
||||
ret = -ENOMEM;
|
||||
goto out_unmap;
|
||||
}
|
||||
base++;
|
||||
}
|
||||
|
||||
ret = bcm_sf2_sw_rst(priv);
|
||||
if (ret) {
|
||||
pr_err("unable to software reset switch: %d\n", ret);
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
/* Disable all interrupts and request them */
|
||||
intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
|
||||
intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
|
||||
@ -484,7 +514,8 @@ out_free_irq0:
|
||||
out_unmap:
|
||||
base = &priv->core;
|
||||
for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
|
||||
iounmap(*base);
|
||||
if (*base)
|
||||
iounmap(*base);
|
||||
base++;
|
||||
}
|
||||
return ret;
|
||||
@ -733,29 +764,6 @@ static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
|
||||
{
|
||||
unsigned int timeout = 1000;
|
||||
u32 reg;
|
||||
|
||||
reg = core_readl(priv, CORE_WATCHDOG_CTRL);
|
||||
reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
|
||||
core_writel(priv, reg, CORE_WATCHDOG_CTRL);
|
||||
|
||||
do {
|
||||
reg = core_readl(priv, CORE_WATCHDOG_CTRL);
|
||||
if (!(reg & SOFTWARE_RESET))
|
||||
break;
|
||||
|
||||
usleep_range(1000, 2000);
|
||||
} while (timeout-- > 0);
|
||||
|
||||
if (timeout == 0)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm_sf2_sw_resume(struct dsa_switch *ds)
|
||||
{
|
||||
struct bcm_sf2_priv *priv = ds_to_priv(ds);
|
||||
|
@ -8563,7 +8563,8 @@ static int tg3_init_rings(struct tg3 *tp)
|
||||
if (tnapi->rx_rcb)
|
||||
memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
|
||||
|
||||
if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
|
||||
if (tnapi->prodring.rx_std &&
|
||||
tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
|
||||
tg3_free_rings(tp);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user