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drm/amd/powerplay: correct Navi10 VCN powergate control (v2)

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No VCN DPM bit check as that's different from VCN PG. Also
no extra check for possible double enablement/disablement
as that's already done by VCN.

v2: check return value of smu_feature_set_enabled

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
2019-07-22 10:27:21 +08:00
committed by Alex Deucher
parent bf2bf52383
commit 5fa790f6c9
1 changed files with 10 additions and 18 deletions
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16
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
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@@ -592,28 +592,20 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable) static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
{ {
int ret = 0; int ret = 0;
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
if (enable && power_gate->uvd_gated) { if (enable) {
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1); ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
if (ret) if (ret)
return ret; return ret;
}
power_gate->uvd_gated = false;
} else { } else {
if (!enable && !power_gate->uvd_gated) {
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn); ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
if (ret) if (ret)
return ret; return ret;
} }
power_gate->uvd_gated = true;
}
}
return 0; ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
return ret;
} }
static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,