forked from Minki/linux
cs5535-gpio: add AMD CS5535/CS5536 GPIO driver support
This creates a CS5535/CS5536 GPIO driver which uses a gpio_chip backend (allowing GPIO users to use the generic GPIO API if desired) while also allowing architecture-specific users directly (via the cs5535_gpio_* functions). Tested on an OLPC machine. Some Leemotes also use CS5536 (with a mips cpu), which is why this is in drivers/gpio rather than arch/x86. Currently, it conflicts with older geode GPIO support; once MFGPT support is reworked to also be more generic, the older geode code will be removed. Signed-off-by: Andres Salomon <dilinger@collabora.co.uk> Cc: Takashi Iwai <tiwai@suse.de> Cc: Jordan Crouse <jordan@cosmicpenguin.net> Cc: David Brownell <david-b@pacbell.net> Reviewed-by: Alessandro Zummo <a.zummo@towertech.it> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Andres Salomon
Linus Torvalds
parent
1f2f38d89d
commit
5f0a96b044
@ -12,6 +12,7 @@
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#include <asm/processor.h>
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#include <linux/io.h>
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#include <linux/cs5535.h>
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/* Generic southbridge functions */
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@ -115,33 +116,6 @@ extern int geode_get_dev_base(unsigned int dev);
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#define VSA_VR_MEM_SIZE 0x0200
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#define AMD_VSA_SIG 0x4132 /* signature is ascii 'VSA2' */
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#define GSW_VSA_SIG 0x534d /* General Software signature */
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/* GPIO */
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#define GPIO_OUTPUT_VAL 0x00
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#define GPIO_OUTPUT_ENABLE 0x04
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#define GPIO_OUTPUT_OPEN_DRAIN 0x08
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#define GPIO_OUTPUT_INVERT 0x0C
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#define GPIO_OUTPUT_AUX1 0x10
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#define GPIO_OUTPUT_AUX2 0x14
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#define GPIO_PULL_UP 0x18
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#define GPIO_PULL_DOWN 0x1C
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#define GPIO_INPUT_ENABLE 0x20
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#define GPIO_INPUT_INVERT 0x24
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#define GPIO_INPUT_FILTER 0x28
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#define GPIO_INPUT_EVENT_COUNT 0x2C
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#define GPIO_READ_BACK 0x30
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#define GPIO_INPUT_AUX1 0x34
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#define GPIO_EVENTS_ENABLE 0x38
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#define GPIO_LOCK_ENABLE 0x3C
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#define GPIO_POSITIVE_EDGE_EN 0x40
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#define GPIO_NEGATIVE_EDGE_EN 0x44
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#define GPIO_POSITIVE_EDGE_STS 0x48
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#define GPIO_NEGATIVE_EDGE_STS 0x4C
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#define GPIO_MAP_X 0xE0
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#define GPIO_MAP_Y 0xE4
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#define GPIO_MAP_Z 0xE8
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#define GPIO_MAP_W 0xEC
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static inline u32 geode_gpio(unsigned int nr)
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{
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@ -174,6 +174,16 @@ config GPIO_ADP5520
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comment "PCI GPIO expanders:"
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config GPIO_CS5535
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tristate "AMD CS5535/CS5536 GPIO support"
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depends on PCI && !CS5535_GPIO && !MGEODE_LX
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help
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The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that
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can be used for quite a number of things. The CS5535/6 is found on
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AMD Geode and Lemote Yeeloong devices.
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If unsure, say N.
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config GPIO_BT8XX
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tristate "BT8XX GPIO abuser"
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depends on PCI && VIDEO_BT848=n
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@ -16,6 +16,7 @@ obj-$(CONFIG_GPIO_PL061) += pl061.o
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obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o
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obj-$(CONFIG_GPIO_UCB1400) += ucb1400_gpio.o
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obj-$(CONFIG_GPIO_XILINX) += xilinx_gpio.o
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obj-$(CONFIG_GPIO_CS5535) += cs5535-gpio.o
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obj-$(CONFIG_GPIO_BT8XX) += bt8xxgpio.o
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obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o
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obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o
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282
drivers/gpio/cs5535-gpio.c
Normal file
282
drivers/gpio/cs5535-gpio.c
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@ -0,0 +1,282 @@
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/*
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* AMD CS5535/CS5536 GPIO driver
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* Copyright (C) 2006 Advanced Micro Devices, Inc.
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* Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/cs5535.h>
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#define DRV_NAME "cs5535-gpio"
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#define GPIO_BAR 1
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static struct cs5535_gpio_chip {
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struct gpio_chip chip;
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resource_size_t base;
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struct pci_dev *pdev;
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spinlock_t lock;
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} cs5535_gpio_chip;
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/*
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* The CS5535/CS5536 GPIOs support a number of extra features not defined
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* by the gpio_chip API, so these are exported. For a full list of the
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* registers, see include/linux/cs5535.h.
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*/
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static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
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unsigned int reg)
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{
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if (offset < 16)
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/* low bank register */
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outl(1 << offset, chip->base + reg);
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else
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/* high bank register */
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outl(1 << (offset - 16), chip->base + 0x80 + reg);
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}
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void cs5535_gpio_set(unsigned offset, unsigned int reg)
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{
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struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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__cs5535_gpio_set(chip, offset, reg);
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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EXPORT_SYMBOL_GPL(cs5535_gpio_set);
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static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset,
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unsigned int reg)
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{
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if (offset < 16)
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/* low bank register */
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outl(1 << (offset + 16), chip->base + reg);
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else
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/* high bank register */
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outl(1 << offset, chip->base + 0x80 + reg);
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}
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void cs5535_gpio_clear(unsigned offset, unsigned int reg)
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{
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struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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__cs5535_gpio_clear(chip, offset, reg);
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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EXPORT_SYMBOL_GPL(cs5535_gpio_clear);
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int cs5535_gpio_isset(unsigned offset, unsigned int reg)
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{
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struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
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unsigned long flags;
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long val;
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spin_lock_irqsave(&chip->lock, flags);
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if (offset < 16)
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/* low bank register */
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val = inl(chip->base + reg);
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else {
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/* high bank register */
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val = inl(chip->base + 0x80 + reg);
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offset -= 16;
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}
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spin_unlock_irqrestore(&chip->lock, flags);
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return (val & (1 << offset)) ? 1 : 0;
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}
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EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
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/*
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* Generic gpio_chip API support.
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*/
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static int chip_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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return cs5535_gpio_isset(offset, GPIO_OUTPUT_VAL);
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}
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static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
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{
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if (val)
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cs5535_gpio_set(offset, GPIO_OUTPUT_VAL);
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else
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cs5535_gpio_clear(offset, GPIO_OUTPUT_VAL);
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}
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static int chip_direction_input(struct gpio_chip *c, unsigned offset)
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{
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struct cs5535_gpio_chip *chip = (struct cs5535_gpio_chip *) c;
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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__cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val)
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{
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struct cs5535_gpio_chip *chip = (struct cs5535_gpio_chip *) c;
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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__cs5535_gpio_set(chip, offset, GPIO_OUTPUT_ENABLE);
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if (val)
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__cs5535_gpio_set(chip, offset, GPIO_OUTPUT_VAL);
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else
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__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_VAL);
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static struct cs5535_gpio_chip cs5535_gpio_chip = {
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.chip = {
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.owner = THIS_MODULE,
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.label = DRV_NAME,
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.base = 0,
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.ngpio = 28,
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.get = chip_gpio_get,
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.set = chip_gpio_set,
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.direction_input = chip_direction_input,
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.direction_output = chip_direction_output,
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},
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};
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static int __init cs5535_gpio_probe(struct pci_dev *pdev,
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const struct pci_device_id *pci_id)
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{
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int err;
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/* There are two ways to get the GPIO base address; one is by
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* fetching it from MSR_LBAR_GPIO, the other is by reading the
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* PCI BAR info. The latter method is easier (especially across
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* different architectures), so we'll stick with that for now. If
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* it turns out to be unreliable in the face of crappy BIOSes, we
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* can always go back to using MSRs.. */
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err = pci_enable_device_io(pdev);
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if (err) {
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dev_err(&pdev->dev, "can't enable device IO\n");
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goto done;
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}
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err = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
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if (err) {
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dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
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goto done;
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}
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/* set up the driver-specific struct */
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cs5535_gpio_chip.base = pci_resource_start(pdev, GPIO_BAR);
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cs5535_gpio_chip.pdev = pdev;
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spin_lock_init(&cs5535_gpio_chip.lock);
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dev_info(&pdev->dev, "allocated PCI BAR #%d: base 0x%llx\n", GPIO_BAR,
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(unsigned long long) cs5535_gpio_chip.base);
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/* finally, register with the generic GPIO API */
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err = gpiochip_add(&cs5535_gpio_chip.chip);
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if (err) {
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dev_err(&pdev->dev, "failed to register gpio chip\n");
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goto release_region;
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}
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printk(KERN_INFO DRV_NAME ": GPIO support successfully loaded.\n");
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return 0;
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release_region:
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pci_release_region(pdev, GPIO_BAR);
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done:
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return err;
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}
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static void __exit cs5535_gpio_remove(struct pci_dev *pdev)
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{
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int err;
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err = gpiochip_remove(&cs5535_gpio_chip.chip);
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if (err) {
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/* uhh? */
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dev_err(&pdev->dev, "unable to remove gpio_chip?\n");
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}
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pci_release_region(pdev, GPIO_BAR);
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}
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static struct pci_device_id cs5535_gpio_pci_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, cs5535_gpio_pci_tbl);
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/*
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* We can't use the standard PCI driver registration stuff here, since
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* that allows only one driver to bind to each PCI device (and we want
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* multiple drivers to be able to bind to the device). Instead, manually
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* scan for the PCI device, request a single region, and keep track of the
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* devices that we're using.
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*/
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static int __init cs5535_gpio_scan_pci(void)
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{
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struct pci_dev *pdev;
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int err = -ENODEV;
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int i;
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for (i = 0; i < ARRAY_SIZE(cs5535_gpio_pci_tbl); i++) {
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pdev = pci_get_device(cs5535_gpio_pci_tbl[i].vendor,
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cs5535_gpio_pci_tbl[i].device, NULL);
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if (pdev) {
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err = cs5535_gpio_probe(pdev, &cs5535_gpio_pci_tbl[i]);
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if (err)
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pci_dev_put(pdev);
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/* we only support a single CS5535/6 southbridge */
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break;
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}
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}
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return err;
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}
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static void __exit cs5535_gpio_free_pci(void)
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{
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cs5535_gpio_remove(cs5535_gpio_chip.pdev);
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pci_dev_put(cs5535_gpio_chip.pdev);
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}
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static int __init cs5535_gpio_init(void)
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{
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return cs5535_gpio_scan_pci();
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}
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static void __exit cs5535_gpio_exit(void)
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{
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cs5535_gpio_free_pci();
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}
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module_init(cs5535_gpio_init);
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module_exit(cs5535_gpio_exit);
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MODULE_AUTHOR("Andres Salomon <dilinger@collabora.co.uk>");
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MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
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MODULE_LICENSE("GPL");
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58
include/linux/cs5535.h
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58
include/linux/cs5535.h
Normal file
@ -0,0 +1,58 @@
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/*
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* AMD CS5535/CS5536 definitions
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* Copyright (C) 2006 Advanced Micro Devices, Inc.
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* Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*/
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#ifndef _CS5535_H
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#define _CS5535_H
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/* MSRs */
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#define MSR_LBAR_SMB 0x5140000B
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#define MSR_LBAR_GPIO 0x5140000C
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#define MSR_LBAR_MFGPT 0x5140000D
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#define MSR_LBAR_ACPI 0x5140000E
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#define MSR_LBAR_PMS 0x5140000F
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/* resource sizes */
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#define LBAR_GPIO_SIZE 0xFF
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#define LBAR_MFGPT_SIZE 0x40
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#define LBAR_ACPI_SIZE 0x40
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#define LBAR_PMS_SIZE 0x80
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/* GPIOs */
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#define GPIO_OUTPUT_VAL 0x00
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#define GPIO_OUTPUT_ENABLE 0x04
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#define GPIO_OUTPUT_OPEN_DRAIN 0x08
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#define GPIO_OUTPUT_INVERT 0x0C
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#define GPIO_OUTPUT_AUX1 0x10
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#define GPIO_OUTPUT_AUX2 0x14
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#define GPIO_PULL_UP 0x18
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#define GPIO_PULL_DOWN 0x1C
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#define GPIO_INPUT_ENABLE 0x20
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#define GPIO_INPUT_INVERT 0x24
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#define GPIO_INPUT_FILTER 0x28
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#define GPIO_INPUT_EVENT_COUNT 0x2C
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#define GPIO_READ_BACK 0x30
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#define GPIO_INPUT_AUX1 0x34
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#define GPIO_EVENTS_ENABLE 0x38
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#define GPIO_LOCK_ENABLE 0x3C
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#define GPIO_POSITIVE_EDGE_EN 0x40
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#define GPIO_NEGATIVE_EDGE_EN 0x44
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#define GPIO_POSITIVE_EDGE_STS 0x48
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#define GPIO_NEGATIVE_EDGE_STS 0x4C
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#define GPIO_MAP_X 0xE0
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#define GPIO_MAP_Y 0xE4
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#define GPIO_MAP_Z 0xE8
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#define GPIO_MAP_W 0xEC
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void cs5535_gpio_set(unsigned offset, unsigned int reg);
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void cs5535_gpio_clear(unsigned offset, unsigned int reg);
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int cs5535_gpio_isset(unsigned offset, unsigned int reg);
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#endif
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