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Merge branch 'for-next' into omap-for-linus

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This commit is contained in:
Tony Lindgren 2009-12-11 16:19:16 -08:00
commit 5ccf197859
72 changed files with 8200 additions and 1522 deletions
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5
Documentation/kernel-parameters.txt
View File

@ -1787,6 +1787,11 @@ and is between 256 and 4096 characters. It is defined in the file
waiting for the ACK, so if this is set too high
interrupts *may* be lost!
omap_mux= [OMAP] Override bootloader pin multiplexing.
Format: <mux_mode0.mode_name=value>...
For example, to override I2C bus2:
omap_mux=i2c2_scl.i2c2_scl=0x100,i2c2_sda.i2c2_sda=0x100
opl3= [HW,OSS]
Format: <io>

9
arch/arm/configs/htcherald_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32-rc6
# Sat Nov 14 10:56:01 2009
# Linux kernel version: 2.6.32-rc8
# Sat Dec 5 12:16:24 2009
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@ -198,7 +198,9 @@ CONFIG_ARCH_OMAP1=y
# OMAP Feature Selections
#
# CONFIG_OMAP_RESET_CLOCKS is not set
# CONFIG_OMAP_MUX is not set
CONFIG_OMAP_MUX=y
# CONFIG_OMAP_MUX_DEBUG is not set
CONFIG_OMAP_MUX_WARNINGS=y
CONFIG_OMAP_MCBSP=y
# CONFIG_OMAP_MBOX_FWK is not set
CONFIG_OMAP_MPU_TIMER=y
@ -207,6 +209,7 @@ CONFIG_OMAP_LL_DEBUG_UART1=y
# CONFIG_OMAP_LL_DEBUG_UART2 is not set
# CONFIG_OMAP_LL_DEBUG_UART3 is not set
# CONFIG_OMAP_LL_DEBUG_NONE is not set
CONFIG_OMAP_SERIAL_WAKE=y
# CONFIG_OMAP_PM_NONE is not set
CONFIG_OMAP_PM_NOOP=y

2431
arch/arm/configs/omap3_touchbook_defconfig Normal file
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File diff suppressed because it is too large Load Diff

146
arch/arm/configs/omap_4430sdp_defconfig
View File

@ -1,26 +1,29 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.30-rc7
# Tue Jun 9 12:36:23 2009
# Linux kernel version: 2.6.32
# Sun Dec 6 23:37:45 2009
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_MMU=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_LOCKBREAK=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_ARCH_HAS_CPUFREQ=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
#
# General setup
@ -39,11 +42,12 @@ CONFIG_BSD_PROCESS_ACCT=y
#
# RCU Subsystem
#
CONFIG_CLASSIC_RCU=y
# CONFIG_TREE_RCU is not set
# CONFIG_PREEMPT_RCU is not set
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_PREEMPT_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_GROUP_SCHED=y
@ -52,8 +56,7 @@ CONFIG_FAIR_GROUP_SCHED=y
CONFIG_USER_SCHED=y
# CONFIG_CGROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED=y is not set
# CONFIG_SYSFS_DEPRECATED_V2=y is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
@ -70,7 +73,6 @@ CONFIG_UID16=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
@ -83,6 +85,10 @@ CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
#
# Kernel Performance Events And Counters
#
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
CONFIG_COMPAT_BRK=y
@ -90,13 +96,16 @@ CONFIG_COMPAT_BRK=y
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_USE_GENERIC_SMP_HELPERS=y
CONFIG_HAVE_CLK=y
#
# GCOV-based kernel profiling
#
# CONFIG_SLOW_WORK is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
@ -110,7 +119,7 @@ CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_STOP_MACHINE=y
CONFIG_BLOCK=y
# CONFIG_LBD is not set
CONFIG_LBDAF=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
@ -131,6 +140,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# System Type
#
CONFIG_MMU=y
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
@ -142,8 +152,10 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_STMP3XXX is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
@ -166,10 +178,13 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_S3C64XX is not set
# CONFIG_ARCH_S5PC1XX is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_U300 is not set
# CONFIG_ARCH_DAVINCI is not set
CONFIG_ARCH_OMAP=y
# CONFIG_ARCH_BCMRING is not set
#
# TI OMAP Implementations
@ -190,9 +205,12 @@ CONFIG_ARCH_OMAP4=y
CONFIG_OMAP_32K_TIMER=y
CONFIG_OMAP_32K_TIMER_HZ=128
CONFIG_OMAP_DM_TIMER=y
CONFIG_OMAP_LL_DEBUG_UART1=y
# CONFIG_OMAP_LL_DEBUG_UART1 is not set
# CONFIG_OMAP_LL_DEBUG_UART2 is not set
# CONFIG_OMAP_LL_DEBUG_UART3 is not set
CONFIG_OMAP_LL_DEBUG_UART3=y
# CONFIG_OMAP_LL_DEBUG_NONE is not set
# CONFIG_OMAP_PM_NONE is not set
CONFIG_OMAP_PM_NOOP=y
#
# OMAP Board Type
@ -207,7 +225,7 @@ CONFIG_CPU_32v6K=y
CONFIG_CPU_V7=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_IFAR=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
@ -222,9 +240,10 @@ CONFIG_CPU_CP15_MMU=y
# CONFIG_ARM_THUMB is not set
# CONFIG_ARM_THUMBEE is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
CONFIG_CPU_DCACHE_DISABLE=y
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_HAS_TLS_REG=y
CONFIG_ARM_L1_CACHE_SHIFT=5
# CONFIG_ARM_ERRATA_430973 is not set
# CONFIG_ARM_ERRATA_458693 is not set
# CONFIG_ARM_ERRATA_460075 is not set
@ -245,18 +264,20 @@ CONFIG_ARM_GIC=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_SMP=y
CONFIG_HAVE_ARM_SCU=y
CONFIG_HAVE_ARM_TWD=y
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_NR_CPUS=2
# CONFIG_HOTPLUG_CPU is not set
CONFIG_LOCAL_TIMERS=y
# CONFIG_PREEMPT is not set
# CONFIG_LOCAL_TIMERS is not set
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_HZ=128
# CONFIG_THUMB2_KERNEL is not set
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_OABI_COMPAT=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
# CONFIG_HIGHMEM is not set
@ -271,10 +292,13 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
# CONFIG_UNEVICTABLE_LRU is not set
CONFIG_HAVE_MLOCK=y
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
#
# Boot options
@ -298,9 +322,11 @@ CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600
#
# At least one emulation must be selected
#
# CONFIG_FPE_NWFPE is not set
# CONFIG_FPE_FASTFPE is not set
CONFIG_VFP=y
CONFIG_VFPv3=y
# CONFIG_NEON is not set
CONFIG_NEON=y
#
# Userspace binary formats
@ -325,6 +351,7 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_DEVTMPFS is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
@ -342,6 +369,7 @@ CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=16384
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_MG_DISK is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
@ -355,6 +383,7 @@ CONFIG_HAVE_IDE=y
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_PHONE is not set
#
# Input device support
@ -427,6 +456,11 @@ CONFIG_HW_RANDOM=y
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
# CONFIG_SPI is not set
#
# PPS support
#
# CONFIG_PPS is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
@ -447,11 +481,14 @@ CONFIG_GPIOLIB=y
#
# SPI GPIO expanders:
#
#
# AC97 GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
@ -472,21 +509,8 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
CONFIG_DAB=y
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
#
# Graphics support
@ -511,14 +535,17 @@ CONFIG_DUMMY_CONSOLE=y
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_REGULATOR is not set
# CONFIG_UIO is not set
#
# TI VLYNQ
#
# CONFIG_STAGING is not set
#
@ -535,9 +562,12 @@ CONFIG_JBD=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
CONFIG_FILE_LOCKING=y
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
@ -601,7 +631,6 @@ CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
# CONFIG_NILFS2_FS is not set
#
# Partition Types
@ -673,23 +702,24 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
# CONFIG_DETECT_SOFTLOCKUP is not set
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
@ -708,31 +738,22 @@ CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set
CONFIG_FRAME_POINTER=y
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_TRACING_SUPPORT=y
#
# Tracers
#
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_CONTEXT_SWITCH_TRACER is not set
# CONFIG_EVENT_TRACER is not set
# CONFIG_BOOT_TRACER is not set
# CONFIG_TRACE_BRANCH_PROFILING is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_KMEMTRACE is not set
# CONFIG_WORKQUEUE_TRACER is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_FTRACE is not set
# CONFIG_BRANCH_PROFILE_NONE is not set
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
@ -754,7 +775,6 @@ CONFIG_CRYPTO=y
#
# Crypto core or helper
#
# CONFIG_CRYPTO_FIPS is not set
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD2=y
@ -796,11 +816,13 @@ CONFIG_CRYPTO_PCBC=m
#
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set
#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_GHASH is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set

3
arch/arm/configs/omap_zoom2_defconfig
View File

@ -610,7 +610,8 @@ CONFIG_INPUT_EVDEV=y
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_TWL4030=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set

3
arch/arm/configs/omap_zoom3_defconfig
View File

@ -629,7 +629,8 @@ CONFIG_INPUT_EVDEV=y
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_TWL4030=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set

7
arch/arm/mach-omap1/Makefile
View File

@ -18,6 +18,9 @@ obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
mailbox_mach-objs := mailbox.o
i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
obj-y += $(i2c-omap-m) $(i2c-omap-y)
led-y := leds.o
# Specific board support
@ -49,3 +52,7 @@ led-$(CONFIG_MACH_OMAP_INNOVATOR) += leds-innovator.o
led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-h2p2-debug.o
led-$(CONFIG_MACH_OMAP_OSK) += leds-osk.o
obj-$(CONFIG_LEDS) += $(led-y)
ifneq ($(CONFIG_FB_OMAP),)
obj-y += lcd_dma.o
endif

60
arch/arm/mach-omap1/board-fsample.c
View File

@ -19,6 +19,7 @@
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -30,7 +31,6 @@
#include <mach/gpio.h>
#include <plat/mux.h>
#include <plat/fpga.h>
#include <plat/nand.h>
#include <plat/keypad.h>
#include <plat/common.h>
#include <plat/board.h>
@ -100,6 +100,12 @@ static int fsample_keymap[] = {
0
};
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
@ -167,8 +173,40 @@ static struct platform_device nor_device = {
.resource = &nor_resource,
};
static struct omap_nand_platform_data nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}
#define FSAMPLE_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct mtd_info *mtd)
{
return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
}
static const char *part_probes[] = { "cmdlinepart", NULL };
static struct platform_nand_data nand_data = {
.chip = {
.nr_chips = 1,
.chip_offset = 0,
.options = NAND_SAMSUNG_LP_OPTIONS,
.part_probe_types = part_probes,
},
.ctrl = {
.cmd_ctrl = nand_cmd_ctl,
.dev_ready = nand_dev_ready,
},
};
static struct resource nand_resource = {
@ -178,7 +216,7 @@ static struct resource nand_resource = {
};
static struct platform_device nand_device = {
.name = "omapnand",
.name = "gen_nand",
.id = 0,
.dev = {
.platform_data = &nand_data,
@ -190,6 +228,9 @@ static struct platform_device nand_device = {
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
@ -233,13 +274,6 @@ static struct platform_device *devices[] __initdata = {
&lcd_device,
};
#define P2_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct omap_nand_platform_data *data)
{
return gpio_get_value(P2_NAND_RB_GPIO_PIN);
}
static struct omap_lcd_config fsample_lcd_config __initdata = {
.ctrl_name = "internal",
};
@ -250,9 +284,9 @@ static struct omap_board_config_kernel fsample_config[] = {
static void __init omap_fsample_init(void)
{
if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
BUG();
nand_data.dev_ready = nand_dev_ready;
gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
omap_cfg_reg(M8_1610_FLASH_CS2B_WE);

59
arch/arm/mach-omap1/board-h2.c
View File

@ -28,6 +28,7 @@
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/i2c/tps65010.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/gpio.h>
@ -40,7 +41,6 @@
#include <plat/mux.h>
#include <plat/dma.h>
#include <plat/tc.h>
#include <plat/nand.h>
#include <plat/irda.h>
#include <plat/usb.h>
#include <plat/keypad.h>
@ -179,11 +179,43 @@ static struct mtd_partition h2_nand_partitions[] = {
},
};
/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */
static struct omap_nand_platform_data h2_nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
.parts = h2_nand_partitions,
.nr_parts = ARRAY_SIZE(h2_nand_partitions),
static void h2_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}
#define H2_NAND_RB_GPIO_PIN 62
static int h2_nand_dev_ready(struct mtd_info *mtd)
{
return gpio_get_value(H2_NAND_RB_GPIO_PIN);
}
static const char *h2_part_probes[] = { "cmdlinepart", NULL };
struct platform_nand_data h2_nand_platdata = {
.chip = {
.nr_chips = 1,
.chip_offset = 0,
.nr_partitions = ARRAY_SIZE(h2_nand_partitions),
.partitions = h2_nand_partitions,
.options = NAND_SAMSUNG_LP_OPTIONS,
.part_probe_types = h2_part_probes,
},
.ctrl = {
.cmd_ctrl = h2_nand_cmd_ctl,
.dev_ready = h2_nand_dev_ready,
},
};
static struct resource h2_nand_resource = {
@ -191,15 +223,21 @@ static struct resource h2_nand_resource = {
};
static struct platform_device h2_nand_device = {
.name = "omapnand",
.name = "gen_nand",
.id = 0,
.dev = {
.platform_data = &h2_nand_data,
.platform_data = &h2_nand_platdata,
},
.num_resources = 1,
.resource = &h2_nand_resource,
};
static struct smc91x_platdata h2_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource h2_smc91x_resources[] = {
[0] = {
.start = OMAP1610_ETHR_START, /* Physical */
@ -216,6 +254,9 @@ static struct resource h2_smc91x_resources[] = {
static struct platform_device h2_smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &h2_smc91x_info,
},
.num_resources = ARRAY_SIZE(h2_smc91x_resources),
.resource = h2_smc91x_resources,
};
@ -368,8 +409,6 @@ static struct omap_board_config_kernel h2_config[] __initdata = {
{ OMAP_TAG_LCD, &h2_lcd_config },
};
#define H2_NAND_RB_GPIO_PIN 62
static void __init h2_init(void)
{
/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped

66
arch/arm/mach-omap1/board-h3.c
View File

@ -28,6 +28,7 @@
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/i2c/tps65010.h>
#include <linux/smc91x.h>
#include <asm/setup.h>
#include <asm/page.h>
@ -42,7 +43,6 @@
#include <mach/irqs.h>
#include <plat/mux.h>
#include <plat/tc.h>
#include <plat/nand.h>
#include <plat/usb.h>
#include <plat/keypad.h>
#include <plat/dma.h>
@ -181,11 +181,43 @@ static struct mtd_partition nand_partitions[] = {
},
};
/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */
static struct omap_nand_platform_data nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
.parts = nand_partitions,
.nr_parts = ARRAY_SIZE(nand_partitions),
static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}
#define H3_NAND_RB_GPIO_PIN 10
static int nand_dev_ready(struct mtd_info *mtd)
{
return gpio_get_value(H3_NAND_RB_GPIO_PIN);
}
static const char *part_probes[] = { "cmdlinepart", NULL };
struct platform_nand_data nand_platdata = {
.chip = {
.nr_chips = 1,
.chip_offset = 0,
.nr_partitions = ARRAY_SIZE(nand_partitions),
.partitions = nand_partitions,
.options = NAND_SAMSUNG_LP_OPTIONS,
.part_probe_types = part_probes,
},
.ctrl = {
.cmd_ctrl = nand_cmd_ctl,
.dev_ready = nand_dev_ready,
},
};
static struct resource nand_resource = {
@ -193,15 +225,21 @@ static struct resource nand_resource = {
};
static struct platform_device nand_device = {
.name = "omapnand",
.name = "gen_nand",
.id = 0,
.dev = {
.platform_data = &nand_data,
.platform_data = &nand_platdata,
},
.num_resources = 1,
.resource = &nand_resource,
};
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = OMAP1710_ETHR_START, /* Physical */
@ -218,6 +256,9 @@ static struct resource smc91x_resources[] = {
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
@ -332,13 +373,6 @@ static struct i2c_board_info __initdata h3_i2c_board_info[] = {
},
};
#define H3_NAND_RB_GPIO_PIN 10
static int nand_dev_ready(struct omap_nand_platform_data *data)
{
return gpio_get_value(H3_NAND_RB_GPIO_PIN);
}
static void __init h3_init(void)
{
/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
@ -356,7 +390,7 @@ static void __init h3_init(void)
nand_resource.end += SZ_4K - 1;
if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0)
BUG();
nand_data.dev_ready = nand_dev_ready;
gpio_direction_input(H3_NAND_RB_GPIO_PIN);
/* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
/* GPIO10 pullup/down register, Enable pullup on GPIO10 */

64
arch/arm/mach-omap1/board-htcherald.c
View File

@ -39,6 +39,7 @@
#include <plat/common.h>
#include <plat/board.h>
#include <plat/keypad.h>
#include <plat/usb.h>
#include <mach/irqs.h>
@ -140,6 +141,15 @@ static struct platform_device kp_device = {
.resource = kp_resources,
};
/* USB Device */
static struct omap_usb_config htcherald_usb_config __initdata = {
.otg = 0,
.register_host = 0,
.register_dev = 1,
.hmc_mode = 4,
.pins[0] = 2,
};
/* LCD Device resources */
static struct platform_device lcd_device = {
.name = "lcd_htcherald",
@ -214,6 +224,57 @@ static void __init htcherald_disable_watchdog(void)
}
}
#define HTCHERALD_GPIO_USB_EN1 33
#define HTCHERALD_GPIO_USB_EN2 73
#define HTCHERALD_GPIO_USB_DM 35
#define HTCHERALD_GPIO_USB_DP 36
static void __init htcherald_usb_enable(void)
{
unsigned int tries = 20;
unsigned int value = 0;
/* Request the GPIOs we need to control here */
if (gpio_request(HTCHERALD_GPIO_USB_EN1, "herald_usb") < 0)
goto err1;
if (gpio_request(HTCHERALD_GPIO_USB_EN2, "herald_usb") < 0)
goto err2;
if (gpio_request(HTCHERALD_GPIO_USB_DM, "herald_usb") < 0)
goto err3;
if (gpio_request(HTCHERALD_GPIO_USB_DP, "herald_usb") < 0)
goto err4;
/* force USB_EN GPIO to 0 */
do {
/* output low */
gpio_direction_output(HTCHERALD_GPIO_USB_EN1, 0);
} while ((value = gpio_get_value(HTCHERALD_GPIO_USB_EN1)) == 1 &&
--tries);
if (value == 1)
printk(KERN_WARNING "Unable to reset USB, trying to continue\n");
gpio_direction_output(HTCHERALD_GPIO_USB_EN2, 0); /* output low */
gpio_direction_input(HTCHERALD_GPIO_USB_DM); /* input */
gpio_direction_input(HTCHERALD_GPIO_USB_DP); /* input */
goto done;
err4:
gpio_free(HTCHERALD_GPIO_USB_DM);
err3:
gpio_free(HTCHERALD_GPIO_USB_EN2);
err2:
gpio_free(HTCHERALD_GPIO_USB_EN1);
err1:
printk(KERN_ERR "Unabled to request GPIO for USB\n");
done:
printk(KERN_INFO "USB setup complete.\n");
}
static void __init htcherald_init(void)
{
printk(KERN_INFO "HTC Herald init.\n");
@ -225,6 +286,9 @@ static void __init htcherald_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
htcherald_disable_watchdog();
htcherald_usb_enable();
omap_usb_init(&htcherald_usb_config);
}
static void __init htcherald_init_irq(void)

12
arch/arm/mach-omap1/board-innovator.c
View File

@ -23,6 +23,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -142,6 +143,11 @@ static struct platform_device innovator_kp_device = {
.resource = innovator_kp_resources,
};
static struct smc91x_platdata innovator_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
#ifdef CONFIG_ARCH_OMAP15XX
@ -175,6 +181,9 @@ static struct resource innovator1510_smc91x_resources[] = {
static struct platform_device innovator1510_smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &innovator_smc91x_info,
},
.num_resources = ARRAY_SIZE(innovator1510_smc91x_resources),
.resource = innovator1510_smc91x_resources,
};
@ -241,6 +250,9 @@ static struct resource innovator1610_smc91x_resources[] = {
static struct platform_device innovator1610_smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &innovator_smc91x_info,
},
.num_resources = ARRAY_SIZE(innovator1610_smc91x_resources),
.resource = innovator1610_smc91x_resources,
};

10
arch/arm/mach-omap1/board-osk.c
View File

@ -33,6 +33,7 @@
#include <linux/irq.h>
#include <linux/i2c.h>
#include <linux/leds.h>
#include <linux/smc91x.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
@ -115,6 +116,12 @@ static struct platform_device osk5912_flash_device = {
.resource = &osk_flash_resource,
};
static struct smc91x_platdata osk5912_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource osk5912_smc91x_resources[] = {
[0] = {
.start = OMAP_OSK_ETHR_START, /* Physical */
@ -131,6 +138,9 @@ static struct resource osk5912_smc91x_resources[] = {
static struct platform_device osk5912_smc91x_device = {
.name = "smc91x",
.id = -1,
.dev = {
.platform_data = &osk5912_smc91x_info,
},
.num_resources = ARRAY_SIZE(osk5912_smc91x_resources),
.resource = osk5912_smc91x_resources,
};

58
arch/arm/mach-omap1/board-perseus2.c
View File

@ -19,6 +19,7 @@
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -30,7 +31,6 @@
#include <mach/gpio.h>
#include <plat/mux.h>
#include <plat/fpga.h>
#include <plat/nand.h>
#include <plat/keypad.h>
#include <plat/common.h>
#include <plat/board.h>
@ -67,6 +67,12 @@ static int p2_keymap[] = {
0
};
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
@ -134,8 +140,40 @@ static struct platform_device nor_device = {
.resource = &nor_resource,
};
static struct omap_nand_platform_data nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}
#define P2_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct mtd_info *mtd)
{
return gpio_get_value(P2_NAND_RB_GPIO_PIN);
}
static const char *part_probes[] = { "cmdlinepart", NULL };
static struct platform_nand_data nand_data = {
.chip = {
.nr_chips = 1,
.chip_offset = 0,
.options = NAND_SAMSUNG_LP_OPTIONS,
.part_probe_types = part_probes,
},
.ctrl = {
.cmd_ctrl = nand_cmd_ctl,
.dev_ready = nand_dev_ready,
},
};
static struct resource nand_resource = {
@ -145,7 +183,7 @@ static struct resource nand_resource = {
};
static struct platform_device nand_device = {
.name = "omapnand",
.name = "gen_nand",
.id = 0,
.dev = {
.platform_data = &nand_data,
@ -157,6 +195,9 @@ static struct platform_device nand_device = {
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
@ -201,13 +242,6 @@ static struct platform_device *devices[] __initdata = {
&lcd_device,
};
#define P2_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct omap_nand_platform_data *data)
{
return gpio_get_value(P2_NAND_RB_GPIO_PIN);
}
static struct omap_lcd_config perseus2_lcd_config __initdata = {
.ctrl_name = "internal",
};
@ -220,7 +254,7 @@ static void __init omap_perseus2_init(void)
{
if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
BUG();
nand_data.dev_ready = nand_dev_ready;
gpio_direction_input(P2_NAND_RB_GPIO_PIN);
omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
omap_cfg_reg(M8_1610_FLASH_CS2B_WE);

10
arch/arm/mach-omap1/board-voiceblue.c
View File

@ -22,6 +22,7 @@
#include <linux/reboot.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -106,6 +107,12 @@ static struct platform_device voiceblue_flash_device = {
.resource = &voiceblue_flash_resource,
};
static struct smc91x_platdata voiceblue_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource voiceblue_smc91x_resources[] = {
[0] = {
.start = OMAP_CS2_PHYS + 0x300,
@ -122,6 +129,9 @@ static struct resource voiceblue_smc91x_resources[] = {
static struct platform_device voiceblue_smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &voiceblue_smc91x_info,
},
.num_resources = ARRAY_SIZE(voiceblue_smc91x_resources),
.resource = voiceblue_smc91x_resources,
};

4
arch/arm/mach-omap1/clock_data.c
View File

@ -655,9 +655,9 @@ static struct omap_clk omap_clks[] = {
CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
/* Virtual clocks */
CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310),
CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX),
CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310),
CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),

39
arch/arm/mach-omap1/i2c.c Normal file
View File

@ -0,0 +1,39 @@
/*
* Helper module for board specific I2C bus registration
*
* Copyright (C) 2009 Nokia Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <plat/i2c.h>
#include <plat/mux.h>
#include <plat/cpu.h>
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
if (cpu_is_omap7xx()) {
omap_cfg_reg(I2C_7XX_SDA);
omap_cfg_reg(I2C_7XX_SCL);
} else {
omap_cfg_reg(I2C_SDA);
omap_cfg_reg(I2C_SCL);
}
return omap_plat_register_i2c_bus(bus_id, clkrate, info, len);
}

78
arch/arm/mach-omap1/include/mach/lcd_dma.h Normal file
View File

@ -0,0 +1,78 @@
/*
* arch/arm/mach-omap1/include/mach/lcd_dma.h
*
* Extracted from arch/arm/plat-omap/include/plat/dma.h
* Copyright (C) 2003 Nokia Corporation
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __MACH_OMAP1_LCD_DMA_H__
#define __MACH_OMAP1_LCD_DMA_H__
/* Hardware registers for LCD DMA */
#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
#define OMAP1610_DMA_LCD_BASE (0xfffee300)
#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
/* LCD DMA block numbers */
enum {
OMAP_LCD_DMA_B1_TOP,
OMAP_LCD_DMA_B1_BOTTOM,
OMAP_LCD_DMA_B2_TOP,
OMAP_LCD_DMA_B2_BOTTOM
};
/* LCD DMA functions */
extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
void *data);
extern void omap_free_lcd_dma(void);
extern void omap_setup_lcd_dma(void);
extern void omap_enable_lcd_dma(void);
extern void omap_stop_lcd_dma(void);
extern void omap_set_lcd_dma_ext_controller(int external);
extern void omap_set_lcd_dma_single_transfer(int single);
extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
int data_type);
extern void omap_set_lcd_dma_b1_rotation(int rotate);
extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
extern void omap_set_lcd_dma_b1_mirror(int mirror);
extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
extern int omap_lcd_dma_running(void);
#endif /* __MACH_OMAP1_LCD_DMA_H__ */

57
arch/arm/mach-omap1/include/mach/lcdc.h Normal file
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@ -0,0 +1,57 @@
/*
* arch/arm/mach-omap1/include/mach/lcdc.h
*
* Extracted from drivers/video/omap/lcdc.c
* Copyright (C) 2004 Nokia Corporation
* Author: Imre Deak <imre.deak@nokia.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __MACH_LCDC_H__
#define __MACH_LCDC_H__
#define OMAP_LCDC_BASE 0xfffec000
#define OMAP_LCDC_SIZE 256
#define OMAP_LCDC_IRQ INT_LCD_CTRL
#define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00)
#define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04)
#define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08)
#define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c)
#define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10)
#define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14)
#define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18)
#define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c)
#define OMAP_LCDC_STAT_DONE (1 << 0)
#define OMAP_LCDC_STAT_VSYNC (1 << 1)
#define OMAP_LCDC_STAT_SYNC_LOST (1 << 2)
#define OMAP_LCDC_STAT_ABC (1 << 3)
#define OMAP_LCDC_STAT_LINE_INT (1 << 4)
#define OMAP_LCDC_STAT_FUF (1 << 5)
#define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6)
#define OMAP_LCDC_CTRL_LCD_EN (1 << 0)
#define OMAP_LCDC_CTRL_LCD_TFT (1 << 7)
#define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
#define OMAP_LCDC_IRQ_VSYNC (1 << 2)
#define OMAP_LCDC_IRQ_DONE (1 << 3)
#define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4)
#define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5)
#define OMAP_LCDC_IRQ_LINE (1 << 6)
#define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2)
#endif /* __MACH_LCDC_H__ */

448
arch/arm/mach-omap1/lcd_dma.c Normal file
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@ -0,0 +1,448 @@
/*
* linux/arch/arm/mach-omap1/lcd_dma.c
*
* Extracted from arch/arm/plat-omap/dma.c
* Copyright (C) 2003 - 2008 Nokia Corporation
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
* Graphics DMA and LCD DMA graphics tranformations
* by Imre Deak <imre.deak@nokia.com>
* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
* Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* Support functions for the OMAP internal DMA channels.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/lcdc.h>
#include <plat/dma.h>
int omap_lcd_dma_running(void)
{
/*
* On OMAP1510, internal LCD controller will start the transfer
* when it gets enabled, so assume DMA running if LCD enabled.
*/
if (cpu_is_omap1510())
if (omap_readw(OMAP_LCDC_CONTROL) & OMAP_LCDC_CTRL_LCD_EN)
return 1;
/* Check if LCD DMA is running */
if (cpu_is_omap16xx())
if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
return 1;
return 0;
}
static struct lcd_dma_info {
spinlock_t lock;
int reserved;
void (*callback)(u16 status, void *data);
void *cb_data;
int active;
unsigned long addr, size;
int rotate, data_type, xres, yres;
int vxres;
int mirror;
int xscale, yscale;
int ext_ctrl;
int src_port;
int single_transfer;
} lcd_dma;
void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
int data_type)
{
lcd_dma.addr = addr;
lcd_dma.data_type = data_type;
lcd_dma.xres = fb_xres;
lcd_dma.yres = fb_yres;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1);
void omap_set_lcd_dma_src_port(int port)
{
lcd_dma.src_port = port;
}
void omap_set_lcd_dma_ext_controller(int external)
{
lcd_dma.ext_ctrl = external;
}
EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
void omap_set_lcd_dma_single_transfer(int single)
{
lcd_dma.single_transfer = single;
}
EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
void omap_set_lcd_dma_b1_rotation(int rotate)
{
if (cpu_is_omap1510()) {
printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
BUG();
return;
}
lcd_dma.rotate = rotate;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
void omap_set_lcd_dma_b1_mirror(int mirror)
{
if (cpu_is_omap1510()) {
printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
BUG();
}
lcd_dma.mirror = mirror;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
{
if (cpu_is_omap1510()) {
printk(KERN_ERR "DMA virtual resulotion is not supported "
"in 1510 mode\n");
BUG();
}
lcd_dma.vxres = vxres;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
{
if (cpu_is_omap1510()) {
printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
BUG();
}
lcd_dma.xscale = xscale;
lcd_dma.yscale = yscale;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
static void set_b1_regs(void)
{
unsigned long top, bottom;
int es;
u16 w;
unsigned long en, fn;
long ei, fi;
unsigned long vxres;
unsigned int xscale, yscale;
switch (lcd_dma.data_type) {
case OMAP_DMA_DATA_TYPE_S8:
es = 1;
break;
case OMAP_DMA_DATA_TYPE_S16:
es = 2;
break;
case OMAP_DMA_DATA_TYPE_S32:
es = 4;
break;
default:
BUG();
return;
}
vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
BUG_ON(vxres < lcd_dma.xres);
#define PIXADDR(x, y) (lcd_dma.addr + \
((y) * vxres * yscale + (x) * xscale) * es)
#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
switch (lcd_dma.rotate) {
case 0:
if (!lcd_dma.mirror) {
top = PIXADDR(0, 0);
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
/* 1510 DMA requires the bottom address to be 2 more
* than the actual last memory access location. */
if (cpu_is_omap1510() &&
lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
bottom += 2;
ei = PIXSTEP(0, 0, 1, 0);
fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
} else {
top = PIXADDR(lcd_dma.xres - 1, 0);
bottom = PIXADDR(0, lcd_dma.yres - 1);
ei = PIXSTEP(1, 0, 0, 0);
fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
}
en = lcd_dma.xres;
fn = lcd_dma.yres;
break;
case 90:
if (!lcd_dma.mirror) {
top = PIXADDR(0, lcd_dma.yres - 1);
bottom = PIXADDR(lcd_dma.xres - 1, 0);
ei = PIXSTEP(0, 1, 0, 0);
fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
} else {
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
bottom = PIXADDR(0, 0);
ei = PIXSTEP(0, 1, 0, 0);
fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
}
en = lcd_dma.yres;
fn = lcd_dma.xres;
break;
case 180:
if (!lcd_dma.mirror) {
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
bottom = PIXADDR(0, 0);
ei = PIXSTEP(1, 0, 0, 0);
fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
} else {
top = PIXADDR(0, lcd_dma.yres - 1);
bottom = PIXADDR(lcd_dma.xres - 1, 0);
ei = PIXSTEP(0, 0, 1, 0);
fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
}
en = lcd_dma.xres;
fn = lcd_dma.yres;
break;
case 270:
if (!lcd_dma.mirror) {
top = PIXADDR(lcd_dma.xres - 1, 0);
bottom = PIXADDR(0, lcd_dma.yres - 1);
ei = PIXSTEP(0, 0, 0, 1);
fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
} else {
top = PIXADDR(0, 0);
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
ei = PIXSTEP(0, 0, 0, 1);
fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
}
en = lcd_dma.yres;
fn = lcd_dma.xres;
break;
default:
BUG();
return; /* Suppress warning about uninitialized vars */
}
if (cpu_is_omap1510()) {
omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
return;
}
/* 1610 regs */
omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
w = omap_readw(OMAP1610_DMA_LCD_CSDP);
w &= ~0x03;
w |= lcd_dma.data_type;
omap_writew(w, OMAP1610_DMA_LCD_CSDP);
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
/* Always set the source port as SDRAM for now*/
w &= ~(0x03 << 6);
if (lcd_dma.callback != NULL)
w |= 1 << 1; /* Block interrupt enable */
else
w &= ~(1 << 1);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
if (!(lcd_dma.rotate || lcd_dma.mirror ||
lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
return;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
/* Set the double-indexed addressing mode */
w |= (0x03 << 12);
omap_writew(w, OMAP1610_DMA_LCD_CCR);
omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
}
static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
{
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
if (unlikely(!(w & (1 << 3)))) {
printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
return IRQ_NONE;
}
/* Ack the IRQ */
w |= (1 << 3);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
lcd_dma.active = 0;
if (lcd_dma.callback != NULL)
lcd_dma.callback(w, lcd_dma.cb_data);
return IRQ_HANDLED;
}
int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
void *data)
{
spin_lock_irq(&lcd_dma.lock);
if (lcd_dma.reserved) {
spin_unlock_irq(&lcd_dma.lock);
printk(KERN_ERR "LCD DMA channel already reserved\n");
BUG();
return -EBUSY;
}
lcd_dma.reserved = 1;
spin_unlock_irq(&lcd_dma.lock);
lcd_dma.callback = callback;
lcd_dma.cb_data = data;
lcd_dma.active = 0;
lcd_dma.single_transfer = 0;
lcd_dma.rotate = 0;
lcd_dma.vxres = 0;
lcd_dma.mirror = 0;
lcd_dma.xscale = 0;
lcd_dma.yscale = 0;
lcd_dma.ext_ctrl = 0;
lcd_dma.src_port = 0;
return 0;
}
EXPORT_SYMBOL(omap_request_lcd_dma);
void omap_free_lcd_dma(void)
{
spin_lock(&lcd_dma.lock);
if (!lcd_dma.reserved) {
spin_unlock(&lcd_dma.lock);
printk(KERN_ERR "LCD DMA is not reserved\n");
BUG();
return;
}
if (!cpu_is_omap1510())
omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
OMAP1610_DMA_LCD_CCR);
lcd_dma.reserved = 0;
spin_unlock(&lcd_dma.lock);
}
EXPORT_SYMBOL(omap_free_lcd_dma);
void omap_enable_lcd_dma(void)
{
u16 w;
/*
* Set the Enable bit only if an external controller is
* connected. Otherwise the OMAP internal controller will
* start the transfer when it gets enabled.
*/
if (cpu_is_omap1510() || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w |= 1 << 8;
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
lcd_dma.active = 1;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w |= 1 << 7;
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
EXPORT_SYMBOL(omap_enable_lcd_dma);
void omap_setup_lcd_dma(void)
{
BUG_ON(lcd_dma.active);
if (!cpu_is_omap1510()) {
/* Set some reasonable defaults */
omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
}
set_b1_regs();
if (!cpu_is_omap1510()) {
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
/*
* If DMA was already active set the end_prog bit to have
* the programmed register set loaded into the active
* register set.
*/
w |= 1 << 11; /* End_prog */
if (!lcd_dma.single_transfer)
w |= (3 << 8); /* Auto_init, repeat */
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
}
EXPORT_SYMBOL(omap_setup_lcd_dma);
void omap_stop_lcd_dma(void)
{
u16 w;
lcd_dma.active = 0;
if (cpu_is_omap1510() || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w &= ~(1 << 7);
omap_writew(w, OMAP1610_DMA_LCD_CCR);
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
EXPORT_SYMBOL(omap_stop_lcd_dma);
static int __init omap_init_lcd_dma(void)
{
int r;
if (cpu_is_omap16xx()) {
u16 w;
/* this would prevent OMAP sleep */
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
spin_lock_init(&lcd_dma.lock);
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
"LCD DMA", NULL);
if (r != 0)
printk(KERN_ERR "unable to request IRQ for LCD DMA "
"(error %d)\n", r);
return r;
}
arch_initcall(omap_init_lcd_dma);

8
arch/arm/mach-omap1/mux.c
View File

@ -50,12 +50,18 @@ MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0)
MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0)
MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0)
MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 0, 28, 0, 0)
MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 6, 28, 1, 0)
MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3, 3, 1, 2, 0, 0)
MUX_CFG_7XX("W19_7XX_USB_DCRST", 3, 7, 1, 6, 0, 0)
/* MMC Pins */
MUX_CFG_7XX("MMC_7XX_CMD", 2, 9, 0, 8, 1, 0)
MUX_CFG_7XX("MMC_7XX_CLK", 2, 13, 0, 12, 1, 0)
MUX_CFG_7XX("MMC_7XX_DAT0", 2, 17, 0, 16, 1, 0)
/* I2C interface */
MUX_CFG_7XX("I2C_7XX_SCL", 5, 1, 0, 0, 1, 0)
MUX_CFG_7XX("I2C_7XX_SDA", 5, 5, 0, 0, 1, 0)
};
#define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins)
#else

30
arch/arm/mach-omap2/Kconfig
View File

@ -24,6 +24,18 @@ config ARCH_OMAP3430
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select ARCH_OMAP_OTG
config OMAP_PACKAGE_CBC
bool
config OMAP_PACKAGE_CBB
bool
config OMAP_PACKAGE_CUS
bool
config OMAP_PACKAGE_CBP
bool
comment "OMAP Board Type"
depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
@ -52,14 +64,17 @@ config MACH_OMAP_2430SDP
config MACH_OMAP3_BEAGLE
bool "OMAP3 BEAGLE board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP_LDP
bool "OMAP3 LDP board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OVERO
bool "Gumstix Overo board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP3EVM
bool "OMAP 3530 EVM board"
@ -68,14 +83,22 @@ config MACH_OMAP3EVM
config MACH_OMAP3517EVM
bool "OMAP3517/ AM3517 EVM board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP3_PANDORA
bool "OMAP3 Pandora"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP3_TOUCHBOOK
bool "OMAP3 Touch Book"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select BACKLIGHT_CLASS_DEVICE
config MACH_OMAP_3430SDP
bool "OMAP 3430 SDP board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_NOKIA_N800
bool
@ -96,26 +119,33 @@ config MACH_NOKIA_N8X0
config MACH_NOKIA_RX51
bool "Nokia RX-51 board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP_ZOOM2
bool "OMAP3 Zoom2 board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP_ZOOM3
bool "OMAP3630 Zoom3 board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBP
config MACH_CM_T35
bool "CompuLab CM-T35 module"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CUS
select OMAP_MUX
config MACH_IGEP0020
bool "IGEP0020"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP_3630SDP
bool "OMAP3630 SDP board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBP
config MACH_OMAP_4430SDP
bool "OMAP 4430 SDP board"

9
arch/arm/mach-omap2/Makefile
View File

@ -26,6 +26,9 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
# Pin multiplexing
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
# SMS/SDRC
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
@ -61,6 +64,9 @@ iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o
obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y)
i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
obj-y += $(i2c-omap-m) $(i2c-omap-y)
# Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
@ -99,7 +105,8 @@ obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \
mmc-twl4030.o
obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \
mmc-twl4030.o
obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \
mmc-twl4030.o
obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o

15
arch/arm/mach-omap2/board-3430sdp.c
View File

@ -31,7 +31,6 @@
#include <asm/mach/map.h>
#include <plat/mcspi.h>
#include <plat/mux.h>
#include <plat/board.h>
#include <plat/usb.h>
#include <plat/common.h>
@ -42,6 +41,7 @@
#include <plat/control.h>
#include <plat/gpmc-smc91x.h>
#include "mux.h"
#include "sdram-qimonda-hyb18m512160af-6.h"
#include "mmc-twl4030.h"
@ -625,7 +625,9 @@ static inline void board_smc91x_init(void)
static void enable_board_wakeup_source(void)
{
omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
/* T2 interrupt line (keypad) */
omap_mux_init_signal("sys_nirq",
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
}
static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
@ -640,8 +642,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap_3430sdp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3430_i2c_init();
platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
if (omap_rev() > OMAP3430_REV_ES1_0)

14
arch/arm/mach-omap2/board-3630sdp.c
View File

@ -23,6 +23,7 @@
#include <mach/board-zoom.h>
#include "mux.h"
#include "sdram-hynix-h8mbx00u0mer-0em.h"
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
@ -48,7 +49,9 @@ static inline void board_smc91x_init(void)
static void enable_board_wakeup_source(void)
{
omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
/* T2 interrupt line (keypad) */
omap_mux_init_signal("sys_nirq",
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
}
static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
@ -82,8 +85,17 @@ static void __init omap_sdp_init_irq(void)
omap_gpio_init();
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap_sdp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
zoom_peripherals_init();
board_smc91x_init();
enable_board_wakeup_source();

11
arch/arm/mach-omap2/board-am3517evm.c
View File

@ -30,6 +30,8 @@
#include <plat/common.h>
#include <plat/usb.h>
#include "mux.h"
/*
* Board initialization
*/
@ -60,8 +62,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init am3517_evm_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
platform_add_devices(am3517_evm_devices,
ARRAY_SIZE(am3517_evm_devices));

10
arch/arm/mach-omap2/board-apollon.c
View File

@ -26,6 +26,7 @@
#include <linux/leds.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -120,6 +121,12 @@ static void __init apollon_flash_init(void)
apollon_flash_resource[0].end = base + SZ_128K - 1;
}
static struct smc91x_platdata appolon_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource apollon_smc91x_resources[] = {
[0] = {
.flags = IORESOURCE_MEM,
@ -134,6 +141,9 @@ static struct resource apollon_smc91x_resources[] = {
static struct platform_device apollon_smc91x_device = {
.name = "smc91x",
.id = -1,
.dev = {
.platform_data = &appolon_smc91x_info,
},
.num_resources = ARRAY_SIZE(apollon_smc91x_resources),
.resource = apollon_smc91x_resources,
};

98
arch/arm/mach-omap2/board-cm-t35.c
View File

@ -38,13 +38,13 @@
#include <plat/board.h>
#include <plat/common.h>
#include <plat/mux.h>
#include <plat/nand.h>
#include <plat/gpmc.h>
#include <plat/usb.h>
#include <mach/hardware.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
#include "mmc-twl4030.h"
@ -482,8 +482,102 @@ static void __init cm_t35_map_io(void)
omap2_map_common_io();
}
static struct omap_board_mux board_mux[] __initdata = {
/* nCS and IRQ for CM-T35 ethernet */
OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
/* nCS and IRQ for SB-T35 ethernet */
OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0),
OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
/* PENDOWN GPIO */
OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
/* mUSB */
OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
/* MMC 2 */
OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
/* McSPI 1 */
OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
/* McSPI 4 */
OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP),
/* McBSP 2 */
OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
/* serial ports */
OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
/* DSS */
OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
/* TPS IRQ */
OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
OMAP_PIN_INPUT_PULLUP),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
static void __init cm_t35_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
omap_serial_init();
cm_t35_init_i2c();
cm_t35_init_nand();
@ -492,8 +586,6 @@ static void __init cm_t35_init(void)
cm_t35_init_led();
usb_musb_init();
omap_cfg_reg(AF26_34XX_SYS_NIRQ);
}
MACHINE_START(CM_T35, "Compulab CM-T35")

11
arch/arm/mach-omap2/board-igep0020.c
View File

@ -27,9 +27,9 @@
#include <plat/board.h>
#include <plat/common.h>
#include <plat/gpmc.h>
#include <plat/mux.h>
#include <plat/usb.h>
#include "mux.h"
#include "mmc-twl4030.h"
#define IGEP2_SMSC911X_CS 5
@ -203,8 +203,17 @@ static int __init igep2_i2c_init(void)
return 0;
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init igep2_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
igep2_i2c_init();
omap_serial_init();
usb_musb_init();

10
arch/arm/mach-omap2/board-ldp.c
View File

@ -43,6 +43,7 @@
#include <plat/control.h>
#include <plat/usb.h>
#include "mux.h"
#include "mmc-twl4030.h"
#define LDP_SMSC911X_CS 1
@ -374,8 +375,17 @@ static struct platform_device *ldp_devices[] __initdata = {
&ldp_gpio_keys_device,
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap_ldp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_i2c_init();
platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
ts_gpio = 54;

21
arch/arm/mach-omap2/board-omap3beagle.c
View File

@ -41,10 +41,10 @@
#include <plat/common.h>
#include <plat/gpmc.h>
#include <plat/nand.h>
#include <plat/mux.h>
#include <plat/usb.h>
#include <plat/timer-gp.h>
#include "mux.h"
#include "mmc-twl4030.h"
#define GPMC_CS0_BASE 0x60
@ -140,10 +140,10 @@ static int beagle_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
if (system_rev >= 0x20 && system_rev <= 0x34301000) {
omap_cfg_reg(AG9_34XX_GPIO23);
omap_mux_init_gpio(23, OMAP_PIN_INPUT);
mmc[0].gpio_wp = 23;
} else {
omap_cfg_reg(AH8_34XX_GPIO29);
omap_mux_init_gpio(29, OMAP_PIN_INPUT);
}
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
@ -422,14 +422,23 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap3_beagle_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3_beagle_i2c_init();
platform_add_devices(omap3_beagle_devices,
ARRAY_SIZE(omap3_beagle_devices));
omap_serial_init();
omap_cfg_reg(J25_34XX_GPIO170);
omap_mux_init_gpio(170, OMAP_PIN_INPUT);
gpio_request(170, "DVI_nPD");
/* REVISIT leave DVI powered down until it's needed ... */
gpio_direction_output(170, true);
@ -439,8 +448,8 @@ static void __init omap3_beagle_init(void)
omap3beagle_flash_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
}
static void __init omap3_beagle_map_io(void)

21
arch/arm/mach-omap2/board-omap3evm.c
View File

@ -38,11 +38,11 @@
#include <asm/mach/map.h>
#include <plat/board.h>
#include <plat/mux.h>
#include <plat/usb.h>
#include <plat/common.h>
#include <plat/mcspi.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
#include "mmc-twl4030.h"
@ -223,7 +223,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
omap_cfg_reg(L8_34XX_GPIO63);
omap_mux_init_gpio(63, OMAP_PIN_INPUT);
mmc[0].gpio_cd = gpio + 0;
twl4030_mmc_init(mmc);
@ -422,9 +422,18 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap3_evm_init(void)
{
omap3_evm_get_revision();
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3_evm_i2c_init();
@ -440,24 +449,24 @@ static void __init omap3_evm_init(void)
#endif
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
/* enable EHCI VBUS using GPIO22 */
omap_cfg_reg(AF9_34XX_GPIO22);
omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP);
gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS");
gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0);
gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1);
/* Select EHCI port on main board */
omap_cfg_reg(U3_34XX_GPIO61);
omap_mux_init_gpio(61, OMAP_PIN_INPUT_PULLUP);
gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port");
gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0);
gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0);
/* setup EHCI phy reset config */
omap_cfg_reg(AH14_34XX_GPIO21);
omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
ehci_pdata.reset_gpio_port[1] = 21;
} else {
/* setup EHCI phy reset on MDC */
omap_cfg_reg(AF4_34XX_GPIO135_OUT);
omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
ehci_pdata.reset_gpio_port[1] = 135;
}
usb_musb_init();

41
arch/arm/mach-omap2/board-omap3pandora.c
View File

@ -40,8 +40,8 @@
#include <mach/hardware.h>
#include <plat/mcspi.h>
#include <plat/usb.h>
#include <plat/mux.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
#include "mmc-twl4030.h"
@ -98,10 +98,10 @@ static struct gpio_keys_button pandora_gpio_keys[] = {
GPIO_BUTTON_LOW(103, KEY_DOWN, "down"),
GPIO_BUTTON_LOW(96, KEY_LEFT, "left"),
GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"),
GPIO_BUTTON_LOW(111, BTN_A, "a"),
GPIO_BUTTON_LOW(106, BTN_B, "b"),
GPIO_BUTTON_LOW(109, BTN_X, "x"),
GPIO_BUTTON_LOW(101, BTN_Y, "y"),
GPIO_BUTTON_LOW(109, KEY_KP1, "game 1"),
GPIO_BUTTON_LOW(111, KEY_KP2, "game 2"),
GPIO_BUTTON_LOW(106, KEY_KP3, "game 3"),
GPIO_BUTTON_LOW(101, KEY_KP4, "game 4"),
GPIO_BUTTON_LOW(102, BTN_TL, "l"),
GPIO_BUTTON_LOW(97, BTN_TL2, "l2"),
GPIO_BUTTON_LOW(105, BTN_TR, "r"),
@ -315,7 +315,7 @@ static int __init omap3pandora_i2c_init(void)
omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo,
ARRAY_SIZE(omap3pandora_i2c_boardinfo));
/* i2c2 pins are not connected */
omap_register_i2c_bus(3, 400, NULL, 0);
omap_register_i2c_bus(3, 100, NULL, 0);
return 0;
}
@ -368,23 +368,8 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
}
};
static struct platform_device omap3pandora_lcd_device = {
.name = "pandora_lcd",
.id = -1,
};
static struct omap_lcd_config omap3pandora_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel omap3pandora_config[] __initdata = {
{ OMAP_TAG_LCD, &omap3pandora_lcd_config },
};
static void __init omap3pandora_init_irq(void)
{
omap_board_config = omap3pandora_config;
omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
@ -392,7 +377,6 @@ static void __init omap3pandora_init_irq(void)
}
static struct platform_device *omap3pandora_devices[] __initdata = {
&omap3pandora_lcd_device,
&pandora_leds_gpio,
&pandora_keys_gpio,
};
@ -409,8 +393,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap3pandora_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3pandora_i2c_init();
platform_add_devices(omap3pandora_devices,
ARRAY_SIZE(omap3pandora_devices));
@ -423,8 +416,8 @@ static void __init omap3pandora_init(void)
usb_musb_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
}
static void __init omap3pandora_map_io(void)

572
arch/arm/mach-omap2/board-omap3touchbook.c Normal file
View File

@ -0,0 +1,572 @@
/*
* linux/arch/arm/mach-omap2/board-omap3touchbook.c
*
* Copyright (C) 2009 Always Innovating
*
* Modified from mach-omap2/board-omap3beagleboard.c
*
* Initial code: Grégoire Gentil, Tim Yamin
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand.h>
#include <plat/mcspi.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/regulator/machine.h>
#include <linux/i2c/twl4030.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <plat/board.h>
#include <plat/common.h>
#include <plat/gpmc.h>
#include <plat/nand.h>
#include <plat/usb.h>
#include <plat/timer-gp.h>
#include "mux.h"
#include "mmc-twl4030.h"
#include <asm/setup.h>
#define GPMC_CS0_BASE 0x60
#define GPMC_CS_SIZE 0x30
#define NAND_BLOCK_SIZE SZ_128K
#define OMAP3_AC_GPIO 136
#define OMAP3_TS_GPIO 162
#define TB_BL_PWM_TIMER 9
#define TB_KILL_POWER_GPIO 168
unsigned long touchbook_revision;
static struct mtd_partition omap3touchbook_nand_partitions[] = {
/* All the partition sizes are listed in terms of NAND block size */
{
.name = "X-Loader",
.offset = 0,
.size = 4 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
{
.name = "U-Boot",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
.size = 15 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
{
.name = "U-Boot Env",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
.size = 1 * NAND_BLOCK_SIZE,
},
{
.name = "Kernel",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
.size = 32 * NAND_BLOCK_SIZE,
},
{
.name = "File System",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
.size = MTDPART_SIZ_FULL,
},
};
static struct omap_nand_platform_data omap3touchbook_nand_data = {
.options = NAND_BUSWIDTH_16,
.parts = omap3touchbook_nand_partitions,
.nr_parts = ARRAY_SIZE(omap3touchbook_nand_partitions),
.dma_channel = -1, /* disable DMA in OMAP NAND driver */
.nand_setup = NULL,
.dev_ready = NULL,
};
static struct resource omap3touchbook_nand_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device omap3touchbook_nand_device = {
.name = "omap2-nand",
.id = -1,
.dev = {
.platform_data = &omap3touchbook_nand_data,
},
.num_resources = 1,
.resource = &omap3touchbook_nand_resource,
};
#include "sdram-micron-mt46h32m32lf-6.h"
static struct twl4030_hsmmc_info mmc[] = {
{
.mmc = 1,
.wires = 8,
.gpio_wp = 29,
},
{} /* Terminator */
};
static struct platform_device omap3_touchbook_lcd_device = {
.name = "omap3touchbook_lcd",
.id = -1,
};
static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct regulator_consumer_supply touchbook_vmmc1_supply = {
.supply = "vmmc",
};
static struct regulator_consumer_supply touchbook_vsim_supply = {
.supply = "vmmc_aux",
};
static struct gpio_led gpio_leds[];
static int touchbook_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
if (system_rev >= 0x20 && system_rev <= 0x34301000) {
omap_mux_init_gpio(23, OMAP_PIN_INPUT);
mmc[0].gpio_wp = 23;
} else {
omap_mux_init_gpio(29, OMAP_PIN_INPUT);
}
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
twl4030_mmc_init(mmc);
/* link regulators to MMC adapters */
touchbook_vmmc1_supply.dev = mmc[0].dev;
touchbook_vsim_supply.dev = mmc[0].dev;
/* REVISIT: need ehci-omap hooks for external VBUS
* power switch and overcurrent detect
*/
gpio_request(gpio + 1, "EHCI_nOC");
gpio_direction_input(gpio + 1);
/* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
return 0;
}
static struct twl4030_gpio_platform_data touchbook_gpio_data = {
.gpio_base = OMAP_MAX_GPIO_LINES,
.irq_base = TWL4030_GPIO_IRQ_BASE,
.irq_end = TWL4030_GPIO_IRQ_END,
.use_leds = true,
.pullups = BIT(1),
.pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
| BIT(15) | BIT(16) | BIT(17),
.setup = touchbook_twl_gpio_setup,
};
static struct regulator_consumer_supply touchbook_vdac_supply = {
.supply = "vdac",
.dev = &omap3_touchbook_lcd_device.dev,
};
static struct regulator_consumer_supply touchbook_vdvi_supply = {
.supply = "vdvi",
.dev = &omap3_touchbook_lcd_device.dev,
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data touchbook_vmmc1 = {
.constraints = {
.min_uV = 1850000,
.max_uV = 3150000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &touchbook_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
static struct regulator_init_data touchbook_vsim = {
.constraints = {
.min_uV = 1800000,
.max_uV = 3000000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &touchbook_vsim_supply,
};
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
static struct regulator_init_data touchbook_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &touchbook_vdac_supply,
};
/* VPLL2 for digital video outputs */
static struct regulator_init_data touchbook_vpll2 = {
.constraints = {
.name = "VDVI",
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &touchbook_vdvi_supply,
};
static struct twl4030_usb_data touchbook_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_codec_audio_data touchbook_audio_data = {
.audio_mclk = 26000000,
};
static struct twl4030_codec_data touchbook_codec_data = {
.audio_mclk = 26000000,
.audio = &touchbook_audio_data,
};
static struct twl4030_platform_data touchbook_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.usb = &touchbook_usb_data,
.gpio = &touchbook_gpio_data,
.codec = &touchbook_codec_data,
.vmmc1 = &touchbook_vmmc1,
.vsim = &touchbook_vsim,
.vdac = &touchbook_vdac,
.vpll2 = &touchbook_vpll2,
};
static struct i2c_board_info __initdata touchbook_i2c_boardinfo[] = {
{
I2C_BOARD_INFO("twl4030", 0x48),
.flags = I2C_CLIENT_WAKE,
.irq = INT_34XX_SYS_NIRQ,
.platform_data = &touchbook_twldata,
},
};
static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
{
I2C_BOARD_INFO("bq27200", 0x55),
},
};
static int __init omap3_touchbook_i2c_init(void)
{
/* Standard TouchBook bus */
omap_register_i2c_bus(1, 2600, touchbook_i2c_boardinfo,
ARRAY_SIZE(touchbook_i2c_boardinfo));
/* Additional TouchBook bus */
omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
ARRAY_SIZE(touchBook_i2c_boardinfo));
return 0;
}
static void __init omap3_ads7846_init(void)
{
if (gpio_request(OMAP3_TS_GPIO, "ads7846_pen_down")) {
printk(KERN_ERR "Failed to request GPIO %d for "
"ads7846 pen down IRQ\n", OMAP3_TS_GPIO);
return;
}
gpio_direction_input(OMAP3_TS_GPIO);
omap_set_gpio_debounce(OMAP3_TS_GPIO, 1);
omap_set_gpio_debounce_time(OMAP3_TS_GPIO, 0xa);
}
static struct ads7846_platform_data ads7846_config = {
.x_min = 100,
.y_min = 265,
.x_max = 3950,
.y_max = 3750,
.x_plate_ohms = 40,
.pressure_max = 255,
.debounce_max = 10,
.debounce_tol = 5,
.debounce_rep = 1,
.gpio_pendown = OMAP3_TS_GPIO,
.keep_vref_on = 1,
};
static struct omap2_mcspi_device_config ads7846_mcspi_config = {
.turbo_mode = 0,
.single_channel = 1, /* 0: slave, 1: master */
};
static struct spi_board_info omap3_ads7846_spi_board_info[] __initdata = {
{
.modalias = "ads7846",
.bus_num = 4,
.chip_select = 0,
.max_speed_hz = 1500000,
.controller_data = &ads7846_mcspi_config,
.irq = OMAP_GPIO_IRQ(OMAP3_TS_GPIO),
.platform_data = &ads7846_config,
}
};
static struct gpio_led gpio_leds[] = {
{
.name = "touchbook::usr0",
.default_trigger = "heartbeat",
.gpio = 150,
},
{
.name = "touchbook::usr1",
.default_trigger = "mmc0",
.gpio = 149,
},
{
.name = "touchbook::pmu_stat",
.gpio = -EINVAL, /* gets replaced */
.active_low = true,
},
};
static struct gpio_led_platform_data gpio_led_info = {
.leds = gpio_leds,
.num_leds = ARRAY_SIZE(gpio_leds),
};
static struct platform_device leds_gpio = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &gpio_led_info,
},
};
static struct gpio_keys_button gpio_buttons[] = {
{
.code = BTN_EXTRA,
.gpio = 7,
.desc = "user",
.wakeup = 1,
},
{
.code = KEY_POWER,
.gpio = 183,
.desc = "power",
.wakeup = 1,
},
};
static struct gpio_keys_platform_data gpio_key_info = {
.buttons = gpio_buttons,
.nbuttons = ARRAY_SIZE(gpio_buttons),
};
static struct platform_device keys_gpio = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &gpio_key_info,
},
};
static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = {
{ OMAP_TAG_LCD, &omap3_touchbook_lcd_config },
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap3_touchbook_init_irq(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_board_config = omap3_touchbook_config;
omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
omap_gpio_init();
}
static struct platform_device *omap3_touchbook_devices[] __initdata = {
&omap3_touchbook_lcd_device,
&leds_gpio,
&keys_gpio,
};
static void __init omap3touchbook_flash_init(void)
{
u8 cs = 0;
u8 nandcs = GPMC_CS_NUM + 1;
u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
/* find out the chip-select on which NAND exists */
while (cs < GPMC_CS_NUM) {
u32 ret = 0;
ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
if ((ret & 0xC00) == 0x800) {
printk(KERN_INFO "Found NAND on CS%d\n", cs);
if (nandcs > GPMC_CS_NUM)
nandcs = cs;
}
cs++;
}
if (nandcs > GPMC_CS_NUM) {
printk(KERN_INFO "NAND: Unable to find configuration "
"in GPMC\n ");
return;
}
if (nandcs < GPMC_CS_NUM) {
omap3touchbook_nand_data.cs = nandcs;
omap3touchbook_nand_data.gpmc_cs_baseaddr = (void *)
(gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
omap3touchbook_nand_data.gpmc_baseaddr =
(void *) (gpmc_base_add);
printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
if (platform_device_register(&omap3touchbook_nand_device) < 0)
printk(KERN_ERR "Unable to register NAND device\n");
}
}
static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
.phy_reset = true,
.reset_gpio_port[0] = -EINVAL,
.reset_gpio_port[1] = 147,
.reset_gpio_port[2] = -EINVAL
};
static void omap3_touchbook_poweroff(void)
{
int r;
r = gpio_request(TB_KILL_POWER_GPIO, "DVI reset");
if (r < 0) {
printk(KERN_ERR "Unable to get kill power GPIO\n");
return;
}
gpio_direction_output(TB_KILL_POWER_GPIO, 0);
}
static void __init early_touchbook_revision(char **p)
{
if (!*p)
return;
strict_strtoul(*p, 10, &touchbook_revision);
}
__early_param("tbr=", early_touchbook_revision);
static void __init omap3_touchbook_init(void)
{
pm_power_off = omap3_touchbook_poweroff;
omap3_touchbook_i2c_init();
platform_add_devices(omap3_touchbook_devices,
ARRAY_SIZE(omap3_touchbook_devices));
omap_serial_init();
omap_mux_init_gpio(170, OMAP_PIN_INPUT);
gpio_request(176, "DVI_nPD");
/* REVISIT leave DVI powered down until it's needed ... */
gpio_direction_output(176, true);
/* Touchscreen and accelerometer */
spi_register_board_info(omap3_ads7846_spi_board_info,
ARRAY_SIZE(omap3_ads7846_spi_board_info));
omap3_ads7846_init();
usb_musb_init();
usb_ehci_init(&ehci_pdata);
omap3touchbook_flash_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
}
static void __init omap3_touchbook_map_io(void)
{
omap2_set_globals_343x();
omap2_map_common_io();
}
MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
/* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
.phys_io = 0x48000000,
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap3_touchbook_map_io,
.init_irq = omap3_touchbook_init_irq,
.init_machine = omap3_touchbook_init,
.timer = &omap_timer,
MACHINE_END

14
arch/arm/mach-omap2/board-overo.c
View File

@ -44,9 +44,9 @@
#include <plat/gpmc.h>
#include <mach/hardware.h>
#include <plat/nand.h>
#include <plat/mux.h>
#include <plat/usb.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
#include "mmc-twl4030.h"
@ -405,9 +405,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init overo_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
overo_i2c_init();
platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
omap_serial_init();
@ -418,8 +426,8 @@ static void __init overo_init(void)
overo_init_smsc911x();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
if ((gpio_request(OVERO_GPIO_W2W_NRESET,
"OVERO_GPIO_W2W_NRESET") == 0) &&

9
arch/arm/mach-omap2/board-rx51-peripherals.c
View File

@ -33,6 +33,7 @@
#include <plat/onenand.h>
#include <plat/gpmc-smc91x.h>
#include "mux.h"
#include "mmc-twl4030.h"
#define SYSTEM_REV_B_USES_VAUX3 0x1699
@ -59,7 +60,7 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
.bus_num = 4,
.chip_select = 0,
.max_speed_hz = 48000000,
.mode = SPI_MODE_2,
.mode = SPI_MODE_3,
.controller_data = &wl1251_mcspi_config,
.platform_data = &wl1251_pdata,
},
@ -630,9 +631,9 @@ static struct omap_smc91x_platform_data board_smc91x_data = {
static void __init board_smc91x_init(void)
{
omap_cfg_reg(U8_34XX_GPIO54_DOWN);
omap_cfg_reg(G25_34XX_GPIO86_OUT);
omap_cfg_reg(H19_34XX_GPIO164_OUT);
omap_mux_init_gpio(54, OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_gpio(86, OMAP_PIN_OUTPUT);
omap_mux_init_gpio(164, OMAP_PIN_OUTPUT);
gpmc_smc91x_init(&board_smc91x_data);
}

16
arch/arm/mach-omap2/board-rx51.c
View File

@ -23,13 +23,14 @@
#include <asm/mach/map.h>
#include <plat/mcspi.h>
#include <plat/mux.h>
#include <plat/board.h>
#include <plat/common.h>
#include <plat/dma.h>
#include <plat/gpmc.h>
#include <plat/usb.h>
#include "mux.h"
struct omap_sdrc_params *rx51_get_sdram_timings(void);
static struct omap_lcd_config rx51_lcd_config = {
@ -69,15 +70,24 @@ static void __init rx51_init_irq(void)
extern void __init rx51_peripherals_init(void);
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init rx51_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_serial_init();
usb_musb_init();
rx51_peripherals_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
}
static void __init rx51_map_io(void)

14
arch/arm/mach-omap2/board-zoom-peripherals.c
View File

@ -152,14 +152,20 @@ static struct regulator_init_data zoom_vsim = {
static struct twl4030_hsmmc_info mmc[] __initdata = {
{
.name = "external",
.mmc = 1,
.wires = 4,
.gpio_wp = -EINVAL,
.power_saving = true,
},
{
.name = "internal",
.mmc = 2,
.wires = 4,
.wires = 8,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.nonremovable = true,
.power_saving = true,
},
{} /* Terminator */
};
@ -167,11 +173,8 @@ static struct twl4030_hsmmc_info mmc[] __initdata = {
static int zoom_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
/* gpio + 0 is "mmc0_cd" (input/IRQ),
* gpio + 1 is "mmc1_cd" (input/IRQ)
*/
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
mmc[1].gpio_cd = gpio + 1;
twl4030_mmc_init(mmc);
/* link regulators to MMC adapters ... we "know" the
@ -236,6 +239,7 @@ static struct twl4030_platform_data zoom_twldata = {
.gpio = &zoom_gpio_data,
.keypad = &zoom_kp_twl4030_data,
.codec = &zoom_codec_data,
.vmmc1 = &zoom_vmmc1,
.vmmc2 = &zoom_vmmc2,
.vsim = &zoom_vsim,

10
arch/arm/mach-omap2/board-zoom2.c
View File

@ -23,6 +23,7 @@
#include <mach/board-zoom.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
static void __init omap_zoom2_init_irq(void)
@ -68,8 +69,17 @@ static struct twl4030_platform_data zoom2_twldata = {
#endif
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap_zoom2_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
zoom_peripherals_init();
zoom_debugboard_init();
}

10
arch/arm/mach-omap2/board-zoom3.c
View File

@ -21,6 +21,7 @@
#include <plat/common.h>
#include <plat/board.h>
#include "mux.h"
#include "sdram-hynix-h8mbx00u0mer-0em.h"
static void __init omap_zoom_map_io(void)
@ -42,8 +43,17 @@ static void __init omap_zoom_init_irq(void)
omap_gpio_init();
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap_zoom_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
zoom_peripherals_init();
zoom_debugboard_init();
}

62
arch/arm/mach-omap2/devices.c
View File

@ -27,6 +27,8 @@
#include <mach/gpio.h>
#include <plat/mmc.h>
#include "mux.h"
#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
static struct resource cam_resources[] = {
@ -595,27 +597,40 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
if (cpu_is_omap34xx()) {
if (controller_nr == 0) {
omap_cfg_reg(N28_3430_MMC1_CLK);
omap_cfg_reg(M27_3430_MMC1_CMD);
omap_cfg_reg(N27_3430_MMC1_DAT0);
omap_mux_init_signal("sdmmc1_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat0",
OMAP_PIN_INPUT_PULLUP);
if (mmc_controller->slots[0].wires == 4 ||
mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(N26_3430_MMC1_DAT1);
omap_cfg_reg(N25_3430_MMC1_DAT2);
omap_cfg_reg(P28_3430_MMC1_DAT3);
omap_mux_init_signal("sdmmc1_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(P27_3430_MMC1_DAT4);
omap_cfg_reg(P26_3430_MMC1_DAT5);
omap_cfg_reg(R27_3430_MMC1_DAT6);
omap_cfg_reg(R25_3430_MMC1_DAT7);
omap_mux_init_signal("sdmmc1_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
if (controller_nr == 1) {
/* MMC2 */
omap_cfg_reg(AE2_3430_MMC2_CLK);
omap_cfg_reg(AG5_3430_MMC2_CMD);
omap_cfg_reg(AH5_3430_MMC2_DAT0);
omap_mux_init_signal("sdmmc2_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat0",
OMAP_PIN_INPUT_PULLUP);
/*
* For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
@ -623,15 +638,22 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
*/
if (mmc_controller->slots[0].wires == 4 ||
mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(AH4_3430_MMC2_DAT1);
omap_cfg_reg(AG4_3430_MMC2_DAT2);
omap_cfg_reg(AF4_3430_MMC2_DAT3);
omap_mux_init_signal("sdmmc2_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(AE4_3430_MMC2_DAT4);
omap_cfg_reg(AH3_3430_MMC2_DAT5);
omap_cfg_reg(AF3_3430_MMC2_DAT6);
omap_cfg_reg(AE3_3430_MMC2_DAT7);
omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}

8
arch/arm/mach-omap2/gpmc-smc91x.c
View File

@ -33,17 +33,19 @@ static struct resource gpmc_smc91x_resources[] = {
};
static struct smc91x_platdata gpmc_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct platform_device gpmc_smc91x_device = {
.name = "smc91x",
.id = -1,
.num_resources = ARRAY_SIZE(gpmc_smc91x_resources),
.resource = gpmc_smc91x_resources,
.dev = {
.platform_data = &gpmc_smc91x_info,
},
.num_resources = ARRAY_SIZE(gpmc_smc91x_resources),
.resource = gpmc_smc91x_resources,
};
/*

56
arch/arm/mach-omap2/i2c.c Normal file
View File

@ -0,0 +1,56 @@
/*
* Helper module for board specific I2C bus registration
*
* Copyright (C) 2009 Nokia Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <plat/cpu.h>
#include <plat/i2c.h>
#include <plat/mux.h>
#include "mux.h"
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
if (cpu_is_omap24xx()) {
const int omap24xx_pins[][2] = {
{ M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
{ J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
};
int scl, sda;
scl = omap24xx_pins[bus_id - 1][0];
sda = omap24xx_pins[bus_id - 1][1];
omap_cfg_reg(sda);
omap_cfg_reg(scl);
}
/* First I2C bus is not muxable */
if (cpu_is_omap34xx() && bus_id > 1) {
char mux_name[sizeof("i2c2_scl.i2c2_scl")];
sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
}
return omap_plat_register_i2c_bus(bus_id, clkrate, info, len);
}

31
arch/arm/mach-omap2/id.c
View File

@ -246,6 +246,31 @@ void __init omap3_check_revision(void)
}
}
void __init omap4_check_revision(void)
{
u32 idcode;
u16 hawkeye;
u8 rev;
char *rev_name = "ES1.0";
/*
* The IC rev detection is done with hawkeye and rev.
* Note that rev does not map directly to defined processor
* revision numbers as ES1.0 uses value 0.
*/
idcode = read_tap_reg(OMAP_TAP_IDCODE);
hawkeye = (idcode >> 12) & 0xffff;
rev = (idcode >> 28) & 0xff;
if ((hawkeye == 0xb852) && (rev == 0x0)) {
omap_revision = OMAP4430_REV_ES1_0;
pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
return;
}
pr_err("Unknown OMAP4 CPU id\n");
}
#define OMAP3_SHOW_FEATURE(feat) \
if (omap3_has_ ##feat()) \
printk(#feat" ");
@ -277,10 +302,10 @@ void __init omap3_cpuinfo(void)
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
strcpy(cpu_name, "OMAP3430/3530");
} else if (omap3_has_sgx()) {
} else if (omap3_has_iva()) {
omap_revision = OMAP3525_REV(rev);
strcpy(cpu_name, "OMAP3525");
} else if (omap3_has_iva()) {
} else if (omap3_has_sgx()) {
omap_revision = OMAP3515_REV(rev);
strcpy(cpu_name, "OMAP3515");
} else {
@ -336,7 +361,7 @@ void __init omap2_check_revision(void)
omap3_check_features();
omap3_cpuinfo();
} else if (cpu_is_omap44xx()) {
printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
omap4_check_revision();
return;
} else {
pr_err("OMAP revision unknown, please fix!\n");

1
arch/arm/mach-omap2/io.c
View File

@ -33,6 +33,7 @@
#include <plat/sdrc.h>
#include <plat/gpmc.h>
#include <plat/serial.h>
#include <plat/mux.h>
#include <plat/vram.h>
#include "clock.h"

1071
arch/arm/mach-omap2/mux.c
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163
arch/arm/mach-omap2/mux.h Normal file
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@ -0,0 +1,163 @@
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "mux34xx.h"
#define OMAP_MUX_TERMINATOR 0xffff
/* 34xx mux mode options for each pin. See TRM for options */
#define OMAP_MUX_MODE0 0
#define OMAP_MUX_MODE1 1
#define OMAP_MUX_MODE2 2
#define OMAP_MUX_MODE3 3
#define OMAP_MUX_MODE4 4
#define OMAP_MUX_MODE5 5
#define OMAP_MUX_MODE6 6
#define OMAP_MUX_MODE7 7
/* 24xx/34xx mux bit defines */
#define OMAP_PULL_ENA (1 << 3)
#define OMAP_PULL_UP (1 << 4)
#define OMAP_ALTELECTRICALSEL (1 << 5)
/* 34xx specific mux bit defines */
#define OMAP_INPUT_EN (1 << 8)
#define OMAP_OFF_EN (1 << 9)
#define OMAP_OFFOUT_EN (1 << 10)
#define OMAP_OFFOUT_VAL (1 << 11)
#define OMAP_OFF_PULL_EN (1 << 12)
#define OMAP_OFF_PULL_UP (1 << 13)
#define OMAP_WAKEUP_EN (1 << 14)
/* Active pin states */
#define OMAP_PIN_OUTPUT 0
#define OMAP_PIN_INPUT OMAP_INPUT_EN
#define OMAP_PIN_INPUT_PULLUP (OMAP_PULL_ENA | OMAP_INPUT_EN \
| OMAP_PULL_UP)
#define OMAP_PIN_INPUT_PULLDOWN (OMAP_PULL_ENA | OMAP_INPUT_EN)
/* Off mode states */
#define OMAP_PIN_OFF_NONE 0
#define OMAP_PIN_OFF_OUTPUT_HIGH (OMAP_OFF_EN | OMAP_OFFOUT_EN \
| OMAP_OFFOUT_VAL)
#define OMAP_PIN_OFF_OUTPUT_LOW (OMAP_OFF_EN | OMAP_OFFOUT_EN)
#define OMAP_PIN_OFF_INPUT_PULLUP (OMAP_OFF_EN | OMAP_OFF_PULL_EN \
| OMAP_OFF_PULL_UP)
#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
/* Flags for omap_mux_init */
#define OMAP_PACKAGE_MASK 0xffff
#define OMAP_PACKAGE_CBP 4 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CUS 3 /* 423-pin 0.65 */
#define OMAP_PACKAGE_CBB 2 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CBC 1 /* 515-pin 0.50 0.65 */
#define OMAP_MUX_NR_MODES 8 /* Available modes */
#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
/**
* struct omap_mux - data for omap mux register offset and it's value
* @reg_offset: mux register offset from the mux base
* @gpio: GPIO number
* @muxnames: available signal modes for a ball
*/
struct omap_mux {
u16 reg_offset;
u16 gpio;
#ifdef CONFIG_OMAP_MUX
char *muxnames[OMAP_MUX_NR_MODES];
#ifdef CONFIG_DEBUG_FS
char *balls[OMAP_MUX_NR_SIDES];
#endif
#endif
};
/**
* struct omap_ball - data for balls on omap package
* @reg_offset: mux register offset from the mux base
* @balls: available balls on the package
*/
struct omap_ball {
u16 reg_offset;
char *balls[OMAP_MUX_NR_SIDES];
};
/**
* struct omap_board_mux - data for initializing mux registers
* @reg_offset: mux register offset from the mux base
* @mux_value: desired mux value to set
*/
struct omap_board_mux {
u16 reg_offset;
u16 value;
};
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP34XX)
/**
* omap_mux_init_gpio - initialize a signal based on the GPIO number
* @gpio: GPIO number
* @val: Options for the mux register value
*/
int omap_mux_init_gpio(int gpio, int val);
/**
* omap_mux_init_signal - initialize a signal based on the signal name
* @muxname: Mux name in mode0_name.signal_name format
* @val: Options for the mux register value
*/
int omap_mux_init_signal(char *muxname, int val);
#else
static inline int omap_mux_init_gpio(int gpio, int val)
{
return 0;
}
static inline int omap_mux_init_signal(char *muxname, int val)
{
return 0;
}
#endif
/**
* omap_mux_get_gpio() - get mux register value based on GPIO number
* @gpio: GPIO number
*
*/
u16 omap_mux_get_gpio(int gpio);
/**
* omap_mux_set_gpio() - set mux register value based on GPIO number
* @val: New mux register value
* @gpio: GPIO number
*
*/
void omap_mux_set_gpio(u16 val, int gpio);
/**
* omap3_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
* @flags: OMAP package type used for the board
*/
int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
/**
* omap_mux_init - private mux init function, do not call
*/
int omap_mux_init(u32 mux_pbase, u32 mux_size,
struct omap_mux *superset,
struct omap_mux *package_subset,
struct omap_board_mux *board_mux,
struct omap_ball *package_balls);

2099
arch/arm/mach-omap2/mux34xx.c Normal file
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398
arch/arm/mach-omap2/mux34xx.h Normal file
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@ -0,0 +1,398 @@
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU
#define OMAP3_MUX(mode0, mux_value) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
.value = (mux_value), \
}
/*
* OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
*
* Extracted from the TRM. Add 0x48002030 to these values to get the
* absolute addresses. The name in the macro is the mode-0 name of
* the pin. NOTE: These registers are 16-bits wide.
*
* Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
* of CHASSIS for some registers. For the defines, we follow the
* 36XX naming, and use SDMMC and CHASSIS.
*/
#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000
#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002
#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004
#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006
#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008
#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a
#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c
#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e
#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010
#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012
#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014
#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016
#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018
#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a
#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c
#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e
#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020
#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022
#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024
#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026
#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028
#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a
#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c
#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e
#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030
#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032
#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034
#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036
#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a
#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c
#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e
#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040
#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042
#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044
#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046
#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048
#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c
#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e
#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050
#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052
#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054
#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056
#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058
#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a
#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c
#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e
#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060
#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062
#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064
#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066
#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068
#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a
#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c
#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e
#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070
#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072
#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074
#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076
#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078
#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a
#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c
#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e
#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080
#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082
#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084
#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086
#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088
#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a
#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c
#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e
#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090
#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092
#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094
#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096
#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098
#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2
#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4
#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6
#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8
#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa
#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac
#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae
#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0
#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2
#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4
#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6
#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8
#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba
#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc
#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be
#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0
#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2
#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4
#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6
#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8
#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca
#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc
#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce
#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0
#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2
#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4
#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6
#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8
#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da
#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc
#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de
#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0
#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2
#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4
#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6
#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8
#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea
#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec
#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee
#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0
#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2
#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4
#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6
#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8
#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa
#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc
#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe
#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100
#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102
#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104
#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106
#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108
#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a
#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c
#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e
#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110
#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112
#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114
#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e
/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126
#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128
#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a
#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c
#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e
#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140
#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142
#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144
#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146
#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148
#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a
#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c
#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e
#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150
#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152
#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154
#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156
#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158
#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a
#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c
#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e
#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160
#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162
#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164
#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166
#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168
#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a
#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c
#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e
#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170
#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172
#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174
#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176
#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188
#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a
#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c
#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e
#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190
#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192
#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194
#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196
#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198
#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a
#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4
#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6
#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8
#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa
#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac
#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae
#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc
/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe
#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200
#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202
#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204
#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206
#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208
#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212
#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214
#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216
#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218
#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a
#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c
#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e
#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220
#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222
#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224
#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226
#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228
#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a
#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c
#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e
#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230
#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232
#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234
/* 36xx only */
#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236
#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570
#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572
#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574
#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576
#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578
#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a
#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c
#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e
#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580
#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582
#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584
#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586
#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588
#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a
#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c
#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e
#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590
#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592
#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594
#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596
#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598
#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a
#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c
#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e
#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0
#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2
#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4
/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120
#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122
#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124
#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126
#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8
#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa
#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac
#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae
#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0
#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2
#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4
#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6
#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8
#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba
#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc
#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be
#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0
#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2
#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4
#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6
#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8
#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca
#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0
#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2
#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4
#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6
#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8
#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da
#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc
#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de
#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0
#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2
#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4
#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6
#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea
#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec
#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee
#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0
#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2
#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4
#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6
#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c
#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e
#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20
#define OMAP3_CONTROL_PADCONF_MUX_SIZE \
(OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x2)

35
arch/arm/mach-omap2/omap-headsmp.S
View File

@ -27,20 +27,39 @@
* OMAP4 specific entry point for secondary CPU to jump from ROM
* code. This routine also provides a holding flag into which
* secondary core is held until we're ready for it to initialise.
* The primary core will update the this flag using a hardware
* register AuxCoreBoot1.
* The primary core will update this flag using a hardware
* register AuxCoreBoot0.
*/
ENTRY(omap_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #0x0f
hold: ldr r1, =OMAP4_AUX_CORE_BOOT1_PA @ read from AuxCoreBoot1
ldr r2, [r1]
cmp r2, r0
hold: ldr r12,=0x103
dsb
smc @ read from AuxCoreBoot0
mov r0, r0, lsr #9
mrc p15, 0, r4, c0, c0, 5
and r4, r4, #0x0f
cmp r0, r4
bne hold
/*
* we've been released from the cpu_release,secondary_stack
* we've been released from the wait loop,secondary_stack
* should now contain the SVC stack for this core
*/
b secondary_startup
END(omap_secondary_startup)
ENTRY(omap_modify_auxcoreboot0)
stmfd sp!, {r1-r12, lr}
ldr r12, =0x104
dsb
smc
ldmfd sp!, {r1-r12, pc}
END(omap_modify_auxcoreboot0)
ENTRY(omap_auxcoreboot_addr)
stmfd sp!, {r2-r12, lr}
ldr r12, =0x105
dsb
smc
ldmfd sp!, {r2-r12, pc}
END(omap_auxcoreboot_addr)

31
arch/arm/mach-omap2/omap-smp.c
View File

@ -17,19 +17,15 @@
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <asm/localtimer.h>
#include <asm/smp_scu.h>
#include <mach/hardware.h>
#include <plat/common.h>
/* Registers used for communicating startup information */
static void __iomem *omap4_auxcoreboot_reg0;
static void __iomem *omap4_auxcoreboot_reg1;
/* SCU base address */
static void __iomem *scu_base;
@ -65,8 +61,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
/*
* Set synchronisation state between this boot processor
* and the secondary one
@ -74,18 +68,15 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
spin_lock(&boot_lock);
/*
* Update the AuxCoreBoot1 with boot state for secondary core.
* Update the AuxCoreBoot0 with boot state for secondary core.
* omap_secondary_startup() routine will hold the secondary core till
* the AuxCoreBoot1 register is updated with cpu state
* A barrier is added to ensure that write buffer is drained
*/
__raw_writel(cpu, omap4_auxcoreboot_reg1);
omap_modify_auxcoreboot0(0x200, 0x0);
flush_cache_all();
smp_wmb();
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout))
;
/*
* Now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
@ -99,17 +90,18 @@ static void __init wakeup_secondary(void)
{
/*
* Write the address of secondary startup routine into the
* AuxCoreBoot0 where ROM code will jump and start executing
* AuxCoreBoot1 where ROM code will jump and start executing
* on secondary core once out of WFE
* A barrier is added to ensure that write buffer is drained
*/
__raw_writel(virt_to_phys(omap_secondary_startup), \
omap4_auxcoreboot_reg0);
omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
smp_wmb();
/*
* Send a 'sev' to wake the secondary core from WFE.
* Drain the outstanding writes to memory
*/
dsb();
set_event();
mb();
}
@ -136,7 +128,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
{
unsigned int ncores = get_core_count();
unsigned int cpu = smp_processor_id();
void __iomem *omap4_wkupgen_base;
int i;
/* sanity check */
@ -168,12 +159,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
for (i = 0; i < max_cpus; i++)
set_cpu_present(i, true);
/* Never released */
omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
BUG_ON(!omap4_wkupgen_base);
omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800;
omap4_auxcoreboot_reg1 = omap4_wkupgen_base + 0x804;
if (max_cpus > 1) {
/*
* Enable the local timer or broadcast device for the

90
arch/arm/mach-omap2/serial.c
View File

@ -33,6 +33,7 @@
#include "pm.h"
#include "prm-regbits-34xx.h"
#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
#define UART_OMAP_WER 0x17 /* Wake-up enable register */
#define DEFAULT_TIMEOUT (5 * HZ)
@ -572,6 +573,23 @@ static struct omap_uart_state omap_uart[] = {
#endif
};
/*
* Override the default 8250 read handler: mem_serial_in()
* Empty RX fifo read causes an abort on omap3630 and omap4
* This function makes sure that an empty rx fifo is not read on these silicons
* (OMAP1/2/3430 are not affected)
*/
static unsigned int serial_in_override(struct uart_port *up, int offset)
{
if (UART_RX == offset) {
unsigned int lsr;
lsr = serial_read_reg(omap_uart[up->line].p, UART_LSR);
if (!(lsr & UART_LSR_DR))
return -EPERM;
}
return serial_read_reg(omap_uart[up->line].p, offset);
}
void __init omap_serial_early_init(void)
{
int i;
@ -631,24 +649,64 @@ void __init omap_serial_early_init(void)
}
}
/**
* omap_serial_init_port() - initialize single serial port
* @port: serial port number (0-3)
*
* This function initialies serial driver for given @port only.
* Platforms can call this function instead of omap_serial_init()
* if they don't plan to use all available UARTs as serial ports.
*
* Don't mix calls to omap_serial_init_port() and omap_serial_init(),
* use only one of the two.
*/
void __init omap_serial_init_port(int port)
{
struct omap_uart_state *uart;
struct platform_device *pdev;
struct device *dev;
BUG_ON(port < 0);
BUG_ON(port >= ARRAY_SIZE(omap_uart));
uart = &omap_uart[port];
pdev = &uart->pdev;
dev = &pdev->dev;
omap_uart_reset(uart);
omap_uart_idle_init(uart);
if (WARN_ON(platform_device_register(pdev)))
return;
if ((cpu_is_omap34xx() && uart->padconf) ||
(uart->wk_en && uart->wk_mask)) {
device_init_wakeup(dev, true);
DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
}
/* omap44xx: Never read empty UART fifo
* omap3xxx: Never read empty UART fifo on UARTs
* with IP rev >=0x52
*/
if (cpu_is_omap44xx())
uart->p->serial_in = serial_in_override;
else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
uart->p->serial_in = serial_in_override;
}
/**
* omap_serial_init() - intialize all supported serial ports
*
* Initializes all available UARTs as serial ports. Platforms
* can call this function when they want to have default behaviour
* for serial ports (e.g initialize them all as serial ports).
*/
void __init omap_serial_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
struct omap_uart_state *uart = &omap_uart[i];
struct platform_device *pdev = &uart->pdev;
struct device *dev = &pdev->dev;
omap_uart_reset(uart);
omap_uart_idle_init(uart);
if (WARN_ON(platform_device_register(pdev)))
continue;
if ((cpu_is_omap34xx() && uart->padconf) ||
(uart->wk_en && uart->wk_mask)) {
device_init_wakeup(dev, true);
DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
}
}
for (i = 0; i < ARRAY_SIZE(omap_uart); i++)
omap_serial_init_port(i);
}

166
arch/arm/mach-omap2/usb-ehci.c
View File

@ -27,6 +27,8 @@
#include <mach/irqs.h>
#include <plat/usb.h>
#include "mux.h"
#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
static struct resource ehci_resources[] = {
@ -72,32 +74,44 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
{
switch (port_mode[0]) {
case EHCI_HCD_OMAP_MODE_PHY:
omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
break;
case EHCI_HCD_OMAP_MODE_TLL:
omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
omap_mux_init_signal("hsusb1_tll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hsusb1_tll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case EHCI_HCD_OMAP_MODE_UNKNOWN:
/* FALLTHROUGH */
@ -107,32 +121,52 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
switch (port_mode[1]) {
case EHCI_HCD_OMAP_MODE_PHY:
omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case EHCI_HCD_OMAP_MODE_TLL:
omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
omap_mux_init_signal("hsusb2_tll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hsusb2_tll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case EHCI_HCD_OMAP_MODE_UNKNOWN:
/* FALLTHROUGH */
@ -145,18 +179,30 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
break;
case EHCI_HCD_OMAP_MODE_TLL:
omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
omap_mux_init_signal("hsusb3_tll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hsusb3_tll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case EHCI_HCD_OMAP_MODE_UNKNOWN:
/* FALLTHROUGH */

2
arch/arm/plat-omap/common.c
View File

@ -280,7 +280,7 @@ void __init omap2_set_globals_343x(void)
#if defined(CONFIG_ARCH_OMAP4)
static struct omap_globals omap4_globals = {
.class = OMAP443X_CLASS,
.tap = OMAP2_L4_IO_ADDRESS(0x4830a000),
.tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
.ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
.prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
.cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),

10
arch/arm/plat-omap/debug-devices.c
View File

@ -13,6 +13,7 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
@ -24,6 +25,12 @@
* platforms include H2, H3, H4, and Perseus2.
*/
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource smc91x_resources[] = {
[0] = {
.flags = IORESOURCE_MEM,
@ -36,6 +43,9 @@ static struct resource smc91x_resources[] = {
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = -1,
.dev = {
.platform_data = &smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};

68
arch/arm/plat-omap/devices.c
View File

@ -242,6 +242,39 @@ fail:
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
#ifdef CONFIG_ARCH_OMAP24XX
#define OMAP_RNG_BASE 0x480A0000
#else
#define OMAP_RNG_BASE 0xfffe5000
#endif
static struct resource rng_resources[] = {
{
.start = OMAP_RNG_BASE,
.end = OMAP_RNG_BASE + 0x4f,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap_rng_device = {
.name = "omap_rng",
.id = -1,
.num_resources = ARRAY_SIZE(rng_resources),
.resource = rng_resources,
};
static void omap_init_rng(void)
{
(void) platform_device_register(&omap_rng_device);
}
#else
static inline void omap_init_rng(void) {}
#endif
/*-------------------------------------------------------------------------*/
/* Numbering for the SPI-capable controllers when used for SPI:
* spi = 1
* uwire = 2
@ -324,39 +357,6 @@ static void omap_init_wdt(void)
static inline void omap_init_wdt(void) {}
#endif
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
#ifdef CONFIG_ARCH_OMAP24XX
#define OMAP_RNG_BASE 0x480A0000
#else
#define OMAP_RNG_BASE 0xfffe5000
#endif
static struct resource rng_resources[] = {
{
.start = OMAP_RNG_BASE,
.end = OMAP_RNG_BASE + 0x4f,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap_rng_device = {
.name = "omap_rng",
.id = -1,
.num_resources = ARRAY_SIZE(rng_resources),
.resource = rng_resources,
};
static void omap_init_rng(void)
{
(void) platform_device_register(&omap_rng_device);
}
#else
static inline void omap_init_rng(void) {}
#endif
/*
* This gets called after board-specific INIT_MACHINE, and initializes most
* on-chip peripherals accessible on this board (except for few like USB):
@ -384,9 +384,9 @@ static int __init omap_init_devices(void)
*/
omap_init_dsp();
omap_init_kp();
omap_init_rng();
omap_init_uwire();
omap_init_wdt();
omap_init_rng();
return 0;
}
arch_initcall(omap_init_devices);

410
arch/arm/plat-omap/dma.c
View File

@ -47,7 +47,6 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
#endif
#define OMAP_DMA_ACTIVE 0x01
#define OMAP_DMA_CCR_EN (1 << 7)
#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
@ -1120,17 +1119,8 @@ int omap_dma_running(void)
{
int lch;
/*
* On OMAP1510, internal LCD controller will start the transfer
* when it gets enabled, so assume DMA running if LCD enabled.
*/
if (cpu_is_omap1510())
if (omap_readw(0xfffec000 + 0x00) & (1 << 0))
return 1;
/* Check if LCD DMA is running */
if (cpu_is_omap16xx())
if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
if (cpu_class_is_omap1())
if (omap_lcd_dma_running())
return 1;
for (lch = 0; lch < dma_chan_count; lch++)
@ -1990,377 +1980,6 @@ static struct irqaction omap24xx_dma_irq;
/*----------------------------------------------------------------------------*/
static struct lcd_dma_info {
spinlock_t lock;
int reserved;
void (*callback)(u16 status, void *data);
void *cb_data;
int active;
unsigned long addr, size;
int rotate, data_type, xres, yres;
int vxres;
int mirror;
int xscale, yscale;
int ext_ctrl;
int src_port;
int single_transfer;
} lcd_dma;
void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
int data_type)
{
lcd_dma.addr = addr;
lcd_dma.data_type = data_type;
lcd_dma.xres = fb_xres;
lcd_dma.yres = fb_yres;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1);
void omap_set_lcd_dma_src_port(int port)
{
lcd_dma.src_port = port;
}
void omap_set_lcd_dma_ext_controller(int external)
{
lcd_dma.ext_ctrl = external;
}
EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
void omap_set_lcd_dma_single_transfer(int single)
{
lcd_dma.single_transfer = single;
}
EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
void omap_set_lcd_dma_b1_rotation(int rotate)
{
if (omap_dma_in_1510_mode()) {
printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
BUG();
return;
}
lcd_dma.rotate = rotate;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
void omap_set_lcd_dma_b1_mirror(int mirror)
{
if (omap_dma_in_1510_mode()) {
printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
BUG();
}
lcd_dma.mirror = mirror;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
{
if (omap_dma_in_1510_mode()) {
printk(KERN_ERR "DMA virtual resulotion is not supported "
"in 1510 mode\n");
BUG();
}
lcd_dma.vxres = vxres;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
{
if (omap_dma_in_1510_mode()) {
printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
BUG();
}
lcd_dma.xscale = xscale;
lcd_dma.yscale = yscale;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
static void set_b1_regs(void)
{
unsigned long top, bottom;
int es;
u16 w;
unsigned long en, fn;
long ei, fi;
unsigned long vxres;
unsigned int xscale, yscale;
switch (lcd_dma.data_type) {
case OMAP_DMA_DATA_TYPE_S8:
es = 1;
break;
case OMAP_DMA_DATA_TYPE_S16:
es = 2;
break;
case OMAP_DMA_DATA_TYPE_S32:
es = 4;
break;
default:
BUG();
return;
}
vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
BUG_ON(vxres < lcd_dma.xres);
#define PIXADDR(x, y) (lcd_dma.addr + \
((y) * vxres * yscale + (x) * xscale) * es)
#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
switch (lcd_dma.rotate) {
case 0:
if (!lcd_dma.mirror) {
top = PIXADDR(0, 0);
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
/* 1510 DMA requires the bottom address to be 2 more
* than the actual last memory access location. */
if (omap_dma_in_1510_mode() &&
lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
bottom += 2;
ei = PIXSTEP(0, 0, 1, 0);
fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
} else {
top = PIXADDR(lcd_dma.xres - 1, 0);
bottom = PIXADDR(0, lcd_dma.yres - 1);
ei = PIXSTEP(1, 0, 0, 0);
fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
}
en = lcd_dma.xres;
fn = lcd_dma.yres;
break;
case 90:
if (!lcd_dma.mirror) {
top = PIXADDR(0, lcd_dma.yres - 1);
bottom = PIXADDR(lcd_dma.xres - 1, 0);
ei = PIXSTEP(0, 1, 0, 0);
fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
} else {
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
bottom = PIXADDR(0, 0);
ei = PIXSTEP(0, 1, 0, 0);
fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
}
en = lcd_dma.yres;
fn = lcd_dma.xres;
break;
case 180:
if (!lcd_dma.mirror) {
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
bottom = PIXADDR(0, 0);
ei = PIXSTEP(1, 0, 0, 0);
fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
} else {
top = PIXADDR(0, lcd_dma.yres - 1);
bottom = PIXADDR(lcd_dma.xres - 1, 0);
ei = PIXSTEP(0, 0, 1, 0);
fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
}
en = lcd_dma.xres;
fn = lcd_dma.yres;
break;
case 270:
if (!lcd_dma.mirror) {
top = PIXADDR(lcd_dma.xres - 1, 0);
bottom = PIXADDR(0, lcd_dma.yres - 1);
ei = PIXSTEP(0, 0, 0, 1);
fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
} else {
top = PIXADDR(0, 0);
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
ei = PIXSTEP(0, 0, 0, 1);
fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
}
en = lcd_dma.yres;
fn = lcd_dma.xres;
break;
default:
BUG();
return; /* Suppress warning about uninitialized vars */
}
if (omap_dma_in_1510_mode()) {
omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
return;
}
/* 1610 regs */
omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
w = omap_readw(OMAP1610_DMA_LCD_CSDP);
w &= ~0x03;
w |= lcd_dma.data_type;
omap_writew(w, OMAP1610_DMA_LCD_CSDP);
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
/* Always set the source port as SDRAM for now*/
w &= ~(0x03 << 6);
if (lcd_dma.callback != NULL)
w |= 1 << 1; /* Block interrupt enable */
else
w &= ~(1 << 1);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
if (!(lcd_dma.rotate || lcd_dma.mirror ||
lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
return;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
/* Set the double-indexed addressing mode */
w |= (0x03 << 12);
omap_writew(w, OMAP1610_DMA_LCD_CCR);
omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
}
static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
{
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
if (unlikely(!(w & (1 << 3)))) {
printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
return IRQ_NONE;
}
/* Ack the IRQ */
w |= (1 << 3);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
lcd_dma.active = 0;
if (lcd_dma.callback != NULL)
lcd_dma.callback(w, lcd_dma.cb_data);
return IRQ_HANDLED;
}
int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
void *data)
{
spin_lock_irq(&lcd_dma.lock);
if (lcd_dma.reserved) {
spin_unlock_irq(&lcd_dma.lock);
printk(KERN_ERR "LCD DMA channel already reserved\n");
BUG();
return -EBUSY;
}
lcd_dma.reserved = 1;
spin_unlock_irq(&lcd_dma.lock);
lcd_dma.callback = callback;
lcd_dma.cb_data = data;
lcd_dma.active = 0;
lcd_dma.single_transfer = 0;
lcd_dma.rotate = 0;
lcd_dma.vxres = 0;
lcd_dma.mirror = 0;
lcd_dma.xscale = 0;
lcd_dma.yscale = 0;
lcd_dma.ext_ctrl = 0;
lcd_dma.src_port = 0;
return 0;
}
EXPORT_SYMBOL(omap_request_lcd_dma);
void omap_free_lcd_dma(void)
{
spin_lock(&lcd_dma.lock);
if (!lcd_dma.reserved) {
spin_unlock(&lcd_dma.lock);
printk(KERN_ERR "LCD DMA is not reserved\n");
BUG();
return;
}
if (!enable_1510_mode)
omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
OMAP1610_DMA_LCD_CCR);
lcd_dma.reserved = 0;
spin_unlock(&lcd_dma.lock);
}
EXPORT_SYMBOL(omap_free_lcd_dma);
void omap_enable_lcd_dma(void)
{
u16 w;
/*
* Set the Enable bit only if an external controller is
* connected. Otherwise the OMAP internal controller will
* start the transfer when it gets enabled.
*/
if (enable_1510_mode || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w |= 1 << 8;
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
lcd_dma.active = 1;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w |= 1 << 7;
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
EXPORT_SYMBOL(omap_enable_lcd_dma);
void omap_setup_lcd_dma(void)
{
BUG_ON(lcd_dma.active);
if (!enable_1510_mode) {
/* Set some reasonable defaults */
omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
}
set_b1_regs();
if (!enable_1510_mode) {
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
/*
* If DMA was already active set the end_prog bit to have
* the programmed register set loaded into the active
* register set.
*/
w |= 1 << 11; /* End_prog */
if (!lcd_dma.single_transfer)
w |= (3 << 8); /* Auto_init, repeat */
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
}
EXPORT_SYMBOL(omap_setup_lcd_dma);
void omap_stop_lcd_dma(void)
{
u16 w;
lcd_dma.active = 0;
if (enable_1510_mode || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w &= ~(1 << 7);
omap_writew(w, OMAP1610_DMA_LCD_CCR);
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
EXPORT_SYMBOL(omap_stop_lcd_dma);
void omap_dma_global_context_save(void)
{
omap_dma_global_context.dma_irqenable_l0 =
@ -2465,14 +2084,6 @@ static int __init omap_init_dma(void)
dma_chan_count = 16;
} else
dma_chan_count = 9;
if (cpu_is_omap16xx()) {
u16 w;
/* this would prevent OMAP sleep */
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
} else if (cpu_class_is_omap2()) {
u8 revision = dma_read(REVISION) & 0xff;
printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
@ -2483,7 +2094,6 @@ static int __init omap_init_dma(void)
return 0;
}
spin_lock_init(&lcd_dma.lock);
spin_lock_init(&dma_chan_lock);
for (ch = 0; ch < dma_chan_count; ch++) {
@ -2548,22 +2158,6 @@ static int __init omap_init_dma(void)
}
}
/* FIXME: Update LCD DMA to work on 24xx */
if (cpu_class_is_omap1()) {
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
"LCD DMA", NULL);
if (r != 0) {
int i;
printk(KERN_ERR "unable to request IRQ for LCD DMA "
"(error %d)\n", r);
for (i = 0; i < dma_chan_count; i++)
free_irq(omap1_dma_irq[i], (void *) (i + 1));
goto out_free;
}
}
return 0;
out_free:

44
arch/arm/plat-omap/i2c.c
View File

@ -80,47 +80,8 @@ static struct platform_device omap_i2c_devices[] = {
#endif
};
#if defined(CONFIG_ARCH_OMAP24XX)
static const int omap24xx_pins[][2] = {
{ M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
{ J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
};
#else
static const int omap24xx_pins[][2] = {};
#endif
#if defined(CONFIG_ARCH_OMAP34XX)
static const int omap34xx_pins[][2] = {
{ K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA},
{ AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA},
{ AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA},
};
#else
static const int omap34xx_pins[][2] = {};
#endif
#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
static void __init omap_i2c_mux_pins(int bus)
{
int scl, sda;
if (cpu_class_is_omap1()) {
scl = I2C_SCL;
sda = I2C_SDA;
} else if (cpu_is_omap24xx()) {
scl = omap24xx_pins[bus][0];
sda = omap24xx_pins[bus][1];
} else if (cpu_is_omap34xx()) {
scl = omap34xx_pins[bus][0];
sda = omap34xx_pins[bus][1];
} else {
return;
}
omap_cfg_reg(sda);
omap_cfg_reg(scl);
}
static int __init omap_i2c_nr_ports(void)
{
int ports = 0;
@ -156,7 +117,6 @@ static int __init omap_i2c_add_bus(int bus_id)
res[1].start = irq;
}
omap_i2c_mux_pins(bus_id - 1);
return platform_device_register(pdev);
}
@ -209,7 +169,7 @@ out:
subsys_initcall(omap_register_i2c_bus_cmdline);
/**
* omap_register_i2c_bus - register I2C bus with device descriptors
* omap_plat_register_i2c_bus - register I2C bus with device descriptors
* @bus_id: bus id counting from number 1
* @clkrate: clock rate of the bus in kHz
* @info: pointer into I2C device descriptor table or NULL
@ -217,7 +177,7 @@ subsys_initcall(omap_register_i2c_bus_cmdline);
*
* Returns 0 on success or an error code.
*/
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
int __init omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{

9
arch/arm/plat-omap/include/plat/board.h
View File

@ -114,15 +114,6 @@ struct omap_pwm_led_platform_data {
void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
};
/* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */
struct omap_gpio_switch_config {
char name[12];
u16 gpio;
int flags:4;
int type:4;
int key_code:24; /* Linux key code */
};
struct omap_uart_config {
/* Bit field of UARTs present; bit 0 --> UART1 */
unsigned int enabled_uarts;

14
arch/arm/plat-omap/include/plat/common.h
View File

@ -27,7 +27,7 @@
#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
#define __ARCH_ARM_MACH_OMAP_COMMON_H
#include <linux/i2c.h>
#include <plat/i2c.h>
struct sys_timer;
@ -36,18 +36,6 @@ extern void __iomem *gic_cpu_base_addr;
extern void omap_map_common_io(void);
extern struct sys_timer omap_timer;
#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len);
#else
static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
return 0;
}
#endif
/* IO bases for various OMAP processors */
struct omap_globals {

29
arch/arm/plat-omap/include/plat/cpu.h
View File

@ -176,11 +176,13 @@ IS_OMAP_CLASS(15xx, 0x15)
IS_OMAP_CLASS(16xx, 0x16)
IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
IS_OMAP_SUBCLASS(242x, 0x242)
IS_OMAP_SUBCLASS(243x, 0x243)
IS_OMAP_SUBCLASS(343x, 0x343)
IS_OMAP_SUBCLASS(363x, 0x363)
IS_OMAP_SUBCLASS(443x, 0x443)
#define cpu_is_omap7xx() 0
#define cpu_is_omap15xx() 0
@ -393,11 +395,11 @@ IS_OMAP_TYPE(3517, 0x3517)
(!omap3_has_iva()) && \
(!omap3_has_sgx()))
# define cpu_is_omap3515() (cpu_is_omap3430() && \
(omap3_has_iva()) && \
(!omap3_has_sgx()))
(!omap3_has_iva()) && \
(omap3_has_sgx()))
# define cpu_is_omap3525() (cpu_is_omap3430() && \
(omap3_has_sgx()) && \
(!omap3_has_iva()))
(!omap3_has_sgx()) && \
(omap3_has_iva()))
# define cpu_is_omap3530() (cpu_is_omap3430())
# define cpu_is_omap3505() is_omap3505()
# define cpu_is_omap3517() is_omap3517()
@ -408,8 +410,8 @@ IS_OMAP_TYPE(3517, 0x3517)
# if defined(CONFIG_ARCH_OMAP4)
# undef cpu_is_omap44xx
# undef cpu_is_omap443x
# define cpu_is_omap44xx() 1
# define cpu_is_omap443x() 1
# define cpu_is_omap44xx() is_omap44xx()
# define cpu_is_omap443x() is_omap443x()
# endif
/* Macros to detect if we have OMAP1 or OMAP2 */
@ -436,14 +438,15 @@ IS_OMAP_TYPE(3517, 0x3517)
#define OMAP3630_REV_ES1_0 0x36300034
#define OMAP35XX_CLASS 0x35000034
#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 12))
#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 12))
#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 12))
#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 12))
#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 12))
#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 12))
#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
#define OMAP443X_CLASS 0x44300034
#define OMAP443X_CLASS 0x44300044
#define OMAP4430_REV_ES1_0 0x44300044
/*
* omap_chip bits

60
arch/arm/plat-omap/include/plat/dma.h
View File

@ -401,33 +401,6 @@
/*----------------------------------------------------------------------------*/
/* Hardware registers for LCD DMA */
#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
#define OMAP1610_DMA_LCD_BASE (0xfffee300)
#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
#define OMAP1_DMA_TOUT_IRQ (1 << 0)
#define OMAP_DMA_DROP_IRQ (1 << 1)
#define OMAP_DMA_HALF_IRQ (1 << 2)
@ -441,6 +414,8 @@
#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
#define OMAP_DMA_CCR_EN (1 << 7)
#define OMAP_DMA_DATA_TYPE_S8 0x00
#define OMAP_DMA_DATA_TYPE_S16 0x01
#define OMAP_DMA_DATA_TYPE_S32 0x02
@ -503,14 +478,6 @@
#define DMA_CH_PRIO_HIGH 0x1
#define DMA_CH_PRIO_LOW 0x0 /* Def */
/* LCD DMA block numbers */
enum {
OMAP_LCD_DMA_B1_TOP,
OMAP_LCD_DMA_B1_BOTTOM,
OMAP_LCD_DMA_B2_TOP,
OMAP_LCD_DMA_B2_BOTTOM
};
enum omap_dma_burst_mode {
OMAP_DMA_DATA_BURST_DIS = 0,
OMAP_DMA_DATA_BURST_4,
@ -661,20 +628,13 @@ extern int omap_modify_dma_chain_params(int chain_id,
extern int omap_dma_chain_status(int chain_id);
#endif
/* LCD DMA functions */
extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
void *data);
extern void omap_free_lcd_dma(void);
extern void omap_setup_lcd_dma(void);
extern void omap_enable_lcd_dma(void);
extern void omap_stop_lcd_dma(void);
extern void omap_set_lcd_dma_ext_controller(int external);
extern void omap_set_lcd_dma_single_transfer(int single);
extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
int data_type);
extern void omap_set_lcd_dma_b1_rotation(int rotate);
extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
extern void omap_set_lcd_dma_b1_mirror(int mirror);
extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
#include <mach/lcd_dma.h>
#else
static inline int omap_lcd_dma_running(void)
{
return 0;
}
#endif
#endif /* __ASM_ARCH_DMA_H */

2
arch/arm/plat-omap/include/plat/gpmc.h
View File

@ -45,7 +45,7 @@
#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1)
#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2)
#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)

39
arch/arm/plat-omap/include/plat/i2c.h Normal file
View File

@ -0,0 +1,39 @@
/*
* Helper module for board specific I2C bus registration
*
* Copyright (C) 2009 Nokia Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/i2c.h>
#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len);
#else
static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
return 0;
}
#endif
int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len);

232
arch/arm/plat-omap/include/plat/mux.h
View File

@ -130,58 +130,11 @@
#define OMAP2_PULL_UP (1 << 4)
#define OMAP2_ALTELECTRICALSEL (1 << 5)
/* 34xx specific mux bit defines */
#define OMAP3_INPUT_EN (1 << 8)
#define OMAP3_OFF_EN (1 << 9)
#define OMAP3_OFFOUT_EN (1 << 10)
#define OMAP3_OFFOUT_VAL (1 << 11)
#define OMAP3_OFF_PULL_EN (1 << 12)
#define OMAP3_OFF_PULL_UP (1 << 13)
#define OMAP3_WAKEUP_EN (1 << 14)
/* 34xx mux mode options for each pin. See TRM for options */
#define OMAP34XX_MUX_MODE0 0
#define OMAP34XX_MUX_MODE1 1
#define OMAP34XX_MUX_MODE2 2
#define OMAP34XX_MUX_MODE3 3
#define OMAP34XX_MUX_MODE4 4
#define OMAP34XX_MUX_MODE5 5
#define OMAP34XX_MUX_MODE6 6
#define OMAP34XX_MUX_MODE7 7
/* 34xx active pin states */
#define OMAP34XX_PIN_OUTPUT 0
#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
| OMAP2_PULL_UP)
#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
/* 34xx off mode states */
#define OMAP34XX_PIN_OFF_NONE 0
#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
| OMAP3_OFFOUT_VAL)
#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
| OMAP3_OFF_PULL_UP)
#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
.name = desc, \
.debug = 0, \
.mux_reg = reg_offset, \
.mux_val = mux_value \
},
struct pin_config {
char *name;
const unsigned int mux_reg;
unsigned char debug;
#if defined(CONFIG_ARCH_OMAP34XX)
u16 mux_val; /* Wake-up, off mode, pull, mux mode */
#endif
#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
const unsigned char mask_offset;
const unsigned char mask;
@ -219,11 +172,17 @@ enum omap7xx_index {
AA17_7XX_USB_DM,
W16_7XX_USB_PU_EN,
W17_7XX_USB_VBUSI,
W18_7XX_USB_DMCK_OUT,
W19_7XX_USB_DCRST,
/* MMC */
MMC_7XX_CMD,
MMC_7XX_CLK,
MMC_7XX_DAT0,
/* I2C */
I2C_7XX_SCL,
I2C_7XX_SDA,
};
enum omap1xxx_index {
@ -681,181 +640,6 @@ enum omap24xx_index {
};
enum omap34xx_index {
/* 34xx I2C */
K21_34XX_I2C1_SCL,
J21_34XX_I2C1_SDA,
AF15_34XX_I2C2_SCL,
AE15_34XX_I2C2_SDA,
AF14_34XX_I2C3_SCL,
AG14_34XX_I2C3_SDA,
AD26_34XX_I2C4_SCL,
AE26_34XX_I2C4_SDA,
/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
Y8_3430_USB1HS_PHY_CLK,
Y9_3430_USB1HS_PHY_STP,
AA14_3430_USB1HS_PHY_DIR,
AA11_3430_USB1HS_PHY_NXT,
W13_3430_USB1HS_PHY_DATA0,
W12_3430_USB1HS_PHY_DATA1,
W11_3430_USB1HS_PHY_DATA2,
Y11_3430_USB1HS_PHY_DATA3,
W9_3430_USB1HS_PHY_DATA4,
Y12_3430_USB1HS_PHY_DATA5,
W8_3430_USB1HS_PHY_DATA6,
Y13_3430_USB1HS_PHY_DATA7,
/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
AA8_3430_USB2HS_PHY_CLK,
AA10_3430_USB2HS_PHY_STP,
AA9_3430_USB2HS_PHY_DIR,
AB11_3430_USB2HS_PHY_NXT,
AB10_3430_USB2HS_PHY_DATA0,
AB9_3430_USB2HS_PHY_DATA1,
W3_3430_USB2HS_PHY_DATA2,
T4_3430_USB2HS_PHY_DATA3,
T3_3430_USB2HS_PHY_DATA4,
R3_3430_USB2HS_PHY_DATA5,
R4_3430_USB2HS_PHY_DATA6,
T2_3430_USB2HS_PHY_DATA7,
/* TLL - HSUSB: 12-pin TLL Port 1*/
Y8_3430_USB1HS_TLL_CLK,
Y9_3430_USB1HS_TLL_STP,
AA14_3430_USB1HS_TLL_DIR,
AA11_3430_USB1HS_TLL_NXT,
W13_3430_USB1HS_TLL_DATA0,
W12_3430_USB1HS_TLL_DATA1,
W11_3430_USB1HS_TLL_DATA2,
Y11_3430_USB1HS_TLL_DATA3,
W9_3430_USB1HS_TLL_DATA4,
Y12_3430_USB1HS_TLL_DATA5,
W8_3430_USB1HS_TLL_DATA6,
Y13_3430_USB1HS_TLL_DATA7,
/* TLL - HSUSB: 12-pin TLL Port 2*/
AA8_3430_USB2HS_TLL_CLK,
AA10_3430_USB2HS_TLL_STP,
AA9_3430_USB2HS_TLL_DIR,
AB11_3430_USB2HS_TLL_NXT,
AB10_3430_USB2HS_TLL_DATA0,
AB9_3430_USB2HS_TLL_DATA1,
W3_3430_USB2HS_TLL_DATA2,
T4_3430_USB2HS_TLL_DATA3,
T3_3430_USB2HS_TLL_DATA4,
R3_3430_USB2HS_TLL_DATA5,
R4_3430_USB2HS_TLL_DATA6,
T2_3430_USB2HS_TLL_DATA7,
/* TLL - HSUSB: 12-pin TLL Port 3*/
AA6_3430_USB3HS_TLL_CLK,
AB3_3430_USB3HS_TLL_STP,
AA3_3430_USB3HS_TLL_DIR,
Y3_3430_USB3HS_TLL_NXT,
AA5_3430_USB3HS_TLL_DATA0,
Y4_3430_USB3HS_TLL_DATA1,
Y5_3430_USB3HS_TLL_DATA2,
W5_3430_USB3HS_TLL_DATA3,
AB12_3430_USB3HS_TLL_DATA4,
AB13_3430_USB3HS_TLL_DATA5,
AA13_3430_USB3HS_TLL_DATA6,
AA12_3430_USB3HS_TLL_DATA7,
/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
AF10_3430_USB1FS_PHY_MM1_RXDP,
AG9_3430_USB1FS_PHY_MM1_RXDM,
W13_3430_USB1FS_PHY_MM1_RXRCV,
W12_3430_USB1FS_PHY_MM1_TXSE0,
W11_3430_USB1FS_PHY_MM1_TXDAT,
Y11_3430_USB1FS_PHY_MM1_TXEN_N,
/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
AF7_3430_USB2FS_PHY_MM2_RXDP,
AH7_3430_USB2FS_PHY_MM2_RXDM,
AB10_3430_USB2FS_PHY_MM2_RXRCV,
AB9_3430_USB2FS_PHY_MM2_TXSE0,
W3_3430_USB2FS_PHY_MM2_TXDAT,
T4_3430_USB2FS_PHY_MM2_TXEN_N,
/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
AH3_3430_USB3FS_PHY_MM3_RXDP,
AE3_3430_USB3FS_PHY_MM3_RXDM,
AD1_3430_USB3FS_PHY_MM3_RXRCV,
AE1_3430_USB3FS_PHY_MM3_TXSE0,
AD2_3430_USB3FS_PHY_MM3_TXDAT,
AC1_3430_USB3FS_PHY_MM3_TXEN_N,
/* 34xx GPIO
* - normally these are bidirectional, no internal pullup/pulldown
* - "_UP" suffix (GPIO3_UP) if internal pullup is configured
* - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
* - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
*/
AF26_34XX_GPIO0,
AF22_34XX_GPIO9,
AG9_34XX_GPIO23,
AH8_34XX_GPIO29,
U8_34XX_GPIO54_OUT,
U8_34XX_GPIO54_DOWN,
L8_34XX_GPIO63,
G25_34XX_GPIO86_OUT,
AG4_34XX_GPIO134_OUT,
AF4_34XX_GPIO135_OUT,
AE4_34XX_GPIO136_OUT,
AF6_34XX_GPIO140_UP,
AE6_34XX_GPIO141,
AF5_34XX_GPIO142,
AE5_34XX_GPIO143,
H19_34XX_GPIO164_OUT,
J25_34XX_GPIO170,
/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
H16_34XX_SDRC_CKE0,
H17_34XX_SDRC_CKE1,
/* MMC1 */
N28_3430_MMC1_CLK,
M27_3430_MMC1_CMD,
N27_3430_MMC1_DAT0,
N26_3430_MMC1_DAT1,
N25_3430_MMC1_DAT2,
P28_3430_MMC1_DAT3,
P27_3430_MMC1_DAT4,
P26_3430_MMC1_DAT5,
R27_3430_MMC1_DAT6,
R25_3430_MMC1_DAT7,
/* MMC2 */
AE2_3430_MMC2_CLK,
AG5_3430_MMC2_CMD,
AH5_3430_MMC2_DAT0,
AH4_3430_MMC2_DAT1,
AG4_3430_MMC2_DAT2,
AF4_3430_MMC2_DAT3,
AE4_3430_MMC2_DAT4,
AH3_3430_MMC2_DAT5,
AF3_3430_MMC2_DAT6,
AE3_3430_MMC2_DAT7,
/* MMC3 */
AF10_3430_MMC3_CLK,
AC3_3430_MMC3_CMD,
AE11_3430_MMC3_DAT0,
AH9_3430_MMC3_DAT1,
AF13_3430_MMC3_DAT2,
AF13_3430_MMC3_DAT3,
/* SYS_NIRQ T2 INT1 */
AF26_34XX_SYS_NIRQ,
/* EHCI GPIO's for OMAP3EVM (Rev >= E) */
AH14_34XX_GPIO21,
AF9_34XX_GPIO22,
U3_34XX_GPIO61,
};
struct omap_mux_cfg {
struct pin_config *pins;
unsigned long size;
@ -865,14 +649,14 @@ struct omap_mux_cfg {
#ifdef CONFIG_OMAP_MUX
/* setup pin muxing in Linux */
extern int omap1_mux_init(void);
extern int omap2_mux_init(void);
extern int omap_mux_register(struct omap_mux_cfg *);
extern int omap_cfg_reg(unsigned long reg_cfg);
#else
/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
static inline int omap1_mux_init(void) { return 0; }
static inline int omap2_mux_init(void) { return 0; }
static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
#endif
extern int omap2_mux_init(void);
#endif

1
arch/arm/plat-omap/include/plat/serial.h
View File

@ -53,6 +53,7 @@
#ifndef __ASSEMBLER__
extern void __init omap_serial_early_init(void);
extern void omap_serial_init(void);
extern void omap_serial_init_port(int port);
extern int omap_uart_can_sleep(void);
extern void omap_uart_check_wakeup(void);
extern void omap_uart_prepare_suspend(void);

2
arch/arm/plat-omap/include/plat/smp.h
View File

@ -28,6 +28,8 @@
/* Needed for secondary core boot */
extern void omap_secondary_startup(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
extern void omap_auxcoreboot_addr(u32 cpu_addr);
/*
* We use Soft IRQ1 as the IPI

8
arch/arm/plat-omap/mux.c
View File

@ -54,8 +54,12 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
{
struct pin_config *reg;
if (cpu_is_omap44xx())
return 0;
if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
index);
WARN_ON(1);
return -EINVAL;
}
if (mux_cfg == NULL) {
printk(KERN_ERR "Pin mux table not initialized\n");

12
arch/arm/plat-omap/sram.c
View File

@ -48,8 +48,10 @@
#define OMAP3_SRAM_VA 0xfe400000
#define OMAP3_SRAM_PUB_PA 0x40208000
#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
#define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/
#define OMAP4_SRAM_VA 0xfe400000 /*0xfe4f0000*/
#define OMAP4_SRAM_PA 0x40300000
#define OMAP4_SRAM_VA 0xfe400000
#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000)
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
#define SRAM_BOOTLOADER_SZ 0x00
@ -140,6 +142,10 @@ void __init omap_detect_sram(void)
} else {
omap_sram_size = 0x8000; /* 32K */
}
} else if (cpu_is_omap44xx()) {
omap_sram_base = OMAP4_SRAM_PUB_VA;
omap_sram_start = OMAP4_SRAM_PUB_PA;
omap_sram_size = 0xa000; /* 40K */
} else {
omap_sram_base = OMAP2_SRAM_PUB_VA;
omap_sram_start = OMAP2_SRAM_PUB_PA;
@ -153,7 +159,7 @@ void __init omap_detect_sram(void)
} else if (cpu_is_omap44xx()) {
omap_sram_base = OMAP4_SRAM_VA;
omap_sram_start = OMAP4_SRAM_PA;
omap_sram_size = 0x8000; /* 32K */
omap_sram_size = 0xe000; /* 56K */
} else {
omap_sram_base = OMAP2_SRAM_VA;
omap_sram_start = OMAP2_SRAM_PA;

8
arch/arm/plat-omap/usb.c
View File

@ -137,7 +137,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
if (is_device) {
if (cpu_is_omap24xx())
omap_cfg_reg(J20_24XX_USB0_PUEN);
else
else if (cpu_is_omap7xx()) {
omap_cfg_reg(AA17_7XX_USB_DM);
omap_cfg_reg(W16_7XX_USB_PU_EN);
omap_cfg_reg(W17_7XX_USB_VBUSI);
omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
omap_cfg_reg(W19_7XX_USB_DCRST);
} else
omap_cfg_reg(W4_USB_PUEN);
}

15
drivers/net/smc91x.h
View File

@ -206,21 +206,6 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
}
}
#elif defined(CONFIG_ARCH_OMAP)
/* We can only do 16-bit reads and writes in the static memory space. */
#define SMC_CAN_USE_8BIT 0
#define SMC_CAN_USE_16BIT 1
#define SMC_CAN_USE_32BIT 0
#define SMC_IO_SHIFT 0
#define SMC_NOWAIT 1
#define SMC_inw(a, r) readw((a) + (r))
#define SMC_outw(v, a, r) writew(v, (a) + (r))
#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
#define SMC_IRQ_FLAGS (-1) /* from resource */
#elif defined(CONFIG_SH_SH4202_MICRODEV)
#define SMC_CAN_USE_8BIT 0

33
drivers/video/omap/lcdc.c
View File

@ -29,6 +29,7 @@
#include <linux/vmalloc.h>
#include <linux/clk.h>
#include <mach/lcdc.h>
#include <plat/dma.h>
#include <asm/mach-types.h>
@ -39,38 +40,6 @@
#define MODULE_NAME "lcdc"
#define OMAP_LCDC_BASE 0xfffec000
#define OMAP_LCDC_SIZE 256
#define OMAP_LCDC_IRQ INT_LCD_CTRL
#define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00)
#define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04)
#define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08)
#define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c)
#define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10)
#define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14)
#define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18)
#define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c)
#define OMAP_LCDC_STAT_DONE (1 << 0)
#define OMAP_LCDC_STAT_VSYNC (1 << 1)
#define OMAP_LCDC_STAT_SYNC_LOST (1 << 2)
#define OMAP_LCDC_STAT_ABC (1 << 3)
#define OMAP_LCDC_STAT_LINE_INT (1 << 4)
#define OMAP_LCDC_STAT_FUF (1 << 5)
#define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6)
#define OMAP_LCDC_CTRL_LCD_EN (1 << 0)
#define OMAP_LCDC_CTRL_LCD_TFT (1 << 7)
#define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
#define OMAP_LCDC_IRQ_VSYNC (1 << 2)
#define OMAP_LCDC_IRQ_DONE (1 << 3)
#define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4)
#define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5)
#define OMAP_LCDC_IRQ_LINE (1 << 6)
#define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2)
#define MAX_PALETTE_SIZE PAGE_SIZE
enum lcdc_load_mode {