forked from Minki/linux
drm/radeon: fill in set_vce_clocks for CIK asics
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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58bd2a88fa
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5ad6bf91ef
@ -8925,6 +8925,41 @@ int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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return r;
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}
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int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
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{
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int r, i;
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struct atom_clock_dividers dividers;
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u32 tmp;
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r = radeon_atom_get_clock_dividers(rdev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
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ecclk, false, ÷rs);
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if (r)
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return r;
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for (i = 0; i < 100; i++) {
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if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
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break;
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mdelay(10);
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}
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if (i == 100)
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return -ETIMEDOUT;
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tmp = RREG32_SMC(CG_ECLK_CNTL);
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tmp &= ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK);
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tmp |= dividers.post_divider;
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WREG32_SMC(CG_ECLK_CNTL, tmp);
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for (i = 0; i < 100; i++) {
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if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
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break;
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mdelay(10);
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}
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if (i == 100)
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return -ETIMEDOUT;
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return 0;
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}
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static void cik_pcie_gen3_enable(struct radeon_device *rdev)
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{
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struct pci_dev *root = rdev->pdev->bus->self;
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@ -203,6 +203,12 @@
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#define CTF_TEMP_MASK 0x0003fe00
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#define CTF_TEMP_SHIFT 9
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#define CG_ECLK_CNTL 0xC05000AC
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# define ECLK_DIVIDER_MASK 0x7f
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# define ECLK_DIR_CNTL_EN (1 << 8)
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#define CG_ECLK_STATUS 0xC05000B0
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# define ECLK_STATUS (1 << 0)
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#define CG_SPLL_FUNC_CNTL 0xC0500140
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#define SPLL_RESET (1 << 0)
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#define SPLL_PWRON (1 << 1)
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@ -2076,6 +2076,7 @@ static struct radeon_asic ci_asic = {
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.set_pcie_lanes = NULL,
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.set_clock_gating = NULL,
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.set_uvd_clocks = &cik_set_uvd_clocks,
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.set_vce_clocks = &cik_set_vce_clocks,
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.get_temperature = &ci_get_temp,
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},
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.dpm = {
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@ -2180,6 +2181,7 @@ static struct radeon_asic kv_asic = {
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.set_pcie_lanes = NULL,
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.set_clock_gating = NULL,
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.set_uvd_clocks = &cik_set_uvd_clocks,
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.set_vce_clocks = &cik_set_vce_clocks,
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.get_temperature = &kv_get_temp,
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},
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.dpm = {
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@ -717,6 +717,7 @@ u32 cik_get_xclk(struct radeon_device *rdev);
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uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
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void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
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int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
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void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
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struct radeon_fence *fence);
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bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
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