drm/amd/display: set HBR3 and TPS4 capable flags
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Zeyu Fan <Zeyu.Fan@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -1068,9 +1068,19 @@ bool dce110_link_encoder_construct(
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&bp_cap_info))
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&bp_cap_info))
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enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
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enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
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bp_cap_info.DP_HBR2_CAP;
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bp_cap_info.DP_HBR2_CAP;
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enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
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bp_cap_info.DP_HBR3_EN;
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}
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}
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/* TODO: check PPLIB maxPhyClockInKHz <= 540000, if yes,
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* IS_HBR3_CAPABLE = 0.
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*/
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/* test pattern 3 support */
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/* test pattern 3 support */
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enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
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enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
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/* test pattern 4 support */
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enc110->base.features.flags.bits.IS_TPS4_CAPABLE = true;
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enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE = false;
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enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE = false;
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/*
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/*
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