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drm/amdgpu: Resolved offchip EEPROM I/O issue

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Updated target I2C address

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
John Clements
2019-11-25 18:24:17 +08:00
committed by Alex Deucher
parent 946621691f
commit 5985ebbe78
2 changed files with 13 additions and 5 deletions
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15
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
View File

@@ -27,7 +27,8 @@
#include <linux/bits.h> #include <linux/bits.h>
#include "smu_v11_0_i2c.h" #include "smu_v11_0_i2c.h"
#define EEPROM_I2C_TARGET_ADDR 0xA0 #define EEPROM_I2C_TARGET_ADDR_ARCTURUS 0xA8
#define EEPROM_I2C_TARGET_ADDR_VEGA20 0xA0
/* /*
* The 2 macros bellow represent the actual size in bytes that * The 2 macros bellow represent the actual size in bytes that
@@ -83,7 +84,7 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
{ {
int ret = 0; int ret = 0;
struct i2c_msg msg = { struct i2c_msg msg = {
.addr = EEPROM_I2C_TARGET_ADDR, .addr = 0,
.flags = 0, .flags = 0,
.len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE, .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
.buf = buff, .buf = buff,
@@ -93,6 +94,8 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
*(uint16_t *)buff = EEPROM_HDR_START; *(uint16_t *)buff = EEPROM_HDR_START;
__encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE); __encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);
msg.addr = control->i2c_address;
ret = i2c_transfer(&control->eeprom_accessor, &msg, 1); ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
if (ret < 1) if (ret < 1)
DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret); DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret);
@@ -203,7 +206,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 }; unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
struct i2c_msg msg = { struct i2c_msg msg = {
.addr = EEPROM_I2C_TARGET_ADDR, .addr = 0,
.flags = I2C_M_RD, .flags = I2C_M_RD,
.len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE, .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
.buf = buff, .buf = buff,
@@ -213,10 +216,12 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_VEGA20: case CHIP_VEGA20:
control->i2c_address = EEPROM_I2C_TARGET_ADDR_VEGA20;
ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor); ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);
break; break;
case CHIP_ARCTURUS: case CHIP_ARCTURUS:
control->i2c_address = EEPROM_I2C_TARGET_ADDR_ARCTURUS;
ret = smu_i2c_eeprom_init(&adev->smu, &control->eeprom_accessor); ret = smu_i2c_eeprom_init(&adev->smu, &control->eeprom_accessor);
break; break;
@@ -229,6 +234,8 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
return ret; return ret;
} }
msg.addr = control->i2c_address;
/* Read/Create table header from EEPROM address 0 */ /* Read/Create table header from EEPROM address 0 */
ret = i2c_transfer(&control->eeprom_accessor, &msg, 1); ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
if (ret < 1) { if (ret < 1) {
@@ -408,7 +415,7 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
* Update bits 16,17 of EEPROM address in I2C address by setting them * Update bits 16,17 of EEPROM address in I2C address by setting them
* to bits 1,2 of Device address byte * to bits 1,2 of Device address byte
*/ */
msg->addr = EEPROM_I2C_TARGET_ADDR | msg->addr = control->i2c_address |
((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15); ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
msg->flags = write ? 0 : I2C_M_RD; msg->flags = write ? 0 : I2C_M_RD;
msg->len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE; msg->len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE;

1
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
View File

@@ -50,6 +50,7 @@ struct amdgpu_ras_eeprom_control {
struct mutex tbl_mutex; struct mutex tbl_mutex;
bool bus_locked; bool bus_locked;
uint32_t tbl_byte_sum; uint32_t tbl_byte_sum;
uint16_t i2c_address; // 8-bit represented address
}; };
/* /*