forked from Minki/linux
clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks
This adds a new driver for the USB PHY clocks in the CFGCHIP2 syscon register on TI DA8XX-type SoCs. The USB0 (USB 2.0) PHY clock is an interesting case because it calls clk_enable() in a reentrant way. The USB 2.0 PSC only has to be enabled temporarily while we are locking the PLL, which takes place during the clk_enable() callback. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
David Lechner
Stephen Boyd
parent
1e88a8d64f
commit
58e1e2d2cd
@ -343,6 +343,349 @@ static int __init of_da850_async3_init(struct device *dev, struct regmap *regmap
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return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async3_info, regmap);
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}
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/* --- USB 2.0 PHY clock --- */
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struct da8xx_usb0_clk48 {
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struct clk_hw hw;
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struct clk *fck;
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struct regmap *regmap;
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};
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#define to_da8xx_usb0_clk48(_hw) \
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container_of((_hw), struct da8xx_usb0_clk48, hw)
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static int da8xx_usb0_clk48_prepare(struct clk_hw *hw)
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{
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struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
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/* The USB 2.0 PSC clock is only needed temporarily during the USB 2.0
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* PHY clock enable, but since clk_prepare() can't be called in an
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* atomic context (i.e. in clk_enable()), we have to prepare it here.
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*/
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return clk_prepare(usb0->fck);
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}
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static void da8xx_usb0_clk48_unprepare(struct clk_hw *hw)
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{
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struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
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clk_unprepare(usb0->fck);
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}
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static int da8xx_usb0_clk48_enable(struct clk_hw *hw)
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{
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struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
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unsigned int mask, val;
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int ret;
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/* Locking the USB 2.O PLL requires that the USB 2.O PSC is enabled
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* temporaily. It can be turned back off once the PLL is locked.
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*/
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clk_enable(usb0->fck);
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/* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1
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* PHY may use the USB 2.0 PLL clock without USB 2.0 OTG being used.
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*/
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mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON;
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val = CFGCHIP2_PHY_PLLON;
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regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
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ret = regmap_read_poll_timeout(usb0->regmap, CFGCHIP(2), val,
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val & CFGCHIP2_PHYCLKGD, 0, 500000);
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clk_disable(usb0->fck);
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return ret;
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}
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static void da8xx_usb0_clk48_disable(struct clk_hw *hw)
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{
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struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
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unsigned int val;
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val = CFGCHIP2_PHYPWRDN;
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regmap_write_bits(usb0->regmap, CFGCHIP(2), val, val);
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}
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static int da8xx_usb0_clk48_is_enabled(struct clk_hw *hw)
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{
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struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
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unsigned int val;
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regmap_read(usb0->regmap, CFGCHIP(2), &val);
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return !!(val & CFGCHIP2_PHYCLKGD);
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}
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static unsigned long da8xx_usb0_clk48_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
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unsigned int mask, val;
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/* The parent clock rate must be one of the following */
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mask = CFGCHIP2_REFFREQ_MASK;
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switch (parent_rate) {
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case 12000000:
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val = CFGCHIP2_REFFREQ_12MHZ;
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break;
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case 13000000:
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val = CFGCHIP2_REFFREQ_13MHZ;
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break;
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case 19200000:
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val = CFGCHIP2_REFFREQ_19_2MHZ;
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break;
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case 20000000:
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val = CFGCHIP2_REFFREQ_20MHZ;
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break;
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case 24000000:
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val = CFGCHIP2_REFFREQ_24MHZ;
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break;
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case 26000000:
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val = CFGCHIP2_REFFREQ_26MHZ;
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break;
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case 38400000:
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val = CFGCHIP2_REFFREQ_38_4MHZ;
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break;
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case 40000000:
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val = CFGCHIP2_REFFREQ_40MHZ;
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break;
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case 48000000:
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val = CFGCHIP2_REFFREQ_48MHZ;
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break;
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default:
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return 0;
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}
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regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
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/* USB 2.0 PLL always supplies 48MHz */
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return 48000000;
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}
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static long da8xx_usb0_clk48_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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return 48000000;
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}
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static int da8xx_usb0_clk48_set_parent(struct clk_hw *hw, u8 index)
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{
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struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
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return regmap_write_bits(usb0->regmap, CFGCHIP(2),
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CFGCHIP2_USB2PHYCLKMUX,
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index ? CFGCHIP2_USB2PHYCLKMUX : 0);
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}
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static u8 da8xx_usb0_clk48_get_parent(struct clk_hw *hw)
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{
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struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
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unsigned int val;
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regmap_read(usb0->regmap, CFGCHIP(2), &val);
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return (val & CFGCHIP2_USB2PHYCLKMUX) ? 1 : 0;
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}
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static const struct clk_ops da8xx_usb0_clk48_ops = {
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.prepare = da8xx_usb0_clk48_prepare,
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.unprepare = da8xx_usb0_clk48_unprepare,
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.enable = da8xx_usb0_clk48_enable,
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.disable = da8xx_usb0_clk48_disable,
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.is_enabled = da8xx_usb0_clk48_is_enabled,
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.recalc_rate = da8xx_usb0_clk48_recalc_rate,
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.round_rate = da8xx_usb0_clk48_round_rate,
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.set_parent = da8xx_usb0_clk48_set_parent,
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.get_parent = da8xx_usb0_clk48_get_parent,
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};
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static struct da8xx_usb0_clk48 *
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da8xx_cfgchip_register_usb0_clk48(struct device *dev,
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struct regmap *regmap)
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{
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const char * const parent_names[] = { "usb_refclkin", "pll0_auxclk" };
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struct clk *fck_clk;
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struct da8xx_usb0_clk48 *usb0;
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struct clk_init_data init;
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int ret;
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fck_clk = devm_clk_get(dev, "fck");
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if (IS_ERR(fck_clk)) {
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if (PTR_ERR(fck_clk) != -EPROBE_DEFER)
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dev_err(dev, "Missing fck clock\n");
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return ERR_CAST(fck_clk);
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}
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usb0 = devm_kzalloc(dev, sizeof(*usb0), GFP_KERNEL);
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if (!usb0)
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return ERR_PTR(-ENOMEM);
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init.name = "usb0_clk48";
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init.ops = &da8xx_usb0_clk48_ops;
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init.parent_names = parent_names;
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init.num_parents = 2;
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usb0->hw.init = &init;
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usb0->fck = fck_clk;
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usb0->regmap = regmap;
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ret = devm_clk_hw_register(dev, &usb0->hw);
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if (ret < 0)
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return ERR_PTR(ret);
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return usb0;
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}
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/* --- USB 1.1 PHY clock --- */
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struct da8xx_usb1_clk48 {
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struct clk_hw hw;
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struct regmap *regmap;
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};
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#define to_da8xx_usb1_clk48(_hw) \
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container_of((_hw), struct da8xx_usb1_clk48, hw)
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static int da8xx_usb1_clk48_set_parent(struct clk_hw *hw, u8 index)
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{
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struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw);
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return regmap_write_bits(usb1->regmap, CFGCHIP(2),
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CFGCHIP2_USB1PHYCLKMUX,
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index ? CFGCHIP2_USB1PHYCLKMUX : 0);
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}
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static u8 da8xx_usb1_clk48_get_parent(struct clk_hw *hw)
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{
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struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw);
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unsigned int val;
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regmap_read(usb1->regmap, CFGCHIP(2), &val);
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return (val & CFGCHIP2_USB1PHYCLKMUX) ? 1 : 0;
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}
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static const struct clk_ops da8xx_usb1_clk48_ops = {
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.set_parent = da8xx_usb1_clk48_set_parent,
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.get_parent = da8xx_usb1_clk48_get_parent,
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};
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/**
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* da8xx_cfgchip_register_usb1_clk48 - Register a new USB 1.1 PHY clock
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* @regmap: The CFGCHIP regmap
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*/
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static struct da8xx_usb1_clk48 *
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da8xx_cfgchip_register_usb1_clk48(struct device *dev,
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struct regmap *regmap)
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{
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const char * const parent_names[] = { "usb0_clk48", "usb_refclkin" };
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struct da8xx_usb1_clk48 *usb1;
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struct clk_init_data init;
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int ret;
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usb1 = devm_kzalloc(dev, sizeof(*usb1), GFP_KERNEL);
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if (!usb1)
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return ERR_PTR(-ENOMEM);
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init.name = "usb1_clk48";
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init.ops = &da8xx_usb1_clk48_ops;
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init.parent_names = parent_names;
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init.num_parents = 2;
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usb1->hw.init = &init;
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usb1->regmap = regmap;
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ret = devm_clk_hw_register(dev, &usb1->hw);
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if (ret < 0)
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return ERR_PTR(ret);
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return usb1;
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}
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static int da8xx_cfgchip_register_usb_phy_clk(struct device *dev,
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struct regmap *regmap)
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{
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struct da8xx_usb0_clk48 *usb0;
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struct da8xx_usb1_clk48 *usb1;
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struct clk_hw *parent;
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usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap);
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if (IS_ERR(usb0))
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return PTR_ERR(usb0);
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/*
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* All existing boards use pll0_auxclk as the parent and new boards
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* should use device tree, so hard-coding the value (1) here.
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*/
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parent = clk_hw_get_parent_by_index(&usb0->hw, 1);
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if (parent)
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clk_set_parent(usb0->hw.clk, parent->clk);
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else
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dev_warn(dev, "Failed to find usb0 parent clock\n");
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usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap);
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if (IS_ERR(usb1))
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return PTR_ERR(usb1);
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/*
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* All existing boards use usb0_clk48 as the parent and new boards
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* should use device tree, so hard-coding the value (0) here.
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*/
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parent = clk_hw_get_parent_by_index(&usb1->hw, 0);
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if (parent)
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clk_set_parent(usb1->hw.clk, parent->clk);
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else
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dev_warn(dev, "Failed to find usb1 parent clock\n");
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clk_hw_register_clkdev(&usb0->hw, "usb0_clk48", "da8xx-usb-phy");
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clk_hw_register_clkdev(&usb1->hw, "usb1_clk48", "da8xx-usb-phy");
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return 0;
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}
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static int of_da8xx_usb_phy_clk_init(struct device *dev, struct regmap *regmap)
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{
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struct clk_hw_onecell_data *clk_data;
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struct da8xx_usb0_clk48 *usb0;
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struct da8xx_usb1_clk48 *usb1;
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clk_data = devm_kzalloc(dev, sizeof(*clk_data) + 2 *
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sizeof(*clk_data->hws), GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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clk_data->num = 2;
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usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap);
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if (IS_ERR(usb0)) {
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if (PTR_ERR(usb0) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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dev_warn(dev, "Failed to register usb0_clk48 (%ld)\n",
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PTR_ERR(usb0));
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clk_data->hws[0] = ERR_PTR(-ENOENT);
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} else {
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clk_data->hws[0] = &usb0->hw;
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}
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usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap);
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if (IS_ERR(usb1)) {
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if (PTR_ERR(usb0) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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dev_warn(dev, "Failed to register usb1_clk48 (%ld)\n",
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PTR_ERR(usb1));
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clk_data->hws[1] = ERR_PTR(-ENOENT);
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} else {
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clk_data->hws[1] = &usb1->hw;
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}
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
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}
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/* --- platform device --- */
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static const struct of_device_id da8xx_cfgchip_of_match[] = {
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@ -362,6 +705,10 @@ static const struct of_device_id da8xx_cfgchip_of_match[] = {
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.compatible = "ti,da850-async3-clksrc",
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.data = of_da850_async3_init,
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},
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{
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.compatible = "ti,da830-usb-phy-clocks",
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.data = of_da8xx_usb_phy_clk_init,
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},
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{ }
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};
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@ -382,6 +729,10 @@ static const struct platform_device_id da8xx_cfgchip_id_table[] = {
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.name = "da850-async3-clksrc",
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.driver_data = (kernel_ulong_t)da850_cfgchip_register_async3,
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},
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{
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.name = "da830-usb-phy-clks",
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.driver_data = (kernel_ulong_t)da8xx_cfgchip_register_usb_phy_clk,
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},
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{ }
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};
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