forked from Minki/linux
iommu/arm-smmu: Intelligent SMR allocation
Stream Match Registers are one of the more awkward parts of the SMMUv2 architecture; there are typically never enough to assign one to each stream ID in the system, and configuring them such that a single ID matches multiple entries is catastrophically bad - at best, every transaction raises a global fault; at worst, they go *somewhere*. To address the former issue, we can mask ID bits such that a single register may be used to match multiple IDs belonging to the same device or group, but doing so also heightens the risk of the latter problem (which can be nasty to debug). Tackle both problems at once by replacing the simple bitmap allocator with something much cleverer. Now that we have convenient in-memory representations of the stream mapping table, it becomes straightforward to properly validate new SMR entries against the current state, opening the door to arbitrary masking and SMR sharing. Another feature which falls out of this is that with IDs shared by separate devices being automatically accounted for, simply associating a group pointer with the S2CR offers appropriate group allocation almost for free, so hook that up in the process. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Robin Murphy
Will Deacon
parent
d3097e3930
commit
588888a739
@ -302,6 +302,8 @@ enum arm_smmu_implementation {
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};
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struct arm_smmu_s2cr {
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struct iommu_group *group;
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int count;
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enum arm_smmu_s2cr_type type;
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enum arm_smmu_s2cr_privcfg privcfg;
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u8 cbndx;
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@ -363,6 +365,7 @@ struct arm_smmu_device {
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u16 smr_mask_mask;
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struct arm_smmu_smr *smrs;
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struct arm_smmu_s2cr *s2crs;
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struct mutex stream_map_mutex;
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unsigned long va_size;
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unsigned long ipa_size;
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@ -1041,23 +1044,6 @@ static void arm_smmu_domain_free(struct iommu_domain *domain)
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kfree(smmu_domain);
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}
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static int arm_smmu_alloc_smr(struct arm_smmu_device *smmu)
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{
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int i;
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for (i = 0; i < smmu->num_mapping_groups; i++)
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if (!cmpxchg(&smmu->smrs[i].valid, false, true))
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return i;
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return INVALID_SMENDX;
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}
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static void arm_smmu_free_smr(struct arm_smmu_device *smmu, int idx)
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{
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writel_relaxed(~SMR_VALID, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_SMR(idx));
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WRITE_ONCE(smmu->smrs[idx].valid, false);
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}
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static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx)
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{
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struct arm_smmu_smr *smr = smmu->smrs + idx;
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@ -1085,49 +1071,115 @@ static void arm_smmu_write_sme(struct arm_smmu_device *smmu, int idx)
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arm_smmu_write_smr(smmu, idx);
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}
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static int arm_smmu_master_alloc_smes(struct arm_smmu_device *smmu,
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struct arm_smmu_master_cfg *cfg)
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static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask)
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{
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struct arm_smmu_smr *smrs = smmu->smrs;
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int i, idx;
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int i, free_idx = -ENOSPC;
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/* Allocate the SMRs on the SMMU */
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for_each_cfg_sme(cfg, i, idx) {
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if (idx != INVALID_SMENDX)
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return -EEXIST;
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/* Stream indexing is blissfully easy */
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if (!smrs)
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return id;
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/* ...except on stream indexing hardware, of course */
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if (!smrs) {
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cfg->smendx[i] = cfg->streamids[i];
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/* Validating SMRs is... less so */
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for (i = 0; i < smmu->num_mapping_groups; ++i) {
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if (!smrs[i].valid) {
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/*
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* Note the first free entry we come across, which
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* we'll claim in the end if nothing else matches.
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*/
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if (free_idx < 0)
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free_idx = i;
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continue;
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}
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idx = arm_smmu_alloc_smr(smmu);
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if (idx < 0) {
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dev_err(smmu->dev, "failed to allocate free SMR\n");
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goto err_free_smrs;
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}
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cfg->smendx[i] = idx;
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smrs[idx].id = cfg->streamids[i];
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smrs[idx].mask = 0; /* We don't currently share SMRs */
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/*
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* If the new entry is _entirely_ matched by an existing entry,
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* then reuse that, with the guarantee that there also cannot
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* be any subsequent conflicting entries. In normal use we'd
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* expect simply identical entries for this case, but there's
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* no harm in accommodating the generalisation.
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*/
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if ((mask & smrs[i].mask) == mask &&
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!((id ^ smrs[i].id) & ~smrs[i].mask))
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return i;
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/*
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* If the new entry has any other overlap with an existing one,
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* though, then there always exists at least one stream ID
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* which would cause a conflict, and we can't allow that risk.
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*/
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if (!((id ^ smrs[i].id) & ~(smrs[i].mask | mask)))
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return -EINVAL;
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}
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if (!smrs)
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return 0;
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return free_idx;
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}
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static bool arm_smmu_free_sme(struct arm_smmu_device *smmu, int idx)
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{
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if (--smmu->s2crs[idx].count)
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return false;
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smmu->s2crs[idx] = s2cr_init_val;
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if (smmu->smrs)
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smmu->smrs[idx].valid = false;
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return true;
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}
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static int arm_smmu_master_alloc_smes(struct device *dev)
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{
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struct arm_smmu_master_cfg *cfg = dev->archdata.iommu;
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struct arm_smmu_device *smmu = cfg->smmu;
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struct arm_smmu_smr *smrs = smmu->smrs;
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struct iommu_group *group;
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int i, idx, ret;
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mutex_lock(&smmu->stream_map_mutex);
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/* Figure out a viable stream map entry allocation */
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for_each_cfg_sme(cfg, i, idx) {
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if (idx != INVALID_SMENDX) {
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ret = -EEXIST;
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goto out_err;
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}
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ret = arm_smmu_find_sme(smmu, cfg->streamids[i], 0);
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if (ret < 0)
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goto out_err;
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idx = ret;
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if (smrs && smmu->s2crs[idx].count == 0) {
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smrs[idx].id = cfg->streamids[i];
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smrs[idx].mask = 0; /* We don't currently share SMRs */
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smrs[idx].valid = true;
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}
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smmu->s2crs[idx].count++;
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cfg->smendx[i] = (s16)idx;
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}
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group = iommu_group_get_for_dev(dev);
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if (!group)
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group = ERR_PTR(-ENOMEM);
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if (IS_ERR(group)) {
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ret = PTR_ERR(group);
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goto out_err;
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}
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iommu_group_put(group);
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/* It worked! Now, poke the actual hardware */
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for_each_cfg_sme(cfg, i, idx)
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arm_smmu_write_smr(smmu, idx);
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for_each_cfg_sme(cfg, i, idx) {
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arm_smmu_write_sme(smmu, idx);
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smmu->s2crs[idx].group = group;
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}
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mutex_unlock(&smmu->stream_map_mutex);
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return 0;
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err_free_smrs:
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out_err:
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while (i--) {
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arm_smmu_free_smr(smmu, cfg->smendx[i]);
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arm_smmu_free_sme(smmu, cfg->smendx[i]);
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cfg->smendx[i] = INVALID_SMENDX;
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}
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return -ENOSPC;
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mutex_unlock(&smmu->stream_map_mutex);
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return ret;
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}
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static void arm_smmu_master_free_smes(struct arm_smmu_master_cfg *cfg)
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@ -1135,43 +1187,23 @@ static void arm_smmu_master_free_smes(struct arm_smmu_master_cfg *cfg)
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struct arm_smmu_device *smmu = cfg->smmu;
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int i, idx;
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/*
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* We *must* clear the S2CR first, because freeing the SMR means
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* that it can be re-allocated immediately.
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*/
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mutex_lock(&smmu->stream_map_mutex);
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for_each_cfg_sme(cfg, i, idx) {
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/* An IOMMU group is torn down by the first device to be removed */
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if (idx == INVALID_SMENDX)
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return;
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smmu->s2crs[idx] = s2cr_init_val;
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arm_smmu_write_s2cr(smmu, idx);
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}
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/* Sync S2CR updates before touching anything else */
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__iowmb();
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/* Invalidate the SMRs before freeing back to the allocator */
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for_each_cfg_sme(cfg, i, idx) {
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if (smmu->smrs)
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arm_smmu_free_smr(smmu, idx);
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if (arm_smmu_free_sme(smmu, idx))
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arm_smmu_write_sme(smmu, idx);
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cfg->smendx[i] = INVALID_SMENDX;
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}
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mutex_unlock(&smmu->stream_map_mutex);
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}
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static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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struct arm_smmu_master_cfg *cfg)
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{
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int i, idx, ret = 0;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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struct arm_smmu_s2cr *s2cr = smmu->s2crs;
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enum arm_smmu_s2cr_type type = S2CR_TYPE_TRANS;
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u8 cbndx = smmu_domain->cfg.cbndx;
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if (cfg->smendx[0] == INVALID_SMENDX)
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ret = arm_smmu_master_alloc_smes(smmu, cfg);
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if (ret)
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return ret;
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int i, idx;
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/*
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* FIXME: This won't be needed once we have IOMMU-backed DMA ops
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@ -1183,9 +1215,8 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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type = S2CR_TYPE_BYPASS;
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for_each_cfg_sme(cfg, i, idx) {
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/* Devices in an IOMMU group may already be configured */
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if (type == s2cr[idx].type && cbndx == s2cr[idx].cbndx)
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break;
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continue;
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s2cr[idx].type = type;
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s2cr[idx].privcfg = S2CR_PRIVCFG_UNPRIV;
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@ -1345,7 +1376,6 @@ static bool arm_smmu_capable(enum iommu_cap cap)
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static int arm_smmu_add_device(struct device *dev)
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{
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struct arm_smmu_master_cfg *cfg;
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struct iommu_group *group;
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int i, ret;
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ret = arm_smmu_register_legacy_master(dev);
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@ -1365,13 +1395,9 @@ static int arm_smmu_add_device(struct device *dev)
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cfg->smendx[i] = INVALID_SMENDX;
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}
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group = iommu_group_get_for_dev(dev);
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if (IS_ERR(group)) {
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ret = PTR_ERR(group);
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goto out_free;
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}
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iommu_group_put(group);
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return 0;
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ret = arm_smmu_master_alloc_smes(dev);
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if (!ret)
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return ret;
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out_free:
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kfree(cfg);
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@ -1394,7 +1420,21 @@ static void arm_smmu_remove_device(struct device *dev)
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static struct iommu_group *arm_smmu_device_group(struct device *dev)
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{
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struct iommu_group *group;
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struct arm_smmu_master_cfg *cfg = dev->archdata.iommu;
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struct arm_smmu_device *smmu = cfg->smmu;
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struct iommu_group *group = NULL;
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int i, idx;
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for_each_cfg_sme(cfg, i, idx) {
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if (group && smmu->s2crs[idx].group &&
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group != smmu->s2crs[idx].group)
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return ERR_PTR(-EINVAL);
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group = smmu->s2crs[idx].group;
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}
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if (group)
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return group;
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if (dev_is_pci(dev))
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group = pci_device_group(dev);
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@ -1677,6 +1717,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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smmu->s2crs[i] = s2cr_init_val;
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smmu->num_mapping_groups = size;
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mutex_init(&smmu->stream_map_mutex);
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if (smmu->version < ARM_SMMU_V2 || !(id & ID0_PTFS_NO_AARCH32)) {
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smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_L;
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