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ARM: SoC fixes

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A collection of fixes I've been accruing over the last few weeks, none
 of them have been severe enough to warrant flushing the queue but it's
 been long enough now that it's a good idea to send them in.
 
 A handful of them are fixups for QSPI DT/bindings/compatibles, some
 smaller fixes for system DMA clock control and TMU interrupts on i.MX,
 a handful of fixes for OMAP, including a fix for DSI (display) on omap5.
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Olof Johansson:
 "A collection of fixes I've been accruing over the last few weeks, none
  of them have been severe enough to warrant flushing the queue but it's
  been long enough now that it's a good idea to send them in.

  A handful of them are fixups for QSPI DT/bindings/compatibles, some
  smaller fixes for system DMA clock control and TMU interrupts on i.MX,
  a handful of fixes for OMAP, including a fix for DSI (display) on
  omap5"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (27 commits)
  arm64: dts: ns2: Fixed QSPI compatible string
  ARM: dts: BCM5301X: Fixed QSPI compatible string
  ARM: dts: NSP: Fixed QSPI compatible string
  ARM: dts: bcm: HR2: Fixed QSPI compatible string
  dt-bindings: spi: Fix spi-bcm-qspi compatible ordering
  ARM: dts: imx6sx: fix the pad QSPI1B_SCLK mux mode for uart3
  arm64: dts: imx8mp: correct sdma1 clk setting
  arm64: dts: imx8mq: Fix TMU interrupt property
  ARM: dts: imx7d-zii-rmu2: fix rgmii phy-mode for ksz9031 phy
  ARM: dts: vfxxx: Add syscon compatible with OCOTP
  ARM: dts: imx6q-logicpd: Fix broken PWM
  arm64: dts: imx: Add missing imx8mm-beacon-kit.dtb to build
  ARM: dts: imx6q-prtwd2: Remove unneeded i2c unit name
  ARM: dts: imx6qdl-gw51xx: Remove unneeded #address-cells/#size-cells
  ARM: dts: imx7ulp: Correct gpio ranges
  ARM: dts: ls1021a: fix QuadSPI-memory reg range
  arm64: defconfig: Enable ptn5150 extcon driver
  arm64: defconfig: Enable USB gadget with configfs
  ARM: configs: Update Integrator defconfig
  ARM: dts: omap5: Fix DSI base address and clocks
  ...
This commit is contained in:
Linus Torvalds 2020-09-13 14:54:40 -07:00
commit 5712c3ed54
24 changed files with 78 additions and 68 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt
View File

@ -23,8 +23,8 @@ Required properties:
- compatible: - compatible:
Must be one of : Must be one of :
"brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs
"brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI
BRCMSTB SoCs BRCMSTB SoCs
"brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
BRCMSTB SoCs BRCMSTB SoCs
@ -36,8 +36,8 @@ Required properties:
BRCMSTB SoCs BRCMSTB SoCs
"brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
BRCMSTB SoCs BRCMSTB SoCs
"brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on Cygnus, NSP
"brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi" : NS2 SoCs
- reg: - reg:
Define the bases and ranges of the associated I/O address spaces. Define the bases and ranges of the associated I/O address spaces.
@ -86,7 +86,7 @@ BRCMSTB SoC Example:
spi@f03e3400 { spi@f03e3400 {
#address-cells = <0x1>; #address-cells = <0x1>;
#size-cells = <0x0>; #size-cells = <0x0>;
compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-qspi"; compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>; reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
reg-names = "cs_reg", "mspi", "bspi"; reg-names = "cs_reg", "mspi", "bspi";
interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>; interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
@ -149,7 +149,7 @@ BRCMSTB SoC Example:
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&upg_fixed>; clocks = <&upg_fixed>;
compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-mspi"; compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
reg = <0xf0416000 0x180>; reg = <0xf0416000 0x180>;
reg-names = "mspi"; reg-names = "mspi";
interrupts = <0x14>; interrupts = <0x14>;
@ -160,7 +160,7 @@ BRCMSTB SoC Example:
iProc SoC Example: iProc SoC Example:
qspi: spi@18027200 { qspi: spi@18027200 {
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
reg = <0x18027200 0x184>, reg = <0x18027200 0x184>,
<0x18027000 0x124>, <0x18027000 0x124>,
<0x1811c408 0x004>, <0x1811c408 0x004>,
@ -191,7 +191,7 @@ iProc SoC Example:
NS2 SoC Example: NS2 SoC Example:
qspi: spi@66470200 { qspi: spi@66470200 {
compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"; compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
reg = <0x66470200 0x184>, reg = <0x66470200 0x184>,
<0x66470000 0x124>, <0x66470000 0x124>,
<0x67017408 0x004>, <0x67017408 0x004>,

2
arch/arm/boot/dts/bcm-hr2.dtsi
View File

@ -217,7 +217,7 @@
}; };
qspi: spi@27200 { qspi: spi@27200 {
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
reg = <0x027200 0x184>, reg = <0x027200 0x184>,
<0x027000 0x124>, <0x027000 0x124>,
<0x11c408 0x004>, <0x11c408 0x004>,

2
arch/arm/boot/dts/bcm-nsp.dtsi
View File

@ -284,7 +284,7 @@
}; };
qspi: spi@27200 { qspi: spi@27200 {
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
reg = <0x027200 0x184>, reg = <0x027200 0x184>,
<0x027000 0x124>, <0x027000 0x124>,
<0x11c408 0x004>, <0x11c408 0x004>,

2
arch/arm/boot/dts/bcm5301x.dtsi
View File

@ -488,7 +488,7 @@
}; };
spi@18029200 { spi@18029200 {
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
reg = <0x18029200 0x184>, reg = <0x18029200 0x184>,
<0x18029000 0x124>, <0x18029000 0x124>,
<0x1811b408 0x004>, <0x1811b408 0x004>,

2
arch/arm/boot/dts/imx6q-logicpd.dts
View File

@ -13,7 +13,7 @@
backlight: backlight-lvds { backlight: backlight-lvds {
compatible = "pwm-backlight"; compatible = "pwm-backlight";
pwms = <&pwm3 0 20000>; pwms = <&pwm3 0 20000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>; brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>; default-brightness-level = <6>;
power-supply = <&reg_lcd>; power-supply = <&reg_lcd>;

2
arch/arm/boot/dts/imx6q-prtwd2.dts
View File

@ -30,7 +30,7 @@
}; };
/* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */ /* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */
i2c@4 { i2c {
compatible = "i2c-gpio"; compatible = "i2c-gpio";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>; pinctrl-0 = <&pinctrl_i2c4>;

2
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
View File

@ -22,8 +22,6 @@
gpio-keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user-pb { user-pb {
label = "user_pb"; label = "user_pb";

2
arch/arm/boot/dts/imx6sx-pinfunc.h
View File

@ -1026,7 +1026,7 @@
#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0 #define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0
#define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4 #define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4
#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x1 0x0
#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1 #define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1
#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2 #define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2
#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1 #define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1

2
arch/arm/boot/dts/imx7d-zii-rmu2.dts
View File

@ -58,7 +58,7 @@
<&clks IMX7D_ENET1_TIME_ROOT_CLK>; <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>; assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-handle = <&fec1_phy>; phy-handle = <&fec1_phy>;
status = "okay"; status = "okay";

8
arch/arm/boot/dts/imx7ulp.dtsi
View File

@ -394,7 +394,7 @@
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
<&pcc3 IMX7ULP_CLK_PCTLC>; <&pcc3 IMX7ULP_CLK_PCTLC>;
clock-names = "gpio", "port"; clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 0 32>; gpio-ranges = <&iomuxc1 0 0 20>;
}; };
gpio_ptd: gpio@40af0000 { gpio_ptd: gpio@40af0000 {
@ -408,7 +408,7 @@
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
<&pcc3 IMX7ULP_CLK_PCTLD>; <&pcc3 IMX7ULP_CLK_PCTLD>;
clock-names = "gpio", "port"; clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 32 32>; gpio-ranges = <&iomuxc1 0 32 12>;
}; };
gpio_pte: gpio@40b00000 { gpio_pte: gpio@40b00000 {
@ -422,7 +422,7 @@
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
<&pcc3 IMX7ULP_CLK_PCTLE>; <&pcc3 IMX7ULP_CLK_PCTLE>;
clock-names = "gpio", "port"; clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 64 32>; gpio-ranges = <&iomuxc1 0 64 16>;
}; };
gpio_ptf: gpio@40b10000 { gpio_ptf: gpio@40b10000 {
@ -436,7 +436,7 @@
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
<&pcc3 IMX7ULP_CLK_PCTLF>; <&pcc3 IMX7ULP_CLK_PCTLF>;
clock-names = "gpio", "port"; clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 96 32>; gpio-ranges = <&iomuxc1 0 96 20>;
}; };
}; };

29
arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi
View File

@ -51,6 +51,8 @@
&mcbsp2 { &mcbsp2 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
}; };
&charger { &charger {
@ -102,35 +104,18 @@
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
}; };
lcd0: display@0 { lcd0: display {
compatible = "panel-dpi"; /* This isn't the exact LCD, but the timings meet spec */
label = "28"; compatible = "logicpd,type28";
status = "okay";
/* default-on; */
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_pin>; pinctrl-0 = <&lcd_enable_pin>;
enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ backlight = <&bl>;
enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
port { port {
lcd_in: endpoint { lcd_in: endpoint {
remote-endpoint = <&dpi_out>; remote-endpoint = <&dpi_out>;
}; };
}; };
panel-timing {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <3>;
hback-porch = <2>;
hsync-len = <42>;
vback-porch = <3>;
vfront-porch = <2>;
vsync-len = <11>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <0>;
};
}; };
bl: backlight { bl: backlight {

2
arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi
View File

@ -81,6 +81,8 @@
}; };
&mcbsp2 { &mcbsp2 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
status = "okay"; status = "okay";
}; };

2
arch/arm/boot/dts/ls1021a.dtsi
View File

@ -182,7 +182,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>, reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x40000000>; <0x0 0x40000000 0x0 0x20000000>;
reg-names = "QuadSPI", "QuadSPI-memory"; reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "qspi_en", "qspi"; clock-names = "qspi_en", "qspi";

20
arch/arm/boot/dts/omap5.dtsi
View File

@ -488,11 +488,11 @@
}; };
}; };
target-module@5000 { target-module@4000 {
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x5000 0x4>, reg = <0x4000 0x4>,
<0x5010 0x4>, <0x4010 0x4>,
<0x5014 0x4>; <0x4014 0x4>;
reg-names = "rev", "sysc", "syss"; reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>, ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>, <SYSC_IDLE_NO>,
@ -504,7 +504,7 @@
ti,syss-mask = <1>; ti,syss-mask = <1>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0x5000 0x1000>; ranges = <0 0x4000 0x1000>;
dsi1: encoder@0 { dsi1: encoder@0 {
compatible = "ti,omap5-dsi"; compatible = "ti,omap5-dsi";
@ -514,8 +514,9 @@
reg-names = "proto", "phy", "pll"; reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
clock-names = "fck"; <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
}; };
}; };
@ -545,8 +546,9 @@
reg-names = "proto", "phy", "pll"; reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
clock-names = "fck"; <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
}; };
}; };

2
arch/arm/boot/dts/socfpga_arria10.dtsi
View File

@ -821,7 +821,7 @@
timer3: timer3@ffd00100 { timer3: timer3@ffd00100 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffd01000 0x100>; reg = <0xffd00100 0x100>;
clocks = <&l4_sys_free_clk>; clocks = <&l4_sys_free_clk>;
clock-names = "timer"; clock-names = "timer";
resets = <&rst L4SYSTIMER1_RESET>; resets = <&rst L4SYSTIMER1_RESET>;

2
arch/arm/boot/dts/vfxxx.dtsi
View File

@ -495,7 +495,7 @@
}; };
ocotp: ocotp@400a5000 { ocotp: ocotp@400a5000 {
compatible = "fsl,vf610-ocotp"; compatible = "fsl,vf610-ocotp", "syscon";
reg = <0x400a5000 0x1000>; reg = <0x400a5000 0x1000>;
clocks = <&clks VF610_CLK_OCOTP>; clocks = <&clks VF610_CLK_OCOTP>;
}; };

16
arch/arm/configs/integrator_defconfig
View File

@ -1,13 +1,11 @@
CONFIG_SYSVIPC=y CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14 CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_MULTI_V4T=y CONFIG_ARCH_MULTI_V4T=y
CONFIG_ARCH_MULTI_V5=y CONFIG_ARCH_MULTI_V5=y
# CONFIG_ARCH_MULTI_V7 is not set # CONFIG_ARCH_MULTI_V7 is not set
@ -15,19 +13,17 @@ CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_INTEGRATOR_IMPD1=y CONFIG_INTEGRATOR_IMPD1=y
CONFIG_ARCH_INTEGRATOR_CP=y CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_PCI=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y CONFIG_AEABI=y
# CONFIG_ATAGS is not set # CONFIG_ATAGS is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp" CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp"
CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT=y
CONFIG_CMA=y CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_NET=y CONFIG_NET=y
CONFIG_PACKET=y CONFIG_PACKET=y
CONFIG_UNIX=y CONFIG_UNIX=y
@ -37,6 +33,7 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set # CONFIG_IPV6 is not set
CONFIG_PCI=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_AFS_PARTS=y CONFIG_MTD_AFS_PARTS=y
@ -52,9 +49,12 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_E100=y CONFIG_E100=y
CONFIG_SMC91X=y CONFIG_SMC91X=y
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set # CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_SERIO_SERPORT is not set # CONFIG_SERIO_SERPORT is not set
CONFIG_DRM=y CONFIG_DRM=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_PL111=y CONFIG_DRM_PL111=y
CONFIG_FB_MODE_HELPERS=y CONFIG_FB_MODE_HELPERS=y

2
arch/arm/mach-omap2/omap-iommu.c
View File

@ -74,7 +74,7 @@ static struct powerdomain *_get_pwrdm(struct device *dev)
return pwrdm; return pwrdm;
clk = of_clk_get(dev->of_node->parent, 0); clk = of_clk_get(dev->of_node->parent, 0);
if (!clk) { if (IS_ERR(clk)) {
dev_err(dev, "no fck found\n"); dev_err(dev, "no fck found\n");
return NULL; return NULL;
} }

2
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
View File

@ -745,7 +745,7 @@
}; };
qspi: spi@66470200 { qspi: spi@66470200 {
compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"; compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
reg = <0x66470200 0x184>, reg = <0x66470200 0x184>,
<0x66470000 0x124>, <0x66470000 0x124>,
<0x67017408 0x004>, <0x67017408 0x004>,

1
arch/arm64/boot/dts/freescale/Makefile
View File

@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb

2
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -702,7 +702,7 @@
reg = <0x30bd0000 0x10000>; reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
<&clk IMX8MP_CLK_SDMA1_ROOT>; <&clk IMX8MP_CLK_AHB>;
clock-names = "ipg", "ahb"; clock-names = "ipg", "ahb";
#dma-cells = <3>; #dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";

2
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -423,7 +423,7 @@
tmu: tmu@30260000 { tmu: tmu@30260000 {
compatible = "fsl,imx8mq-tmu"; compatible = "fsl,imx8mq-tmu";
reg = <0x30260000 0x10000>; reg = <0x30260000 0x10000>;
interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
little-endian; little-endian;
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;

12
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View File

@ -13,6 +13,7 @@
*/ */
#include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
/ { / {
compatible = "xlnx,zynqmp"; compatible = "xlnx,zynqmp";
@ -558,6 +559,15 @@
}; };
}; };
psgtr: phy@fd400000 {
compatible = "xlnx,zynqmp-psgtr-v1.1";
status = "disabled";
reg = <0x0 0xfd400000 0x0 0x40000>,
<0x0 0xfd3d0000 0x0 0x1000>;
reg-names = "serdes", "siou";
#phy-cells = <4>;
};
rtc: rtc@ffa60000 { rtc: rtc@ffa60000 {
compatible = "xlnx,zynqmp-rtc"; compatible = "xlnx,zynqmp-rtc";
status = "disabled"; status = "disabled";
@ -601,7 +611,7 @@
power-domains = <&zynqmp_firmware PD_SD_1>; power-domains = <&zynqmp_firmware PD_SD_1>;
}; };
smmu: smmu@fd800000 { smmu: iommu@fd800000 {
compatible = "arm,mmu-500"; compatible = "arm,mmu-500";
reg = <0x0 0xfd800000 0x0 0x20000>; reg = <0x0 0xfd800000 0x0 0x20000>;
status = "disabled"; status = "disabled";

12
arch/arm64/configs/defconfig
View File

@ -724,6 +724,17 @@ CONFIG_USB_GADGET=y
CONFIG_USB_RENESAS_USBHS_UDC=m CONFIG_USB_RENESAS_USBHS_UDC=m
CONFIG_USB_RENESAS_USB3=m CONFIG_USB_RENESAS_USB3=m
CONFIG_USB_TEGRA_XUDC=m CONFIG_USB_TEGRA_XUDC=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_TYPEC=m CONFIG_TYPEC=m
CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPM=m
CONFIG_TYPEC_FUSB302=m CONFIG_TYPEC_FUSB302=m
@ -914,6 +925,7 @@ CONFIG_ARCH_TEGRA_194_SOC=y
CONFIG_ARCH_K3_AM6_SOC=y CONFIG_ARCH_K3_AM6_SOC=y
CONFIG_ARCH_K3_J721E_SOC=y CONFIG_ARCH_K3_J721E_SOC=y
CONFIG_TI_SCI_PM_DOMAINS=y CONFIG_TI_SCI_PM_DOMAINS=y
CONFIG_EXTCON_PTN5150=m
CONFIG_EXTCON_USB_GPIO=y CONFIG_EXTCON_USB_GPIO=y
CONFIG_EXTCON_USBC_CROS_EC=y CONFIG_EXTCON_USBC_CROS_EC=y
CONFIG_IIO=y CONFIG_IIO=y