drm/nv50: flesh out ZCULL init and match nvidia on later chipsets
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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8f7286f8e4
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562af10c67
@ -95,13 +95,41 @@ nv50_graph_init_regs__nv(struct drm_device *dev)
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static void
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static void
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nv50_graph_init_regs(struct drm_device *dev)
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nv50_graph_init_zcull(struct drm_device *dev)
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{
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int i;
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NV_DEBUG(dev, "\n");
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NV_DEBUG(dev, "\n");
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nv_wr32(dev, NV04_PGRAPH_DEBUG_3,
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switch (dev_priv->chipset & 0xf0) {
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(1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */);
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case 0x50:
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nv_wr32(dev, 0x402ca8, 0x800);
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case 0x80:
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case 0x90:
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nv_wr32(dev, 0x402ca8, 0x00000800);
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break;
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case 0xa0:
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default:
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nv_wr32(dev, 0x402cc0, 0x00000000);
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if (dev_priv->chipset == 0xa0 ||
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dev_priv->chipset == 0xaa ||
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dev_priv->chipset == 0xac) {
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nv_wr32(dev, 0x402ca8, 0x00000802);
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} else {
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nv_wr32(dev, 0x402cc0, 0x00000000);
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nv_wr32(dev, 0x402ca8, 0x00000002);
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}
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break;
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}
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/* zero out zcull regions */
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for (i = 0; i < 8; i++) {
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nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000);
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nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000);
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nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000);
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nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000);
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}
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}
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}
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static int
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static int
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@ -136,6 +164,7 @@ nv50_graph_init_ctxctl(struct drm_device *dev)
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}
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}
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kfree(cp);
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kfree(cp);
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nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
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nv_wr32(dev, 0x400320, 4);
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nv_wr32(dev, 0x400320, 4);
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
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@ -151,7 +180,7 @@ nv50_graph_init(struct drm_device *dev)
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nv50_graph_init_reset(dev);
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nv50_graph_init_reset(dev);
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nv50_graph_init_regs__nv(dev);
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nv50_graph_init_regs__nv(dev);
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nv50_graph_init_regs(dev);
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nv50_graph_init_zcull(dev);
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ret = nv50_graph_init_ctxctl(dev);
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ret = nv50_graph_init_ctxctl(dev);
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if (ret)
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if (ret)
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