forked from Minki/linux
clk: cdce925: add support for CDCE913, CDCE937, and CDCE949
The CDCE925 is a member of the CDCE(L)9xx programmable clock generator family. There are also CDCE913, CDCE937, CDCE949 which have different number of PLLs and outputs. The clk-cdce925 driver supports only CDCE925 in the family. This adds support for the CDCE913, CDCE937, CDCE949, too. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Mike Looijmans <mike.looijmans@topic.nl> Cc: Michael Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Akinobu Mita
Stephen Boyd
parent
8e18d06589
commit
5508124ccc
@ -1,15 +1,22 @@
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Binding for TO CDCE925 programmable I2C clock synthesizers.
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Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.
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Reference
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] http://www.ti.com/product/cdce925
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[2] http://www.ti.com/product/cdce913
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[3] http://www.ti.com/product/cdce925
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[4] http://www.ti.com/product/cdce937
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[5] http://www.ti.com/product/cdce949
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The driver provides clock sources for each output Y1 through Y5.
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Required properties:
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- compatible: Shall be "ti,cdce925"
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- compatible: Shall be one of the following:
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- "ti,cdce913": 1-PLL, 3 Outputs
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- "ti,cdce925": 2-PLL, 5 Outputs
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- "ti,cdce937": 3-PLL, 7 Outputs
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- "ti,cdce949": 4-PLL, 9 Outputs
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- reg: I2C device address.
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- clocks: Points to a fixed parent clock that provides the input frequency.
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- #clock-cells: From common clock bindings: Shall be 1.
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@ -18,7 +25,7 @@ Optional properties:
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- xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
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board, or to compensate for external influences.
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For both PLL1 and PLL2 an optional child node can be used to specify spread
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For all PLL1, PLL2, ... an optional child node can be used to specify spread
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spectrum clocking parameters for a board.
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- spread-spectrum: SSC mode as defined in the data sheet.
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- spread-spectrum-center: Use "centered" mode instead of "max" mode. When
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@ -95,16 +95,17 @@ config COMMON_CLK_CDCE706
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This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
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config COMMON_CLK_CDCE925
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tristate "Clock driver for TI CDCE925 devices"
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tristate "Clock driver for TI CDCE913/925/937/949 devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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---help---
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This driver supports the TI CDCE925 programmable clock synthesizer.
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The chip contains two PLLs with spread-spectrum clocking support and
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five output dividers. The driver only supports the following setup,
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and uses a fixed setting for the output muxes.
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This driver supports the TI CDCE913/925/937/949 programmable clock
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synthesizer. Each chip has different number of PLLs and outputs.
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For example, the CDCE925 contains two PLLs with spread-spectrum
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clocking support and five output dividers. The driver only supports
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the following setup, and uses a fixed setting for the output muxes.
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Y1 is derived from the input clock
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Y2 and Y3 derive from PLL1
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Y4 and Y5 derive from PLL2
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@ -1,8 +1,8 @@
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/*
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* Driver for TI Dual PLL CDCE925 clock synthesizer
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* Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer
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*
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* This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1
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* and Y4/Y5 to PLL2. PLL frequency is set on a first-come-first-serve
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* This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1,
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* Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
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* basis. Clients can directly request any frequency that the chip can
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* deliver using the standard clk framework. In addition, the device can
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* be configured and activated via the devicetree.
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@ -19,11 +19,32 @@
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#include <linux/slab.h>
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#include <linux/gcd.h>
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/* The chip has 2 PLLs which can be routed through dividers to 5 outputs.
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/* Each chip has different number of PLLs and outputs, for example:
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* The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs.
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* Model this as 2 PLL clocks which are parents to the outputs.
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*/
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#define NUMBER_OF_PLLS 2
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#define NUMBER_OF_OUTPUTS 5
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enum {
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CDCE913,
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CDCE925,
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CDCE937,
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CDCE949,
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};
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struct clk_cdce925_chip_info {
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int num_plls;
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int num_outputs;
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};
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static const struct clk_cdce925_chip_info clk_cdce925_chip_info_tbl[] = {
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[CDCE913] = { .num_plls = 1, .num_outputs = 3 },
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[CDCE925] = { .num_plls = 2, .num_outputs = 5 },
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[CDCE937] = { .num_plls = 3, .num_outputs = 7 },
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[CDCE949] = { .num_plls = 4, .num_outputs = 9 },
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};
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#define MAX_NUMBER_OF_PLLS 4
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#define MAX_NUMBER_OF_OUTPUTS 9
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#define CDCE925_REG_GLOBAL1 0x01
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#define CDCE925_REG_Y1SPIPDIVH 0x02
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@ -43,7 +64,7 @@ struct clk_cdce925_output {
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struct clk_hw hw;
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struct clk_cdce925_chip *chip;
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u8 index;
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u16 pdiv; /* 1..127 for Y2-Y5; 1..1023 for Y1 */
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u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
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};
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#define to_clk_cdce925_output(_hw) \
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container_of(_hw, struct clk_cdce925_output, hw)
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@ -60,8 +81,9 @@ struct clk_cdce925_pll {
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struct clk_cdce925_chip {
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struct regmap *regmap;
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struct i2c_client *i2c_client;
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struct clk_cdce925_pll pll[NUMBER_OF_PLLS];
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struct clk_cdce925_output clk[NUMBER_OF_OUTPUTS];
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const struct clk_cdce925_chip_info *chip_info;
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struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS];
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struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS];
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};
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/* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */
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@ -284,6 +306,18 @@ static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv)
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case 4:
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regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv);
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break;
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case 5:
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regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv);
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break;
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case 6:
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regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv);
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break;
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case 7:
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regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv);
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break;
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case 8:
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regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv);
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break;
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}
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}
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@ -302,6 +336,14 @@ static void cdce925_clk_activate(struct clk_cdce925_output *data)
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case 4:
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regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03);
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break;
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case 5:
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case 6:
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regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03);
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break;
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case 7:
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case 8:
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regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03);
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break;
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}
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}
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@ -474,15 +516,6 @@ static const struct clk_ops cdce925_clk_y1_ops = {
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.set_rate = cdce925_clk_y1_set_rate,
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};
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static struct regmap_config cdce925_regmap_config = {
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.name = "configuration0",
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.reg_bits = 8,
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.val_bits = 8,
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.cache_type = REGCACHE_RBTREE,
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.max_register = 0x2F,
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};
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#define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00
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#define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80
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@ -582,13 +615,19 @@ static int cdce925_probe(struct i2c_client *client,
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struct clk_cdce925_chip *data;
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struct device_node *node = client->dev.of_node;
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const char *parent_name;
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const char *pll_clk_name[NUMBER_OF_PLLS] = {NULL,};
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const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,};
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struct clk_init_data init;
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u32 value;
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int i;
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int err;
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struct device_node *np_output;
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char child_name[6];
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struct regmap_config config = {
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.name = "configuration0",
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.reg_bits = 8,
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.val_bits = 8,
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.cache_type = REGCACHE_RBTREE,
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};
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dev_dbg(&client->dev, "%s\n", __func__);
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data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
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@ -596,8 +635,11 @@ static int cdce925_probe(struct i2c_client *client,
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return -ENOMEM;
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data->i2c_client = client;
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data->chip_info = &clk_cdce925_chip_info_tbl[id->driver_data];
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config.max_register = CDCE925_OFFSET_PLL +
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data->chip_info->num_plls * 0x10 - 1;
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data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus,
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&client->dev, &cdce925_regmap_config);
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&client->dev, &config);
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if (IS_ERR(data->regmap)) {
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dev_err(&client->dev, "failed to allocate register map\n");
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return PTR_ERR(data->regmap);
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@ -626,7 +668,7 @@ static int cdce925_probe(struct i2c_client *client,
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init.num_parents = parent_name ? 1 : 0;
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/* Register PLL clocks */
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for (i = 0; i < NUMBER_OF_PLLS; ++i) {
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for (i = 0; i < data->chip_info->num_plls; ++i) {
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pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d",
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client->dev.of_node->name, i);
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init.name = pll_clk_name[i];
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@ -684,7 +726,7 @@ static int cdce925_probe(struct i2c_client *client,
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init.ops = &cdce925_clk_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.num_parents = 1;
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for (i = 1; i < NUMBER_OF_OUTPUTS; ++i) {
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for (i = 1; i < data->chip_info->num_outputs; ++i) {
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init.name = kasprintf(GFP_KERNEL, "%s.Y%d",
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client->dev.of_node->name, i+1);
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data->clk[i].chip = data;
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@ -702,6 +744,16 @@ static int cdce925_probe(struct i2c_client *client,
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/* Mux Y4/5 to PLL2 */
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init.parent_names = &pll_clk_name[1];
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break;
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case 5:
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case 6:
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/* Mux Y6/7 to PLL3 */
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init.parent_names = &pll_clk_name[2];
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break;
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case 7:
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case 8:
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/* Mux Y8/9 to PLL4 */
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init.parent_names = &pll_clk_name[3];
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break;
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}
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err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
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kfree(init.name); /* clock framework made a copy of the name */
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@ -720,7 +772,7 @@ static int cdce925_probe(struct i2c_client *client,
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err = 0;
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error:
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for (i = 0; i < NUMBER_OF_PLLS; ++i)
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for (i = 0; i < data->chip_info->num_plls; ++i)
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/* clock framework made a copy of the name */
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kfree(pll_clk_name[i]);
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@ -728,13 +780,19 @@ error:
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}
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static const struct i2c_device_id cdce925_id[] = {
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{ "cdce925", 0 },
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{ "cdce913", CDCE913 },
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{ "cdce925", CDCE925 },
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{ "cdce937", CDCE937 },
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{ "cdce949", CDCE949 },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, cdce925_id);
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static const struct of_device_id clk_cdce925_of_match[] = {
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{ .compatible = "ti,cdce913" },
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{ .compatible = "ti,cdce925" },
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{ .compatible = "ti,cdce937" },
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{ .compatible = "ti,cdce949" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, clk_cdce925_of_match);
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@ -750,5 +808,5 @@ static struct i2c_driver cdce925_driver = {
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module_i2c_driver(cdce925_driver);
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MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
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MODULE_DESCRIPTION("cdce925 driver");
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MODULE_DESCRIPTION("TI CDCE913/925/937/949 driver");
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MODULE_LICENSE("GPL");
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