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blackfin: adi gpio driver and pinctrl driver support

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Remove gpio driver for new gpio controller on BF54x and BF60x.
Build the bfin_gpio driver only when other BF5xx processors are selected.
Replace the prefix of some gpio and peripheral functions with adi.
add portmux platform data in machine portmux.h

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Steven Miao <realmz6@gmail.com>
This commit is contained in:
Sonic Zhang 2013-05-30 18:37:28 +08:00 committed by Steven Miao
parent 036c5df183
commit 54e4ff4d40
19 changed files with 1043 additions and 795 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/blackfin/Kconfig
View File

@ -317,6 +317,14 @@ config BF53x
depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
default y
config GPIO_ADI
def_bool y
depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
config PINCTRL
def_bool y
depends on BF54x || BF60x
config MEM_MT48LC64M4A2FB_7E
bool
depends on (BFIN533_STAMP)

157
arch/blackfin/include/asm/gpio.h
View File

@ -25,8 +25,12 @@
#ifndef __ASSEMBLY__
#ifndef CONFIG_PINCTRL
#include <linux/compiler.h>
#include <linux/gpio.h>
#include <asm/blackfin.h>
#include <asm/portmux.h>
#include <asm/irq_handler.h>
/***********************************************************
*
@ -45,7 +49,6 @@
* MODIFICATION HISTORY :
**************************************************************/
#if !BFIN_GPIO_PINT
void set_gpio_dir(unsigned, unsigned short);
void set_gpio_inen(unsigned, unsigned short);
void set_gpio_polar(unsigned, unsigned short);
@ -115,7 +118,6 @@ struct gpio_port_t {
unsigned short dummy16;
unsigned short inen;
};
#endif
#ifdef BFIN_SPECIAL_GPIO_BANKS
void bfin_special_gpio_free(unsigned gpio);
@ -127,25 +129,21 @@ void bfin_special_gpio_pm_hibernate_suspend(void);
#endif
#ifdef CONFIG_PM
int bfin_pm_standby_ctrl(unsigned ctrl);
void bfin_gpio_pm_hibernate_restore(void);
void bfin_gpio_pm_hibernate_suspend(void);
int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
int bfin_gpio_pm_standby_ctrl(unsigned ctrl);
static inline int bfin_pm_standby_setup(void)
{
return bfin_pm_standby_ctrl(1);
return bfin_gpio_pm_standby_ctrl(1);
}
static inline void bfin_pm_standby_restore(void)
{
bfin_pm_standby_ctrl(0);
bfin_gpio_pm_standby_ctrl(0);
}
void bfin_gpio_pm_hibernate_restore(void);
void bfin_gpio_pm_hibernate_suspend(void);
void bfin_pint_suspend(void);
void bfin_pint_resume(void);
# if !BFIN_GPIO_PINT
int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
struct gpio_port_s {
unsigned short data;
@ -161,7 +159,6 @@ struct gpio_port_s {
unsigned short reserved;
unsigned short mux;
};
# endif
#endif /*CONFIG_PM*/
/***********************************************************
@ -178,36 +175,29 @@ struct gpio_port_s {
*************************************************************
* MODIFICATION HISTORY :
**************************************************************/
int bfin_gpio_request(unsigned gpio, const char *label);
void bfin_gpio_free(unsigned gpio);
int bfin_gpio_irq_request(unsigned gpio, const char *label);
void bfin_gpio_irq_free(unsigned gpio);
int bfin_gpio_direction_input(unsigned gpio);
int bfin_gpio_direction_output(unsigned gpio, int value);
int bfin_gpio_get_value(unsigned gpio);
void bfin_gpio_set_value(unsigned gpio, int value);
void bfin_gpio_irq_prepare(unsigned gpio);
static inline int irq_to_gpio(unsigned irq)
{
return irq - GPIO_IRQ_BASE;
}
#endif /* CONFIG_PINCTRL */
#include <asm/irq.h>
#include <asm/errno.h>
#ifdef CONFIG_GPIOLIB
#include <asm-generic/gpio.h> /* cansleep wrappers */
static inline int gpio_get_value(unsigned int gpio)
{
if (gpio < MAX_BLACKFIN_GPIOS)
return bfin_gpio_get_value(gpio);
else
return __gpio_get_value(gpio);
return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned int gpio, int value)
{
if (gpio < MAX_BLACKFIN_GPIOS)
bfin_gpio_set_value(gpio, value);
else
__gpio_set_value(gpio, value);
__gpio_set_value(gpio, value);
}
static inline int gpio_cansleep(unsigned int gpio)
@ -219,113 +209,6 @@ static inline int gpio_to_irq(unsigned gpio)
{
return __gpio_to_irq(gpio);
}
#else /* !CONFIG_GPIOLIB */
static inline int gpio_request(unsigned gpio, const char *label)
{
return bfin_gpio_request(gpio, label);
}
static inline void gpio_free(unsigned gpio)
{
return bfin_gpio_free(gpio);
}
static inline int gpio_direction_input(unsigned gpio)
{
return bfin_gpio_direction_input(gpio);
}
static inline int gpio_direction_output(unsigned gpio, int value)
{
return bfin_gpio_direction_output(gpio, value);
}
static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
{
return -EINVAL;
}
static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
{
int err;
err = bfin_gpio_request(gpio, label);
if (err)
return err;
if (flags & GPIOF_DIR_IN)
err = bfin_gpio_direction_input(gpio);
else
err = bfin_gpio_direction_output(gpio,
(flags & GPIOF_INIT_HIGH) ? 1 : 0);
if (err)
bfin_gpio_free(gpio);
return err;
}
static inline int gpio_request_array(const struct gpio *array, size_t num)
{
int i, err;
for (i = 0; i < num; i++, array++) {
err = gpio_request_one(array->gpio, array->flags, array->label);
if (err)
goto err_free;
}
return 0;
err_free:
while (i--)
bfin_gpio_free((--array)->gpio);
return err;
}
static inline void gpio_free_array(const struct gpio *array, size_t num)
{
while (num--)
bfin_gpio_free((array++)->gpio);
}
static inline int __gpio_get_value(unsigned gpio)
{
return bfin_gpio_get_value(gpio);
}
static inline void __gpio_set_value(unsigned gpio, int value)
{
return bfin_gpio_set_value(gpio, value);
}
static inline int gpio_get_value(unsigned gpio)
{
return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
return __gpio_set_value(gpio, value);
}
static inline int gpio_to_irq(unsigned gpio)
{
if (likely(gpio < MAX_BLACKFIN_GPIOS))
return gpio + GPIO_IRQ_BASE;
return -EINVAL;
}
#include <asm-generic/gpio.h> /* cansleep wrappers */
#endif /* !CONFIG_GPIOLIB */
static inline int irq_to_gpio(unsigned irq)
{
return (irq - GPIO_IRQ_BASE);
}
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_BLACKFIN_GPIO_H__ */

3
arch/blackfin/include/asm/irq.h
View File

@ -23,8 +23,7 @@
/*
* pm save bfin pint registers
*/
struct bfin_pm_pint_save {
u32 mask_set;
struct adi_pm_pint_save {
u32 assign;
u32 edge_set;
u32 invert_set;

6
arch/blackfin/include/asm/irq_handler.h
View File

@ -12,11 +12,11 @@
#include <mach/irq.h>
/* init functions only */
extern int __init init_arch_irq(void);
extern int init_arch_irq(void);
extern void init_exception_vectors(void);
extern void __init program_IAR(void);
extern void program_IAR(void);
#ifdef init_mach_irq
extern void __init init_mach_irq(void);
extern void init_mach_irq(void);
#else
# define init_mach_irq()
#endif

17
arch/blackfin/include/asm/portmux.h
View File

@ -17,14 +17,29 @@
#define P_MAYSHARE 0x2000
#define P_DONTCARE 0x1000
#ifdef CONFIG_PINCTRL
#include <asm/irq_handler.h>
#define gpio_pint_regs bfin_pint_regs
#define adi_internal_set_wake bfin_internal_set_wake
#define peripheral_request(per, label) 0
#define peripheral_free(per)
#define peripheral_request_list(per, label) \
(pdev ? (IS_ERR(devm_pinctrl_get_select_default(&pdev->dev)) \
? -EINVAL : 0) : 0)
#define peripheral_free_list(per)
#else
int peripheral_request(unsigned short per, const char *label);
void peripheral_free(unsigned short per);
int peripheral_request_list(const unsigned short per[], const char *label);
void peripheral_free_list(const unsigned short per[]);
#endif
#include <asm/gpio.h>
#include <linux/err.h>
#include <linux/pinctrl/pinctrl.h>
#include <mach/portmux.h>
#include <linux/gpio.h>
#ifndef P_SPORT2_TFS
#define P_SPORT2_TFS P_UNDEF

3
arch/blackfin/kernel/Makefile
View File

@ -7,7 +7,7 @@ extra-y := vmlinux.lds
obj-y := \
entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
fixed_code.o reboot.o bfin_gpio.o bfin_dma.o \
fixed_code.o reboot.o bfin_dma.o \
exception.o dumpstack.o
ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
@ -16,6 +16,7 @@ else
obj-y += time.o
endif
obj-$(CONFIG_GPIO_ADI) += bfin_gpio.o
obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o
obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o

138
arch/blackfin/kernel/bfin_gpio.c
View File

@ -11,11 +11,8 @@
#include <linux/err.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
#include <asm/portmux.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <asm/irq_handler.h>
#if ANOMALY_05000311 || ANOMALY_05000323
enum {
@ -58,19 +55,6 @@ static struct gpio_port_t * const gpio_array[] = {
(struct gpio_port_t *) FIO0_FLAG_D,
(struct gpio_port_t *) FIO1_FLAG_D,
(struct gpio_port_t *) FIO2_FLAG_D,
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
(struct gpio_port_t *)PORTA_FER,
(struct gpio_port_t *)PORTB_FER,
(struct gpio_port_t *)PORTC_FER,
(struct gpio_port_t *)PORTD_FER,
(struct gpio_port_t *)PORTE_FER,
(struct gpio_port_t *)PORTF_FER,
(struct gpio_port_t *)PORTG_FER,
# if defined(CONFIG_BF54x)
(struct gpio_port_t *)PORTH_FER,
(struct gpio_port_t *)PORTI_FER,
(struct gpio_port_t *)PORTJ_FER,
# endif
#else
# error no gpio arrays defined
#endif
@ -169,12 +153,6 @@ DECLARE_RESERVED_MAP(gpio_irq, GPIO_BANK_NUM);
inline int check_gpio(unsigned gpio)
{
#if defined(CONFIG_BF54x)
if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
|| gpio == GPIO_PH14 || gpio == GPIO_PH15
|| gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
return -EINVAL;
#endif
if (gpio >= MAX_BLACKFIN_GPIOS)
return -EINVAL;
return 0;
@ -212,12 +190,6 @@ static void port_setup(unsigned gpio, unsigned short usage)
else
*port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
SSYNC();
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
if (usage == GPIO_USAGE)
gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
else
gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
SSYNC();
#endif
}
@ -306,31 +278,6 @@ static void portmux_setup(unsigned short per)
bfin_write_PORT_MUX(pmux);
}
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
inline void portmux_setup(unsigned short per)
{
u16 ident = P_IDENT(per);
u16 function = P_FUNCT2MUX(per);
u32 pmux;
pmux = gpio_array[gpio_bank(ident)]->port_mux;
pmux &= ~(0x3 << (2 * gpio_sub_n(ident)));
pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
gpio_array[gpio_bank(ident)]->port_mux = pmux;
}
inline u16 get_portmux(unsigned short per)
{
u16 ident = P_IDENT(per);
u32 pmux = gpio_array[gpio_bank(ident)]->port_mux;
return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
}
static int portmux_group_check(unsigned short per)
{
return 0;
}
#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
static int portmux_group_check(unsigned short per)
{
@ -384,7 +331,6 @@ static int portmux_group_check(unsigned short per)
}
#endif
#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
/***********************************************************
*
* FUNCTIONS: Blackfin General Purpose Ports Access Functions
@ -577,7 +523,7 @@ static const unsigned int sic_iwr_irqs[] = {
*************************************************************
* MODIFICATION HISTORY :
**************************************************************/
int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
{
unsigned long flags;
@ -596,7 +542,7 @@ int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
return 0;
}
int bfin_pm_standby_ctrl(unsigned ctrl)
int bfin_gpio_pm_standby_ctrl(unsigned ctrl)
{
u16 bank, mask, i;
@ -687,53 +633,6 @@ void bfin_gpio_pm_hibernate_restore(void)
#endif
#else /* CONFIG_BF54x || CONFIG_BF60x */
#ifdef CONFIG_PM
int bfin_pm_standby_ctrl(unsigned ctrl)
{
return 0;
}
void bfin_gpio_pm_hibernate_suspend(void)
{
int i, bank;
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
bank = gpio_bank(i);
gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer;
gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux;
gpio_bank_saved[bank].data = gpio_array[bank]->data;
gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
gpio_bank_saved[bank].dir = gpio_array[bank]->dir_set;
}
}
void bfin_gpio_pm_hibernate_restore(void)
{
int i, bank;
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
bank = gpio_bank(i);
gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
gpio_array[bank]->data_set = gpio_bank_saved[bank].data
& gpio_bank_saved[bank].dir;
gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
}
}
#endif
unsigned short get_gpio_dir(unsigned gpio)
{
return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)));
}
EXPORT_SYMBOL(get_gpio_dir);
#endif /* CONFIG_BF54x || CONFIG_BF60x */
/***********************************************************
*
@ -790,11 +689,7 @@ int peripheral_request(unsigned short per, const char *label)
* be requested and used by several drivers
*/
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
#else
if (!(per & P_MAYSHARE)) {
#endif
/*
* Allow that the identical pin function can
* be requested from the same driver twice
@ -943,12 +838,9 @@ int bfin_gpio_request(unsigned gpio, const char *label)
if (unlikely(is_reserved(gpio_irq, gpio, 1))) {
printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
" (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
}
#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
else { /* Reset POLAR setting when acquiring a gpio for the first time */
} else { /* Reset POLAR setting when acquiring a gpio for the first time */
set_gpio_polar(gpio, 0);
}
#endif
reserve(gpio, gpio);
set_label(gpio, label);
@ -1117,11 +1009,7 @@ void bfin_gpio_irq_free(unsigned gpio)
static inline void __bfin_gpio_direction_input(unsigned gpio)
{
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
#endif
gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
}
@ -1145,17 +1033,7 @@ EXPORT_SYMBOL(bfin_gpio_direction_input);
void bfin_gpio_irq_prepare(unsigned gpio)
{
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
unsigned long flags;
#endif
port_setup(gpio, GPIO_USAGE);
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
flags = hard_local_irq_save();
__bfin_gpio_direction_input(gpio);
hard_local_irq_restore(flags);
#endif
}
void bfin_gpio_set_value(unsigned gpio, int arg)
@ -1180,11 +1058,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
gpio_set_value(gpio, value);
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
#endif
AWA_DUMMY_READ(dir);
hard_local_irq_restore(flags);
@ -1195,9 +1069,6 @@ EXPORT_SYMBOL(bfin_gpio_direction_output);
int bfin_gpio_get_value(unsigned gpio)
{
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
#else
unsigned long flags;
if (unlikely(get_gpio_edge(gpio))) {
@ -1210,7 +1081,6 @@ int bfin_gpio_get_value(unsigned gpio)
return ret;
} else
return get_gpio_data(gpio);
#endif
}
EXPORT_SYMBOL(bfin_gpio_get_value);

34
arch/blackfin/mach-bf548/Kconfig
View File

@ -377,40 +377,6 @@ config IRQ_PINT3
endmenu
comment "Pin Interrupt to Port Assignment"
menu "Assignment"
config PINTx_REASSIGN
bool "Reprogram PINT Assignment"
default y
help
The interrupt assignment registers controls the pin-to-interrupt
assignment in a byte-wide manner. Each option allows you to select
a set of pins (High/Low Byte) of an specific Port being mapped
to one of the four PIN Interrupts IRQ_PINTx.
You shouldn't change any of these unless you know exactly what you're doing.
Please consult the Blackfin BF54x Processor Hardware Reference Manual.
config PINT0_ASSIGN
hex "PINT0_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT1_ASSIGN
hex "PINT1_ASSIGN"
depends on PINTx_REASSIGN
default 0x01010000
config PINT2_ASSIGN
hex "PINT2_ASSIGN"
depends on PINTx_REASSIGN
default 0x07000101
config PINT3_ASSIGN
hex "PINT3_ASSIGN"
depends on PINTx_REASSIGN
default 0x02020303
endmenu
endmenu
endif

495
arch/blackfin/mach-bf548/boards/ezkit.c
View File

@ -17,6 +17,9 @@
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/usb/musb.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_data/pinctrl-adi2.h>
#include <asm/bfin5xx_spi.h>
#include <asm/dma.h>
#include <asm/gpio.h>
@ -1058,6 +1061,411 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
};
#endif
#ifdef CONFIG_PINCTRL_ADI2
# define ADI_PINT_DEVNAME "adi-gpio-pint"
# define ADI_GPIO_DEVNAME "adi-gpio"
# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
static struct platform_device bfin_pinctrl_device = {
.name = ADI_PINCTRL_DEVNAME,
.id = 0,
};
static struct resource bfin_pint0_resources[] = {
{
.start = PINT0_MASK_SET,
.end = PINT0_LATCH + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PINT0,
.end = IRQ_PINT0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_pint0_device = {
.name = ADI_PINT_DEVNAME,
.id = 0,
.num_resources = ARRAY_SIZE(bfin_pint0_resources),
.resource = bfin_pint0_resources,
};
static struct resource bfin_pint1_resources[] = {
{
.start = PINT1_MASK_SET,
.end = PINT1_LATCH + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PINT1,
.end = IRQ_PINT1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_pint1_device = {
.name = ADI_PINT_DEVNAME,
.id = 1,
.num_resources = ARRAY_SIZE(bfin_pint1_resources),
.resource = bfin_pint1_resources,
};
static struct resource bfin_pint2_resources[] = {
{
.start = PINT2_MASK_SET,
.end = PINT2_LATCH + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PINT2,
.end = IRQ_PINT2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_pint2_device = {
.name = ADI_PINT_DEVNAME,
.id = 2,
.num_resources = ARRAY_SIZE(bfin_pint2_resources),
.resource = bfin_pint2_resources,
};
static struct resource bfin_pint3_resources[] = {
{
.start = PINT3_MASK_SET,
.end = PINT3_LATCH + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PINT3,
.end = IRQ_PINT3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_pint3_device = {
.name = ADI_PINT_DEVNAME,
.id = 3,
.num_resources = ARRAY_SIZE(bfin_pint3_resources),
.resource = bfin_pint3_resources,
};
static struct resource bfin_gpa_resources[] = {
{
.start = PORTA_FER,
.end = PORTA_MUX + 3,
.flags = IORESOURCE_MEM,
},
{ /* optional */
.start = IRQ_PA0,
.end = IRQ_PA0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
.port_gpio_base = GPIO_PA0, /* Optional */
.port_pin_base = GPIO_PA0,
.port_width = GPIO_BANKSIZE,
.pint_id = 0, /* PINT0 */
.pint_assign = true, /* PINT upper 16 bit */
.pint_map = 0, /* mapping mask in PINT */
};
static struct platform_device bfin_gpa_device = {
.name = ADI_GPIO_DEVNAME,
.id = 0,
.num_resources = ARRAY_SIZE(bfin_gpa_resources),
.resource = bfin_gpa_resources,
.dev = {
.platform_data = &bfin_gpa_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpb_resources[] = {
{
.start = PORTB_FER,
.end = PORTB_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PB0,
.end = IRQ_PB0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
.port_gpio_base = GPIO_PB0,
.port_pin_base = GPIO_PB0,
.port_width = 15,
.pint_id = 0,
.pint_assign = true,
.pint_map = 1,
};
static struct platform_device bfin_gpb_device = {
.name = ADI_GPIO_DEVNAME,
.id = 1,
.num_resources = ARRAY_SIZE(bfin_gpb_resources),
.resource = bfin_gpb_resources,
.dev = {
.platform_data = &bfin_gpb_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpc_resources[] = {
{
.start = PORTC_FER,
.end = PORTC_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PC0,
.end = IRQ_PC0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
.port_gpio_base = GPIO_PC0,
.port_pin_base = GPIO_PC0,
.port_width = 14,
.pint_id = 2,
.pint_assign = true,
.pint_map = 0,
};
static struct platform_device bfin_gpc_device = {
.name = ADI_GPIO_DEVNAME,
.id = 2,
.num_resources = ARRAY_SIZE(bfin_gpc_resources),
.resource = bfin_gpc_resources,
.dev = {
.platform_data = &bfin_gpc_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpd_resources[] = {
{
.start = PORTD_FER,
.end = PORTD_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PD0,
.end = IRQ_PD0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
.port_gpio_base = GPIO_PD0,
.port_pin_base = GPIO_PD0,
.port_width = GPIO_BANKSIZE,
.pint_id = 2,
.pint_assign = false,
.pint_map = 1,
};
static struct platform_device bfin_gpd_device = {
.name = ADI_GPIO_DEVNAME,
.id = 3,
.num_resources = ARRAY_SIZE(bfin_gpd_resources),
.resource = bfin_gpd_resources,
.dev = {
.platform_data = &bfin_gpd_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpe_resources[] = {
{
.start = PORTE_FER,
.end = PORTE_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PE0,
.end = IRQ_PE0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
.port_gpio_base = GPIO_PE0,
.port_pin_base = GPIO_PE0,
.port_width = GPIO_BANKSIZE,
.pint_id = 3,
.pint_assign = true,
.pint_map = 2,
};
static struct platform_device bfin_gpe_device = {
.name = ADI_GPIO_DEVNAME,
.id = 4,
.num_resources = ARRAY_SIZE(bfin_gpe_resources),
.resource = bfin_gpe_resources,
.dev = {
.platform_data = &bfin_gpe_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpf_resources[] = {
{
.start = PORTF_FER,
.end = PORTF_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PF0,
.end = IRQ_PF0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
.port_gpio_base = GPIO_PF0,
.port_pin_base = GPIO_PF0,
.port_width = GPIO_BANKSIZE,
.pint_id = 3,
.pint_assign = false,
.pint_map = 3,
};
static struct platform_device bfin_gpf_device = {
.name = ADI_GPIO_DEVNAME,
.id = 5,
.num_resources = ARRAY_SIZE(bfin_gpf_resources),
.resource = bfin_gpf_resources,
.dev = {
.platform_data = &bfin_gpf_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpg_resources[] = {
{
.start = PORTG_FER,
.end = PORTG_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PG0,
.end = IRQ_PG0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
.port_gpio_base = GPIO_PG0,
.port_pin_base = GPIO_PG0,
.port_width = GPIO_BANKSIZE,
.pint_id = -1,
};
static struct platform_device bfin_gpg_device = {
.name = ADI_GPIO_DEVNAME,
.id = 6,
.num_resources = ARRAY_SIZE(bfin_gpg_resources),
.resource = bfin_gpg_resources,
.dev = {
.platform_data = &bfin_gpg_pdata, /* Passed to driver */
},
};
static struct resource bfin_gph_resources[] = {
{
.start = PORTH_FER,
.end = PORTH_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PH0,
.end = IRQ_PH0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gph_pdata = {
.port_gpio_base = GPIO_PH0,
.port_pin_base = GPIO_PH0,
.port_width = 14,
.pint_id = -1,
};
static struct platform_device bfin_gph_device = {
.name = ADI_GPIO_DEVNAME,
.id = 7,
.num_resources = ARRAY_SIZE(bfin_gph_resources),
.resource = bfin_gph_resources,
.dev = {
.platform_data = &bfin_gph_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpi_resources[] = {
{
.start = PORTI_FER,
.end = PORTI_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PI0,
.end = IRQ_PI0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpi_pdata = {
.port_gpio_base = GPIO_PI0,
.port_pin_base = GPIO_PI0,
.port_width = GPIO_BANKSIZE,
.pint_id = -1,
};
static struct platform_device bfin_gpi_device = {
.name = ADI_GPIO_DEVNAME,
.id = 8,
.num_resources = ARRAY_SIZE(bfin_gpi_resources),
.resource = bfin_gpi_resources,
.dev = {
.platform_data = &bfin_gpi_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpj_resources[] = {
{
.start = PORTJ_FER,
.end = PORTJ_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PJ0,
.end = IRQ_PJ0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpj_pdata = {
.port_gpio_base = GPIO_PJ0,
.port_pin_base = GPIO_PJ0,
.port_width = 14,
.pint_id = -1,
};
static struct platform_device bfin_gpj_device = {
.name = ADI_GPIO_DEVNAME,
.id = 9,
.num_resources = ARRAY_SIZE(bfin_gpj_resources),
.resource = bfin_gpj_resources,
.dev = {
.platform_data = &bfin_gpj_pdata, /* Passed to driver */
},
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE)
@ -1066,7 +1474,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.modalias = "m25p80", /* Name of spi_driver for this device */
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0, /* Framework bus number */
.chip_select = 1, /* SPI_SSEL1*/
.chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1*/
.platform_data = &bfin_spi_flash_data,
.controller_data = &spi_flash_chip_info,
.mode = SPI_MODE_3,
@ -1078,7 +1486,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 1,
.chip_select = 4,
.chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
},
#endif
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
@ -1088,7 +1496,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 2,
.chip_select = MAX_CTRL_CS + GPIO_PE5, /* SPI_SSEL2 */
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@ -1096,7 +1504,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1 */
},
#endif
#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
@ -1106,7 +1514,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.irq = IRQ_PC5,
.max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 1,
.chip_select = 2,
.chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
.mode = SPI_MODE_3,
},
#endif
@ -1152,7 +1560,7 @@ static struct resource bfin_spi1_resource[] = {
/* SPI controller data */
static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
.num_chipselect = 4,
.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};
@ -1168,7 +1576,7 @@ static struct platform_device bf54x_spi_master0 = {
};
static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
.num_chipselect = 4,
.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
};
@ -1508,6 +1916,23 @@ static struct platform_device bfin_ac97 = {
static struct platform_device *ezkit_devices[] __initdata = {
&bfin_dpmc,
#if defined(CONFIG_PINCTRL_ADI2)
&bfin_pinctrl_device,
&bfin_pint0_device,
&bfin_pint1_device,
&bfin_pint2_device,
&bfin_pint3_device,
&bfin_gpa_device,
&bfin_gpb_device,
&bfin_gpc_device,
&bfin_gpd_device,
&bfin_gpe_device,
&bfin_gpf_device,
&bfin_gpg_device,
&bfin_gph_device,
&bfin_gpi_device,
&bfin_gpj_device,
#endif
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
&rtc_device,
@ -1644,10 +2069,66 @@ static struct platform_device *ezkit_devices[] __initdata = {
#endif
};
/* Pin control settings */
static struct pinctrl_map __initdata bfin_pinmux_map[] = {
/* per-device maps */
PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
#ifdef CONFIG_BFIN_UART1_CTSRTS
PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"),
#endif
PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.2", "pinctrl-adi2.0", NULL, "uart2"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3"),
#ifdef CONFIG_BFIN_UART3_CTSRTS
PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3_ctsrts"),
#endif
PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.2", "pinctrl-adi2.0", NULL, "uart2"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.3", "pinctrl-adi2.0", NULL, "uart3"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.0", "pinctrl-adi2.0", NULL, "spi0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.1", "pinctrl-adi2.0", NULL, "spi1"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
#endif
PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.1", "pinctrl-adi2.0", NULL, "can1"),
PIN_MAP_MUX_GROUP_DEFAULT("bf54x-lq043", "pinctrl-adi2.0", NULL, "ppi0_24b"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.0", "pinctrl-adi2.0", NULL, "sport0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.1", "pinctrl-adi2.0", NULL, "sport1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.2", "pinctrl-adi2.0", NULL, "sport2"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.3", "pinctrl-adi2.0", NULL, "sport3"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.3", "pinctrl-adi2.0", NULL, "sport3"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.3", "pinctrl-adi2.0", NULL, "sport3"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.0", "pinctrl-adi2.0", NULL, "sport0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.1", "pinctrl-adi2.0", NULL, "sport1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.2", "pinctrl-adi2.0", NULL, "sport2"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.3", "pinctrl-adi2.0", NULL, "sport3"),
PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi"),
#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi_alter"),
#endif
PIN_MAP_MUX_GROUP_DEFAULT("bf5xx-nand.0", "pinctrl-adi2.0", NULL, "nfc0"),
PIN_MAP_MUX_GROUP_DEFAULT("bf54x-keys", "pinctrl-adi2.0", NULL, "keys_4x4"),
};
static int __init ezkit_init(void)
{
printk(KERN_INFO "%s(): registering device resources\n", __func__);
/* Initialize pinmuxing */
pinctrl_register_mappings(bfin_pinmux_map,
ARRAY_SIZE(bfin_pinmux_map));
i2c_register_board_info(0, bfin_i2c_board_info0,
ARRAY_SIZE(bfin_i2c_board_info0));
#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */

8
arch/blackfin/mach-bf548/include/mach/gpio.h
View File

@ -194,14 +194,6 @@ struct gpio_port_t {
unsigned int port_mux;
};
struct gpio_port_s {
unsigned short fer;
unsigned short data;
unsigned short dir;
unsigned short inen;
unsigned int mux;
};
#endif
#include <mach-common/ports-a.h>

2
arch/blackfin/mach-bf548/include/mach/irq.h
View File

@ -433,7 +433,7 @@
#include <linux/types.h>
/*
* bfin pint registers layout
* gpio pint registers layout
*/
struct bfin_pint_regs {
u32 mask_set;

2
arch/blackfin/mach-bf548/include/mach/portmux.h
View File

@ -7,8 +7,6 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))

42
arch/blackfin/mach-bf609/Kconfig
View File

@ -9,48 +9,6 @@ source "arch/blackfin/mach-bf609/boards/Kconfig"
menu "BF609 Specific Configuration"
comment "Pin Interrupt to Port Assignment"
menu "Assignment"
config PINTx_REASSIGN
bool "Reprogram PINT Assignment"
default y
help
The interrupt assignment registers controls the pin-to-interrupt
assignment in a byte-wide manner. Each option allows you to select
a set of pins (High/Low Byte) of an specific Port being mapped
to one of the four PIN Interrupts IRQ_PINTx.
You shouldn't change any of these unless you know exactly what you're doing.
Please consult the Blackfin BF60x Processor Hardware Reference Manual.
config PINT0_ASSIGN
hex "PINT0_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT1_ASSIGN
hex "PINT1_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT2_ASSIGN
hex "PINT2_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT3_ASSIGN
hex "PINT3_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT4_ASSIGN
hex "PINT3_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
config PINT5_ASSIGN
hex "PINT3_ASSIGN"
depends on PINTx_REASSIGN
default 0x00000101
endmenu
config SEC_IRQ_PRIORITY_LEVELS
int "SEC interrupt priority levels"
default 7

471
arch/blackfin/mach-bf609/boards/ezkit.c
View File

@ -17,6 +17,9 @@
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/usb/musb.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_data/pinctrl-adi2.h>
#include <asm/bfin_spi3.h>
#include <asm/dma.h>
#include <asm/gpio.h>
@ -106,8 +109,6 @@ static struct platform_device bfin_rotary_device = {
#include <linux/stmmac.h>
#include <linux/phy.h>
static unsigned short pins[] = P_RMII0;
static struct stmmac_mdio_bus_data phy_private_data = {
.phy_mask = 1,
};
@ -674,7 +675,7 @@ static struct mtd_partition ezkit_partitions[] = {
},
};
int bf609_nor_flash_init(struct platform_device *dev)
int bf609_nor_flash_init(struct platform_device *pdev)
{
#define CONFIG_SMC_GCTL_VAL 0x00000010
const unsigned short pins[] = {
@ -1319,6 +1320,367 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
};
#endif
#ifdef CONFIG_PINCTRL_ADI2
# define ADI_PINT_DEVNAME "adi-gpio-pint"
# define ADI_GPIO_DEVNAME "adi-gpio"
# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
static struct platform_device bfin_pinctrl_device = {
.name = ADI_PINCTRL_DEVNAME,
.id = 0,
};
#ifdef CONFIG_PINCTRL_ADI2
# define ADI_PINT_DEVNAME "adi-gpio-pint"
# define ADI_GPIO_DEVNAME "adi-gpio"
# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
static struct platform_device bfin_pinctrl_device = {
.name = ADI_PINCTRL_DEVNAME,
.id = 0,
};
static struct resource bfin_pint0_resources[] = {
{
.start = PINT0_MASK_SET,
.end = PINT0_LATCH + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PINT0,
.end = IRQ_PINT0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_pint0_device = {
.name = ADI_PINT_DEVNAME,
.id = 0,
.num_resources = ARRAY_SIZE(bfin_pint0_resources),
.resource = bfin_pint0_resources,
};
static struct resource bfin_pint1_resources[] = {
{
.start = PINT1_MASK_SET,
.end = PINT1_LATCH + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PINT1,
.end = IRQ_PINT1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_pint1_device = {
.name = ADI_PINT_DEVNAME,
.id = 1,
.num_resources = ARRAY_SIZE(bfin_pint1_resources),
.resource = bfin_pint1_resources,
};
static struct resource bfin_pint2_resources[] = {
{
.start = PINT2_MASK_SET,
.end = PINT2_LATCH + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PINT2,
.end = IRQ_PINT2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_pint2_device = {
.name = ADI_PINT_DEVNAME,
.id = 2,
.num_resources = ARRAY_SIZE(bfin_pint2_resources),
.resource = bfin_pint2_resources,
};
static struct resource bfin_pint3_resources[] = {
{
.start = PINT3_MASK_SET,
.end = PINT3_LATCH + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PINT3,
.end = IRQ_PINT3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_pint3_device = {
.name = ADI_PINT_DEVNAME,
.id = 3,
.num_resources = ARRAY_SIZE(bfin_pint3_resources),
.resource = bfin_pint3_resources,
};
static struct resource bfin_pint4_resources[] = {
{
.start = PINT4_MASK_SET,
.end = PINT4_LATCH + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PINT4,
.end = IRQ_PINT4,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_pint4_device = {
.name = ADI_PINT_DEVNAME,
.id = 4,
.num_resources = ARRAY_SIZE(bfin_pint4_resources),
.resource = bfin_pint4_resources,
};
static struct resource bfin_pint5_resources[] = {
{
.start = PINT5_MASK_SET,
.end = PINT5_LATCH + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PINT5,
.end = IRQ_PINT5,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_pint5_device = {
.name = ADI_PINT_DEVNAME,
.id = 5,
.num_resources = ARRAY_SIZE(bfin_pint5_resources),
.resource = bfin_pint5_resources,
};
static struct resource bfin_gpa_resources[] = {
{
.start = PORTA_FER,
.end = PORTA_MUX + 3,
.flags = IORESOURCE_MEM,
},
{ /* optional */
.start = IRQ_PA0,
.end = IRQ_PA0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
.port_pin_base = GPIO_PA0,
.port_width = GPIO_BANKSIZE,
.pint_id = 0, /* PINT0 */
.pint_assign = true, /* PINT upper 16 bit */
.pint_map = 0, /* mapping mask in PINT */
};
static struct platform_device bfin_gpa_device = {
.name = ADI_GPIO_DEVNAME,
.id = 0,
.num_resources = ARRAY_SIZE(bfin_gpa_resources),
.resource = bfin_gpa_resources,
.dev = {
.platform_data = &bfin_gpa_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpb_resources[] = {
{
.start = PORTB_FER,
.end = PORTB_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PB0,
.end = IRQ_PB0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
.port_pin_base = GPIO_PB0,
.port_width = GPIO_BANKSIZE,
.pint_id = 0,
.pint_assign = false,
.pint_map = 1,
};
static struct platform_device bfin_gpb_device = {
.name = ADI_GPIO_DEVNAME,
.id = 1,
.num_resources = ARRAY_SIZE(bfin_gpb_resources),
.resource = bfin_gpb_resources,
.dev = {
.platform_data = &bfin_gpb_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpc_resources[] = {
{
.start = PORTC_FER,
.end = PORTC_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PC0,
.end = IRQ_PC0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
.port_pin_base = GPIO_PC0,
.port_width = GPIO_BANKSIZE,
.pint_id = 1,
.pint_assign = false,
.pint_map = 1,
};
static struct platform_device bfin_gpc_device = {
.name = ADI_GPIO_DEVNAME,
.id = 2,
.num_resources = ARRAY_SIZE(bfin_gpc_resources),
.resource = bfin_gpc_resources,
.dev = {
.platform_data = &bfin_gpc_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpd_resources[] = {
{
.start = PORTD_FER,
.end = PORTD_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PD0,
.end = IRQ_PD0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
.port_pin_base = GPIO_PD0,
.port_width = GPIO_BANKSIZE,
.pint_id = 2,
.pint_assign = false,
.pint_map = 1,
};
static struct platform_device bfin_gpd_device = {
.name = ADI_GPIO_DEVNAME,
.id = 3,
.num_resources = ARRAY_SIZE(bfin_gpd_resources),
.resource = bfin_gpd_resources,
.dev = {
.platform_data = &bfin_gpd_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpe_resources[] = {
{
.start = PORTE_FER,
.end = PORTE_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PE0,
.end = IRQ_PE0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
.port_pin_base = GPIO_PE0,
.port_width = GPIO_BANKSIZE,
.pint_id = 3,
.pint_assign = false,
.pint_map = 1,
};
static struct platform_device bfin_gpe_device = {
.name = ADI_GPIO_DEVNAME,
.id = 4,
.num_resources = ARRAY_SIZE(bfin_gpe_resources),
.resource = bfin_gpe_resources,
.dev = {
.platform_data = &bfin_gpe_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpf_resources[] = {
{
.start = PORTF_FER,
.end = PORTF_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PF0,
.end = IRQ_PF0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
.port_pin_base = GPIO_PF0,
.port_width = GPIO_BANKSIZE,
.pint_id = 4,
.pint_assign = false,
.pint_map = 1,
};
static struct platform_device bfin_gpf_device = {
.name = ADI_GPIO_DEVNAME,
.id = 5,
.num_resources = ARRAY_SIZE(bfin_gpf_resources),
.resource = bfin_gpf_resources,
.dev = {
.platform_data = &bfin_gpf_pdata, /* Passed to driver */
},
};
static struct resource bfin_gpg_resources[] = {
{
.start = PORTG_FER,
.end = PORTG_MUX + 3,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_PG0,
.end = IRQ_PG0,
.flags = IORESOURCE_IRQ,
},
};
static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
.port_pin_base = GPIO_PG0,
.port_width = GPIO_BANKSIZE,
.pint_id = 5,
.pint_assign = false,
.pint_map = 1,
};
static struct platform_device bfin_gpg_device = {
.name = ADI_GPIO_DEVNAME,
.id = 6,
.num_resources = ARRAY_SIZE(bfin_gpg_resources),
.resource = bfin_gpg_resources,
.dev = {
.platform_data = &bfin_gpg_pdata, /* Passed to driver */
},
};
#endif
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
#include <linux/input.h>
#include <linux/gpio_keys.h>
@ -1349,7 +1711,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.modalias = "m25p80", /* Name of spi_driver for this device */
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0, /* Framework bus number */
.chip_select = 1, /* SPI_SSEL1*/
.chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
.platform_data = &bfin_spi_flash_data,
.controller_data = &spi_flash_chip_info,
.mode = SPI_MODE_3,
@ -1362,7 +1724,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.irq = IRQ_PD9,
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 4,
.chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@ -1370,7 +1732,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
.controller_data = &spidev_chip_info,
},
#endif
@ -1565,6 +1927,22 @@ static struct platform_device bfin_dpmc = {
static struct platform_device *ezkit_devices[] __initdata = {
&bfin_dpmc,
#if defined(CONFIG_PINCTRL_ADI2)
&bfin_pinctrl_device,
&bfin_pint0_device,
&bfin_pint1_device,
&bfin_pint2_device,
&bfin_pint3_device,
&bfin_pint4_device,
&bfin_pint5_device,
&bfin_gpa_device,
&bfin_gpb_device,
&bfin_gpc_device,
&bfin_gpd_device,
&bfin_gpe_device,
&bfin_gpf_device,
&bfin_gpg_device,
#endif
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
&rtc_device,
@ -1681,20 +2059,91 @@ static struct platform_device *ezkit_devices[] __initdata = {
};
/* Pin control settings */
static struct pinctrl_map __initdata bfin_pinmux_map[] = {
/* per-device maps */
PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2", "pinctrl-adi2.0", NULL, "ppi2_16b"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
#if defined(CONFIG_VIDEO_MT9M114) || defined(CONFIG_VIDEO_MT9M114_MODULE)
PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_8b"),
#elif defined(CONFIG_VIDEO_VS6624) || defined(CONFIG_VIDEO_VS6624_MODULE)
PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
#else
PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_24b"),
#endif
PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
};
/* Pin control settings */
static struct pinctrl_map __initdata bfin_pinmux_map[] = {
/* per-device maps */
PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
#ifdef CONFIG_BFIN_UART0_CTSRTS
PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0_ctsrts"),
#endif
PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
#ifdef CONFIG_BFIN_UART1_CTSRTS
PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"),
#endif
PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2", "pinctrl-adi2.0", NULL, "ppi2_16b"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", NULL, "ppi2_16b"),
#if defined(CONFIG_VIDEO_MT9M114) || defined(CONFIG_VIDEO_MT9M114_MODULE)
PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_8b"),
#elif defined(CONFIG_VIDEO_VS6624) || defined(CONFIG_VIDEO_VS6624_MODULE)
PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
#else
PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_24b"),
#endif
PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
};
static int __init ezkit_init(void)
{
printk(KERN_INFO "%s(): registering device resources\n", __func__);
/* Initialize pinmuxing */
pinctrl_register_mappings(bfin_pinmux_map,
ARRAY_SIZE(bfin_pinmux_map));
i2c_register_board_info(0, bfin_i2c_board_info0,
ARRAY_SIZE(bfin_i2c_board_info0));
i2c_register_board_info(1, bfin_i2c_board_info1,
ARRAY_SIZE(bfin_i2c_board_info1));
#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
if (!peripheral_request_list(pins, "emac0"))
printk(KERN_ERR "%s(): request emac pins failed\n", __func__);
#endif
platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));

8
arch/blackfin/mach-bf609/include/mach/gpio.h
View File

@ -152,14 +152,6 @@ struct gpio_port_t {
unsigned long revid;
};
struct gpio_port_s {
unsigned short fer;
unsigned short data;
unsigned short dir;
unsigned short inen;
unsigned int mux;
};
#endif
#include <mach-common/ports-a.h>

2
arch/blackfin/mach-bf609/include/mach/irq.h
View File

@ -298,7 +298,7 @@
extern u8 sec_int_priority[];
/*
* bfin pint registers layout
* gpio pint registers layout
*/
struct bfin_pint_regs {
u32 mask_set;

6
arch/blackfin/mach-bf609/include/mach/portmux.h
View File

@ -7,8 +7,6 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
/* EMAC RMII Port Mux */
#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
@ -21,6 +19,7 @@
#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
#define P_MII0_PTPPPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
#define P_RMII0 {\
P_MII0_ETxD0, \
@ -32,6 +31,7 @@
P_MII0_TxCLK, \
P_MII0_PHYINT, \
P_MII0_CRS, \
P_MII0_PTPPPS, \
P_MII0_MDC, \
P_MII0_MDIO, 0}
@ -46,6 +46,7 @@
#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
#define P_MII1_PTPPPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
#define P_RMII1 {\
P_MII1_ETxD0, \
@ -57,6 +58,7 @@
P_MII1_TxCLK, \
P_MII1_PHYINT, \
P_MII1_CRS, \
P_MII1_PTPPPS, \
P_MII1_MDC, \
P_MII1_MDIO, 0}

421
arch/blackfin/mach-common/ints-priority.c
View File

@ -704,10 +704,9 @@ static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
__irq_set_handler_locked(irq, handle);
}
static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
extern void bfin_gpio_irq_prepare(unsigned gpio);
#ifdef CONFIG_GPIO_ADI
#if !BFIN_GPIO_PINT
static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
static void bfin_gpio_ack_irq(struct irq_data *d)
{
@ -821,15 +820,6 @@ static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
return 0;
}
#ifdef CONFIG_PM
static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
{
return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
}
#else
# define bfin_gpio_set_wake NULL
#endif
static void bfin_demux_gpio_block(unsigned int irq)
{
unsigned int gpio, mask;
@ -896,279 +886,40 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
bfin_demux_gpio_block(irq);
}
#else
#define NR_PINT_BITS 32
#define IRQ_NOT_AVAIL 0xFF
#define PINT_2_BANK(x) ((x) >> 5)
#define PINT_2_BIT(x) ((x) & 0x1F)
#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
static unsigned char irq2pint_lut[NR_PINTS];
static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
(struct bfin_pint_regs *)PINT0_MASK_SET,
(struct bfin_pint_regs *)PINT1_MASK_SET,
(struct bfin_pint_regs *)PINT2_MASK_SET,
(struct bfin_pint_regs *)PINT3_MASK_SET,
#ifdef CONFIG_BF60x
(struct bfin_pint_regs *)PINT4_MASK_SET,
(struct bfin_pint_regs *)PINT5_MASK_SET,
#endif
};
inline unsigned int get_irq_base(u32 bank, u8 bmap)
{
unsigned int irq_base;
#ifndef CONFIG_BF60x
if (bank < 2) { /*PA-PB */
irq_base = IRQ_PA0 + bmap * 16;
} else { /*PC-PJ */
irq_base = IRQ_PC0 + bmap * 16;
}
#else
irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
#endif
return irq_base;
}
/* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
void init_pint_lut(void)
{
u16 bank, bit, irq_base, bit_pos;
u32 pint_assign;
u8 bmap;
memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
pint_assign = pint[bank]->assign;
for (bit = 0; bit < NR_PINT_BITS; bit++) {
bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
irq_base = get_irq_base(bank, bmap);
irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
bit_pos = bit + bank * NR_PINT_BITS;
pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
}
}
}
static void bfin_gpio_ack_irq(struct irq_data *d)
{
u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
u32 pintbit = PINT_BIT(pint_val);
u32 bank = PINT_2_BANK(pint_val);
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
if (pint[bank]->invert_set & pintbit)
pint[bank]->invert_clear = pintbit;
else
pint[bank]->invert_set = pintbit;
}
pint[bank]->request = pintbit;
}
static void bfin_gpio_mask_ack_irq(struct irq_data *d)
{
u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
u32 pintbit = PINT_BIT(pint_val);
u32 bank = PINT_2_BANK(pint_val);
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
if (pint[bank]->invert_set & pintbit)
pint[bank]->invert_clear = pintbit;
else
pint[bank]->invert_set = pintbit;
}
pint[bank]->request = pintbit;
pint[bank]->mask_clear = pintbit;
}
static void bfin_gpio_mask_irq(struct irq_data *d)
{
u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
}
static void bfin_gpio_unmask_irq(struct irq_data *d)
{
u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
u32 pintbit = PINT_BIT(pint_val);
u32 bank = PINT_2_BANK(pint_val);
pint[bank]->mask_set = pintbit;
}
static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
{
unsigned int irq = d->irq;
u32 gpionr = irq_to_gpio(irq);
u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
if (pint_val == IRQ_NOT_AVAIL) {
printk(KERN_ERR
"GPIO IRQ %d :Not in PINT Assign table "
"Reconfigure Interrupt to Port Assignemt\n", irq);
return -ENODEV;
}
if (__test_and_set_bit(gpionr, gpio_enabled))
bfin_gpio_irq_prepare(gpionr);
bfin_gpio_unmask_irq(d);
return 0;
}
static void bfin_gpio_irq_shutdown(struct irq_data *d)
{
u32 gpionr = irq_to_gpio(d->irq);
bfin_gpio_mask_irq(d);
__clear_bit(gpionr, gpio_enabled);
bfin_gpio_irq_free(gpionr);
}
static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
{
unsigned int irq = d->irq;
int ret;
char buf[16];
u32 gpionr = irq_to_gpio(irq);
u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
u32 pintbit = PINT_BIT(pint_val);
u32 bank = PINT_2_BANK(pint_val);
if (pint_val == IRQ_NOT_AVAIL)
return -ENODEV;
if (type == IRQ_TYPE_PROBE) {
/* only probe unenabled GPIO interrupt lines */
if (test_bit(gpionr, gpio_enabled))
return 0;
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
snprintf(buf, 16, "gpio-irq%d", irq);
ret = bfin_gpio_irq_request(gpionr, buf);
if (ret)
return ret;
if (__test_and_set_bit(gpionr, gpio_enabled))
bfin_gpio_irq_prepare(gpionr);
} else {
__clear_bit(gpionr, gpio_enabled);
return 0;
}
if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
else
pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
== (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
if (gpio_get_value(gpionr))
pint[bank]->invert_set = pintbit;
else
pint[bank]->invert_clear = pintbit;
}
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
pint[bank]->edge_set = pintbit;
bfin_set_irq_handler(irq, handle_edge_irq);
} else {
pint[bank]->edge_clear = pintbit;
bfin_set_irq_handler(irq, handle_level_irq);
}
return 0;
}
#ifdef CONFIG_PM
static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS];
static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
{
u32 pint_irq;
u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
u32 bank = PINT_2_BANK(pint_val);
return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
}
switch (bank) {
case 0:
pint_irq = IRQ_PINT0;
break;
case 2:
pint_irq = IRQ_PINT2;
break;
case 3:
pint_irq = IRQ_PINT3;
break;
case 1:
pint_irq = IRQ_PINT1;
break;
#ifdef CONFIG_BF60x
case 4:
pint_irq = IRQ_PINT4;
break;
case 5:
pint_irq = IRQ_PINT5;
break;
#endif
default:
return -EINVAL;
}
#else
# define bfin_gpio_set_wake NULL
#ifndef SEC_GCTL
bfin_internal_set_wake(pint_irq, state);
#endif
return 0;
}
static struct irq_chip bfin_gpio_irqchip = {
.name = "GPIO",
.irq_ack = bfin_gpio_ack_irq,
.irq_mask = bfin_gpio_mask_irq,
.irq_mask_ack = bfin_gpio_mask_ack_irq,
.irq_unmask = bfin_gpio_unmask_irq,
.irq_disable = bfin_gpio_mask_irq,
.irq_enable = bfin_gpio_unmask_irq,
.irq_set_type = bfin_gpio_irq_type,
.irq_startup = bfin_gpio_irq_startup,
.irq_shutdown = bfin_gpio_irq_shutdown,
.irq_set_wake = bfin_gpio_set_wake,
};
void bfin_pint_suspend(void)
{
u32 bank;
#endif
for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
save_pint_reg[bank].mask_set = pint[bank]->mask_set;
save_pint_reg[bank].assign = pint[bank]->assign;
save_pint_reg[bank].edge_set = pint[bank]->edge_set;
save_pint_reg[bank].invert_set = pint[bank]->invert_set;
}
}
void bfin_pint_resume(void)
{
u32 bank;
for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
pint[bank]->mask_set = save_pint_reg[bank].mask_set;
pint[bank]->assign = save_pint_reg[bank].assign;
pint[bank]->edge_set = save_pint_reg[bank].edge_set;
pint[bank]->invert_set = save_pint_reg[bank].invert_set;
}
}
#ifdef CONFIG_PM
#ifdef SEC_GCTL
static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
static int sec_suspend(void)
{
u32 bank;
@ -1195,91 +946,9 @@ static struct syscore_ops sec_pm_syscore_ops = {
.suspend = sec_suspend,
.resume = sec_resume,
};
#endif
#else
# define bfin_gpio_set_wake NULL
#endif
void bfin_demux_gpio_irq(unsigned int inta_irq,
struct irq_desc *desc)
{
u32 bank, pint_val;
u32 request, irq;
u32 level_mask;
int umask = 0;
struct irq_chip *chip = irq_desc_get_chip(desc);
if (chip->irq_mask_ack) {
chip->irq_mask_ack(&desc->irq_data);
} else {
chip->irq_mask(&desc->irq_data);
if (chip->irq_ack)
chip->irq_ack(&desc->irq_data);
}
switch (inta_irq) {
case IRQ_PINT0:
bank = 0;
break;
case IRQ_PINT2:
bank = 2;
break;
case IRQ_PINT3:
bank = 3;
break;
case IRQ_PINT1:
bank = 1;
break;
#ifdef CONFIG_BF60x
case IRQ_PINT4:
bank = 4;
break;
case IRQ_PINT5:
bank = 5;
break;
#endif
default:
return;
}
pint_val = bank * NR_PINT_BITS;
request = pint[bank]->request;
level_mask = pint[bank]->edge_set & request;
while (request) {
if (request & 1) {
irq = pint2irq_lut[pint_val] + SYS_IRQS;
if (level_mask & PINT_BIT(pint_val)) {
umask = 1;
chip->irq_unmask(&desc->irq_data);
}
bfin_handle_irq(irq);
}
pint_val++;
request >>= 1;
}
if (!umask)
chip->irq_unmask(&desc->irq_data);
}
#endif
static struct irq_chip bfin_gpio_irqchip = {
.name = "GPIO",
.irq_ack = bfin_gpio_ack_irq,
.irq_mask = bfin_gpio_mask_irq,
.irq_mask_ack = bfin_gpio_mask_ack_irq,
.irq_unmask = bfin_gpio_unmask_irq,
.irq_disable = bfin_gpio_mask_irq,
.irq_enable = bfin_gpio_unmask_irq,
.irq_set_type = bfin_gpio_irq_type,
.irq_startup = bfin_gpio_irq_startup,
.irq_shutdown = bfin_gpio_irq_shutdown,
.irq_set_wake = bfin_gpio_set_wake,
};
void init_exception_vectors(void)
{
@ -1331,17 +1000,6 @@ int __init init_arch_irq(void)
local_irq_disable();
#if BFIN_GPIO_PINT
# ifdef CONFIG_PINTx_REASSIGN
pint[0]->assign = CONFIG_PINT0_ASSIGN;
pint[1]->assign = CONFIG_PINT1_ASSIGN;
pint[2]->assign = CONFIG_PINT2_ASSIGN;
pint[3]->assign = CONFIG_PINT3_ASSIGN;
# endif
/* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
init_pint_lut();
#endif
for (irq = 0; irq <= SYS_IRQS; irq++) {
if (irq <= IRQ_CORETMR)
irq_set_chip(irq, &bfin_core_irqchip);
@ -1349,12 +1007,8 @@ int __init init_arch_irq(void)
irq_set_chip(irq, &bfin_internal_irqchip);
switch (irq) {
#if BFIN_GPIO_PINT
case IRQ_PINT0:
case IRQ_PINT1:
case IRQ_PINT2:
case IRQ_PINT3:
#elif defined(BF537_FAMILY)
#if !BFIN_GPIO_PINT
#if defined(BF537_FAMILY)
case IRQ_PH_INTA_MAC_RX:
case IRQ_PF_INTA_PG_INTA:
#elif defined(BF533_FAMILY)
@ -1372,6 +1026,7 @@ int __init init_arch_irq(void)
#endif
irq_set_chained_handler(irq, bfin_demux_gpio_irq);
break;
#endif
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
case IRQ_MAC_ERROR:
irq_set_chained_handler(irq,
@ -1419,10 +1074,12 @@ int __init init_arch_irq(void)
handle_level_irq);
#endif
/* if configured as edge, then will be changed to do_edge_IRQ */
#ifdef CONFIG_GPIO_ADI
for (irq = GPIO_IRQ_BASE;
irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
handle_level_irq);
#endif
bfin_write_IMASK(0);
CSYNC();
ilat = bfin_read_ILAT();
@ -1525,19 +1182,6 @@ int __init init_arch_irq(void)
local_irq_disable();
#if BFIN_GPIO_PINT
# ifdef CONFIG_PINTx_REASSIGN
pint[0]->assign = CONFIG_PINT0_ASSIGN;
pint[1]->assign = CONFIG_PINT1_ASSIGN;
pint[2]->assign = CONFIG_PINT2_ASSIGN;
pint[3]->assign = CONFIG_PINT3_ASSIGN;
pint[4]->assign = CONFIG_PINT4_ASSIGN;
pint[5]->assign = CONFIG_PINT5_ASSIGN;
# endif
/* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
init_pint_lut();
#endif
for (irq = 0; irq <= SYS_IRQS; irq++) {
if (irq <= IRQ_CORETMR) {
irq_set_chip_and_handler(irq, &bfin_core_irqchip,
@ -1546,9 +1190,6 @@ int __init init_arch_irq(void)
if (irq == IRQ_CORETMR)
irq_set_handler(irq, handle_percpu_irq);
#endif
} else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
irq_set_chip(irq, &bfin_sec_irqchip);
irq_set_chained_handler(irq, bfin_demux_gpio_irq);
} else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
handle_percpu_irq);
@ -1563,10 +1204,6 @@ int __init init_arch_irq(void)
__irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
}
}
for (irq = GPIO_IRQ_BASE;
irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
handle_level_irq);
bfin_write_IMASK(0);
CSYNC();

15
arch/blackfin/mach-common/pm.c
View File

@ -27,7 +27,7 @@ struct bfin_cpu_pm_fns *bfin_cpu_pm;
void bfin_pm_suspend_standby_enter(void)
{
#ifndef CONFIG_BF60x
#if !BFIN_GPIO_PINT
bfin_pm_standby_setup();
#endif
@ -41,7 +41,7 @@ void bfin_pm_suspend_standby_enter(void)
# endif
#endif
#ifndef CONFIG_BF60x
#if !BFIN_GPIO_PINT
bfin_pm_standby_restore();
#endif
@ -128,6 +128,7 @@ static void flushinv_all_dcache(void)
if ((status & 0x3) != 0x3)
continue;
/* construct the address using the tag */
addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
@ -170,10 +171,8 @@ int bfin_pm_suspend_mem_enter(void)
return ret;
}
#ifdef CONFIG_GPIO_ADI
bfin_gpio_pm_hibernate_suspend();
#if BFIN_GPIO_PINT
bfin_pint_suspend();
#endif
#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
@ -194,11 +193,9 @@ int bfin_pm_suspend_mem_enter(void)
_enable_icplb();
_enable_dcplb();
#if BFIN_GPIO_PINT
bfin_pint_resume();
#endif
#ifdef CONFIG_GPIO_ADI
bfin_gpio_pm_hibernate_restore();
#endif
blackfin_dma_resume();
kfree(memptr);