powerpc/64s: micro-optimise __hard_irq_enable() for mtmsrd L=1 support
Book3S minimum supported ISA version now requires mtmsrd L=1. This instruction does not require bits other than RI and EE to be supplied, so __hard_irq_enable() and __hard_irq_disable() does not have to read the kernel_msr from paca. Interrupt entry code already relies on L=1 support. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -228,8 +228,8 @@ static inline bool arch_irqs_disabled(void)
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#define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory")
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#define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory")
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#else
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#define __hard_irq_enable() __mtmsrd(local_paca->kernel_msr | MSR_EE, 1)
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#define __hard_irq_disable() __mtmsrd(local_paca->kernel_msr, 1)
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#define __hard_irq_enable() __mtmsrd(MSR_EE|MSR_RI, 1)
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#define __hard_irq_disable() __mtmsrd(MSR_RI, 1)
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#endif
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#define hard_irq_disable() do { \
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