ath9k: Revamp transmit control block
Use the ath_buf instance associated with each tx frame directly and remove all redundant information in ath_tx_control. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
c51701632c
commit
528f0c6b3b
@ -114,7 +114,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
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ath9k_hw_set11n_txdesc(ah, ds,
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skb->len + FCS_LEN, /* frame length */
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ATH9K_PKT_TYPE_BEACON, /* Atheros packet type */
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avp->av_btxctl.txpower, /* txpower XXX */
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MAX_RATE_POWER, /* FIXME */
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ATH9K_TXKEYIX_INVALID, /* no encryption */
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ATH9K_KEY_TYPE_CLEAR, /* no encryption */
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flags /* no ack,
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@ -84,9 +84,6 @@ struct ath_node;
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#define TSF_TO_TU(_h,_l) \
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((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
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#define ATH9K_BH_STATUS_INTACT 0
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#define ATH9K_BH_STATUS_CHANGE 1
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#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
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static inline unsigned long get_timestamp(void)
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@ -209,6 +206,7 @@ struct ath_buf_state {
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struct ath_rc_series bfs_rcs[4]; /* rate series */
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u32 bf_type; /* BUF_* (enum buffer_type) */
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/* key type use to encrypt this frame */
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u32 bfs_keyix;
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enum ath9k_key_type bfs_keytype;
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};
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@ -219,6 +217,7 @@ struct ath_buf_state {
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#define bf_seqno bf_state.bfs_seqno
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#define bf_tidno bf_state.bfs_tidno
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#define bf_rcs bf_state.bfs_rcs
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#define bf_keyix bf_state.bfs_keyix
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#define bf_keytype bf_state.bfs_keytype
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#define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
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#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
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@ -244,7 +243,6 @@ struct ath_buf {
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struct ath_buf *bf_next; /* next subframe in the aggregate */
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struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
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void *bf_mpdu; /* enclosing frame structure */
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void *bf_node; /* pointer to the node */
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struct ath_desc *bf_desc; /* virtual addr of desc */
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dma_addr_t bf_daddr; /* physical addr of desc */
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dma_addr_t bf_buf_addr; /* physical addr of data buffer */
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@ -493,24 +491,8 @@ struct ath_atx {
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/* per-frame tx control block */
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struct ath_tx_control {
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struct ath_node *an;
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struct ath_txq *txq;
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int if_id;
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int qnum;
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u32 ht:1;
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u32 ps:1;
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u32 use_minrate:1;
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enum ath9k_pkt_type atype;
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enum ath9k_key_type keytype;
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u32 flags;
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u16 seqno;
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u16 tidno;
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u16 txpower;
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u16 frmlen;
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u32 keyix;
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int min_rate;
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int mcast_rate;
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struct ath_softc *dev;
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dma_addr_t dmacontext;
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};
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/* per frame tx status block */
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@ -551,15 +533,17 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
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int ath_tx_init(struct ath_softc *sc, int nbufs);
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int ath_tx_cleanup(struct ath_softc *sc);
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int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
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struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
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int ath_txq_update(struct ath_softc *sc, int qnum,
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struct ath9k_tx_queue_info *q);
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int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
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int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
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struct ath_tx_control *txctl);
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void ath_tx_tasklet(struct ath_softc *sc);
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u32 ath_txq_depth(struct ath_softc *sc, int qnum);
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u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
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void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
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void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
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struct ath_xmit_status *tx_status, struct ath_node *an);
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struct ath_xmit_status *tx_status);
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void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
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/**********************/
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@ -412,7 +412,7 @@ void ath_get_beaconconfig(struct ath_softc *sc,
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}
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void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
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struct ath_xmit_status *tx_status, struct ath_node *an)
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struct ath_xmit_status *tx_status)
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{
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struct ieee80211_hw *hw = sc->hw;
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struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
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@ -906,6 +906,7 @@ static int ath_attach(u16 devid,
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}
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hw->queues = 4;
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hw->sta_data_size = sizeof(struct ath_node);
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/* Register rate control */
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hw->rate_control_algorithm = "ath9k_rate_control";
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@ -1016,9 +1017,12 @@ static int ath9k_start(struct ieee80211_hw *hw)
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static int ath9k_tx(struct ieee80211_hw *hw,
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struct sk_buff *skb)
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{
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struct ath_softc *sc = hw->priv;
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int hdrlen, padsize;
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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struct ath_softc *sc = hw->priv;
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struct ath_tx_control txctl;
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int hdrlen, padsize;
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memset(&txctl, 0, sizeof(struct ath_tx_control));
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/*
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* As a temporary workaround, assign seq# here; this will likely need
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@ -1043,17 +1047,24 @@ static int ath9k_tx(struct ieee80211_hw *hw,
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memmove(skb->data, skb->data + padsize, hdrlen);
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}
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/* Check if a tx queue is available */
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txctl.txq = ath_test_get_txq(sc, skb);
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if (!txctl.txq)
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goto exit;
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DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
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__func__,
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skb);
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if (ath_tx_start(sc, skb) != 0) {
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if (ath_tx_start(sc, skb, &txctl) != 0) {
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DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
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dev_kfree_skb_any(skb);
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/* FIXME: Check for proper return value from ATH_DEV */
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return 0;
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goto exit;
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}
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return 0;
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exit:
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dev_kfree_skb_any(skb);
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return 0;
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}
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@ -136,15 +136,17 @@ static int ath_aggr_query(struct ath_softc *sc,
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return 0;
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}
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static enum ath9k_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
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/* Calculate Atheros packet type from IEEE80211 packet header */
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static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
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{
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struct ieee80211_hdr *hdr;
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enum ath9k_pkt_type htype;
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__le16 fc;
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hdr = (struct ieee80211_hdr *)skb->data;
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fc = hdr->frame_control;
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/* Calculate Atheros packet type from IEEE80211 packet header */
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if (ieee80211_is_beacon(fc))
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htype = ATH9K_PKT_TYPE_BEACON;
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else if (ieee80211_is_probe_resp(fc))
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@ -159,214 +161,176 @@ static enum ath9k_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
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return htype;
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}
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static void fill_min_rates(struct sk_buff *skb, struct ath_tx_control *txctl)
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static bool check_min_rate(struct sk_buff *skb)
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{
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struct ieee80211_hdr *hdr;
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struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
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struct ath_tx_info_priv *tx_info_priv;
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bool use_minrate = false;
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__le16 fc;
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hdr = (struct ieee80211_hdr *)skb->data;
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fc = hdr->frame_control;
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/* XXX: HACK! */
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tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif;
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if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) {
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txctl->use_minrate = 1;
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txctl->min_rate = tx_info_priv->min_rate;
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use_minrate = true;
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} else if (ieee80211_is_data(fc)) {
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if (ieee80211_is_nullfunc(fc) ||
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/* Port Access Entity (IEEE 802.1X) */
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(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
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txctl->use_minrate = 1;
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txctl->min_rate = tx_info_priv->min_rate;
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/* Port Access Entity (IEEE 802.1X) */
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(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
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use_minrate = true;
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}
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if (is_multicast_ether_addr(hdr->addr1))
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txctl->mcast_rate = tx_info_priv->min_rate;
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}
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return use_minrate;
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}
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/* This function will setup additional txctl information, mostly rate stuff */
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/* FIXME: seqno, ps */
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static int ath_tx_prepare(struct ath_softc *sc,
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struct sk_buff *skb,
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struct ath_tx_control *txctl)
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static int get_hw_crypto_keytype(struct sk_buff *skb)
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{
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struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
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if (tx_info->control.hw_key) {
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if (tx_info->control.hw_key->alg == ALG_WEP)
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return ATH9K_KEY_TYPE_WEP;
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else if (tx_info->control.hw_key->alg == ALG_TKIP)
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return ATH9K_KEY_TYPE_TKIP;
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else if (tx_info->control.hw_key->alg == ALG_CCMP)
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return ATH9K_KEY_TYPE_AES;
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}
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return ATH9K_KEY_TYPE_CLEAR;
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}
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static void setup_rate_retries(struct ath_softc *sc, struct sk_buff *skb)
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{
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struct ieee80211_hw *hw = sc->hw;
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struct ieee80211_hdr *hdr;
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struct ath_rc_series *rcs;
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struct ath_txq *txq = NULL;
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const struct ath9k_rate_table *rt;
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struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
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struct ath_tx_info_priv *tx_info_priv;
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int hdrlen;
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u8 rix, antenna;
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struct ath_rc_series *rcs;
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struct ieee80211_hdr *hdr;
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const struct ath9k_rate_table *rt;
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bool use_minrate;
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__le16 fc;
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u8 *qc;
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txctl->dev = sc;
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hdr = (struct ieee80211_hdr *)skb->data;
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hdrlen = ieee80211_get_hdrlen_from_skb(skb);
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fc = hdr->frame_control;
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u8 rix;
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rt = sc->sc_currates;
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BUG_ON(!rt);
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if (ieee80211_is_data_qos(fc)) {
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qc = ieee80211_get_qos_ctl(hdr);
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txctl->tidno = qc[0] & 0xf;
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}
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txctl->if_id = 0;
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txctl->frmlen = skb->len + FCS_LEN - (hdrlen & 3);
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/* Always try at highest power possible unless the the device
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* was configured by the user to use another power. */
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if (likely(sc->sc_config.txpowlimit == ATH_TXPOWER_MAX))
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txctl->txpower = ATH_TXPOWER_MAX;
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else
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txctl->txpower = sc->sc_config.txpowlimit;
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/* Fill Key related fields */
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txctl->keytype = ATH9K_KEY_TYPE_CLEAR;
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txctl->keyix = ATH9K_TXKEYIX_INVALID;
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if (tx_info->control.hw_key) {
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txctl->keyix = tx_info->control.hw_key->hw_key_idx;
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txctl->frmlen += tx_info->control.hw_key->icv_len;
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if (tx_info->control.hw_key->alg == ALG_WEP)
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txctl->keytype = ATH9K_KEY_TYPE_WEP;
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else if (tx_info->control.hw_key->alg == ALG_TKIP)
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txctl->keytype = ATH9K_KEY_TYPE_TKIP;
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else if (tx_info->control.hw_key->alg == ALG_CCMP)
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txctl->keytype = ATH9K_KEY_TYPE_AES;
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}
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/* Fill packet type */
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txctl->atype = get_hal_packet_type(hdr);
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/* Fill qnum */
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if (unlikely(txctl->flags & ATH9K_TXDESC_CAB)) {
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txctl->qnum = 0;
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txq = sc->sc_cabq;
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} else {
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txctl->qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
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txq = &sc->sc_txq[txctl->qnum];
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}
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spin_lock_bh(&txq->axq_lock);
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/* Try to avoid running out of descriptors */
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if (txq->axq_depth >= (ATH_TXBUF - 20) &&
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!(txctl->flags & ATH9K_TXDESC_CAB)) {
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DPRINTF(sc, ATH_DBG_FATAL,
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"%s: TX queue: %d is full, depth: %d\n",
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__func__,
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txctl->qnum,
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txq->axq_depth);
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ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
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txq->stopped = 1;
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spin_unlock_bh(&txq->axq_lock);
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return -1;
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}
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spin_unlock_bh(&txq->axq_lock);
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/* Fill rate */
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fill_min_rates(skb, txctl);
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/* Fill flags */
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txctl->flags |= ATH9K_TXDESC_CLRDMASK /* needed for crypto errors */
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| ATH9K_TXDESC_INTREQ; /* Generate an interrupt */
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if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
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txctl->flags |= ATH9K_TXDESC_NOACK;
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if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
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txctl->flags |= ATH9K_TXDESC_RTSENA;
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/*
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* Setup for rate calculations.
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*/
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/* XXX: HACK! */
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tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif;
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hdr = (struct ieee80211_hdr *)skb->data;
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fc = hdr->frame_control;
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tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif; /* HACK */
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rcs = tx_info_priv->rcs;
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if (ieee80211_is_data(fc) && !txctl->use_minrate) {
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/* Enable HT only for DATA frames and not for EAPOL */
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/* XXX why AMPDU only?? */
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txctl->ht = (hw->conf.ht.enabled &&
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(tx_info->flags & IEEE80211_TX_CTL_AMPDU));
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/* Check if min rates have to be used */
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use_minrate = check_min_rate(skb);
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if (ieee80211_is_data(fc) && !use_minrate) {
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if (is_multicast_ether_addr(hdr->addr1)) {
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rcs[0].rix = (u8)
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ath_tx_findindex(rt, txctl->mcast_rate);
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/*
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* mcast packets are not re-tried.
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*/
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rcs[0].rix =
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ath_tx_findindex(rt, tx_info_priv->min_rate);
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/* mcast packets are not re-tried */
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rcs[0].tries = 1;
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}
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/* For HT capable stations, we save tidno for later use.
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* We also override seqno set by upper layer with the one
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* in tx aggregation state.
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*
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* First, the fragmentation stat is determined.
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* If fragmentation is on, the sequence number is
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* not overridden, since it has been
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* incremented by the fragmentation routine.
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*/
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if (likely(!(txctl->flags & ATH9K_TXDESC_FRAG_IS_ON)) &&
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txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
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struct ath_atx_tid *tid;
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tid = ATH_AN_2_TID(txctl->an, txctl->tidno);
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hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
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IEEE80211_SEQ_SEQ_SHIFT);
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txctl->seqno = tid->seq_next;
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INCR(tid->seq_next, IEEE80211_SEQ_MAX);
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}
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} else {
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/* for management and control frames,
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* or for NULL and EAPOL frames */
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if (txctl->min_rate)
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rcs[0].rix = ath_rate_findrateix(sc, txctl->min_rate);
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or for NULL and EAPOL frames */
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if (use_minrate)
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rcs[0].rix = ath_rate_findrateix(sc, tx_info_priv->min_rate);
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else
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rcs[0].rix = 0;
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rcs[0].tries = ATH_MGT_TXMAXTRY;
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}
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rix = rcs[0].rix;
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if (ieee80211_has_morefrags(fc) ||
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(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) {
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/*
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** Force hardware to use computed duration for next
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** fragment by disabling multi-rate retry, which
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** updates duration based on the multi-rate
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** duration table.
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*/
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rcs[1].tries = rcs[2].tries = rcs[3].tries = 0;
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rcs[1].rix = rcs[2].rix = rcs[3].rix = 0;
|
||||
/* reset tries but keep rate index */
|
||||
rcs[0].tries = ATH_TXMAXTRY;
|
||||
}
|
||||
}
|
||||
|
||||
if (is_multicast_ether_addr(hdr->addr1)) {
|
||||
antenna = sc->sc_mcastantenna + 1;
|
||||
sc->sc_mcastantenna = (sc->sc_mcastantenna + 1) & 0x1;
|
||||
/* Called only when tx aggregation is enabled and HT is supported */
|
||||
|
||||
static void assign_aggr_tid_seqno(struct sk_buff *skb,
|
||||
struct ath_buf *bf)
|
||||
{
|
||||
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
|
||||
struct ieee80211_hdr *hdr;
|
||||
struct ath_node *an;
|
||||
struct ath_atx_tid *tid;
|
||||
__le16 fc;
|
||||
u8 *qc;
|
||||
|
||||
if (!tx_info->control.sta)
|
||||
return;
|
||||
|
||||
an = (struct ath_node *)tx_info->control.sta->drv_priv;
|
||||
hdr = (struct ieee80211_hdr *)skb->data;
|
||||
fc = hdr->frame_control;
|
||||
|
||||
/* Get tidno */
|
||||
|
||||
if (ieee80211_is_data_qos(fc)) {
|
||||
qc = ieee80211_get_qos_ctl(hdr);
|
||||
bf->bf_tidno = qc[0] & 0xf;
|
||||
}
|
||||
|
||||
return 0;
|
||||
/* Get seqno */
|
||||
|
||||
if (ieee80211_is_data(fc) && !check_min_rate(skb)) {
|
||||
/* For HT capable stations, we save tidno for later use.
|
||||
* We also override seqno set by upper layer with the one
|
||||
* in tx aggregation state.
|
||||
*
|
||||
* If fragmentation is on, the sequence number is
|
||||
* not overridden, since it has been
|
||||
* incremented by the fragmentation routine.
|
||||
*
|
||||
* FIXME: check if the fragmentation threshold exceeds
|
||||
* IEEE80211 max.
|
||||
*/
|
||||
tid = ATH_AN_2_TID(an, bf->bf_tidno);
|
||||
hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
|
||||
IEEE80211_SEQ_SEQ_SHIFT);
|
||||
bf->bf_seqno = tid->seq_next;
|
||||
INCR(tid->seq_next, IEEE80211_SEQ_MAX);
|
||||
}
|
||||
}
|
||||
|
||||
static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
|
||||
struct ath_txq *txq)
|
||||
{
|
||||
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
|
||||
int flags = 0;
|
||||
|
||||
flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
|
||||
flags |= ATH9K_TXDESC_INTREQ;
|
||||
|
||||
if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
|
||||
flags |= ATH9K_TXDESC_NOACK;
|
||||
if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
|
||||
flags |= ATH9K_TXDESC_RTSENA;
|
||||
|
||||
return flags;
|
||||
}
|
||||
|
||||
static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
|
||||
{
|
||||
struct ath_buf *bf = NULL;
|
||||
|
||||
spin_lock_bh(&sc->sc_txbuflock);
|
||||
|
||||
if (unlikely(list_empty(&sc->sc_txbuf))) {
|
||||
spin_unlock_bh(&sc->sc_txbuflock);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list);
|
||||
list_del(&bf->list);
|
||||
|
||||
spin_unlock_bh(&sc->sc_txbuflock);
|
||||
|
||||
return bf;
|
||||
}
|
||||
|
||||
/* To complete a chain of buffers associated a frame */
|
||||
@ -402,7 +366,7 @@ static void ath_tx_complete_buf(struct ath_softc *sc,
|
||||
skb->len,
|
||||
PCI_DMA_TODEVICE);
|
||||
/* complete this frame */
|
||||
ath_tx_complete(sc, skb, &tx_status, bf->bf_node);
|
||||
ath_tx_complete(sc, skb, &tx_status);
|
||||
|
||||
/*
|
||||
* Return the list of ath_buf of this mpdu to free queue
|
||||
@ -615,7 +579,15 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
||||
u32 ctsduration = 0;
|
||||
u8 rix = 0, cix, ctsrate = 0;
|
||||
u32 aggr_limit_with_rts = ah->ah_caps.rts_aggr_limit;
|
||||
struct ath_node *an = (struct ath_node *) bf->bf_node;
|
||||
struct ath_node *an = NULL;
|
||||
struct sk_buff *skb;
|
||||
struct ieee80211_tx_info *tx_info;
|
||||
|
||||
skb = (struct sk_buff *)bf->bf_mpdu;
|
||||
tx_info = IEEE80211_SKB_CB(skb);
|
||||
|
||||
if (tx_info->control.sta)
|
||||
an = (struct ath_node *)tx_info->control.sta->drv_priv;
|
||||
|
||||
/*
|
||||
* get the cix for the lowest valid rix.
|
||||
@ -654,7 +626,6 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
||||
* use RTS.
|
||||
*/
|
||||
if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) {
|
||||
BUG_ON(!an);
|
||||
/*
|
||||
* 802.11g protection not needed, use our default behavior
|
||||
*/
|
||||
@ -664,7 +635,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
||||
* For dynamic MIMO PS, RTS needs to precede the first aggregate
|
||||
* and the second aggregate should have any protection at all.
|
||||
*/
|
||||
if (an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) {
|
||||
if (an && an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) {
|
||||
if (!bf_isaggrburst(bf)) {
|
||||
flags = ATH9K_TXDESC_RTSENA;
|
||||
dynamic_mimops = 1;
|
||||
@ -736,7 +707,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
||||
(bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG),
|
||||
bf_isshpreamble(bf));
|
||||
|
||||
if ((an->an_smmode == ATH_SM_PWRSAV_STATIC) &&
|
||||
if (an && (an->an_smmode == ATH_SM_PWRSAV_STATIC) &&
|
||||
(bf->bf_rcs[i].flags & ATH_RC_DS_FLAG) == 0) {
|
||||
/*
|
||||
* When sending to an HT node that has enabled static
|
||||
@ -888,8 +859,10 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
|
||||
struct list_head *bf_q,
|
||||
int txok)
|
||||
{
|
||||
struct ath_node *an = bf->bf_node;
|
||||
struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
|
||||
struct ath_node *an = NULL;
|
||||
struct sk_buff *skb;
|
||||
struct ieee80211_tx_info *tx_info;
|
||||
struct ath_atx_tid *tid = NULL;
|
||||
struct ath_buf *bf_last = bf->bf_lastbf;
|
||||
struct ath_desc *ds = bf_last->bf_desc;
|
||||
struct ath_buf *bf_next, *bf_lastq = NULL;
|
||||
@ -898,6 +871,14 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
|
||||
u32 ba[WME_BA_BMP_SIZE >> 5];
|
||||
int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
|
||||
|
||||
skb = (struct sk_buff *)bf->bf_mpdu;
|
||||
tx_info = IEEE80211_SKB_CB(skb);
|
||||
|
||||
if (tx_info->control.sta) {
|
||||
an = (struct ath_node *)tx_info->control.sta->drv_priv;
|
||||
tid = ATH_AN_2_TID(an, bf->bf_tidno);
|
||||
}
|
||||
|
||||
isaggr = bf_isaggr(bf);
|
||||
if (isaggr) {
|
||||
if (txok) {
|
||||
@ -1030,7 +1011,6 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
|
||||
|
||||
/* copy descriptor content */
|
||||
tbf->bf_mpdu = bf_last->bf_mpdu;
|
||||
tbf->bf_node = bf_last->bf_node;
|
||||
tbf->bf_buf_addr = bf_last->bf_buf_addr;
|
||||
*(tbf->bf_desc) = *(bf_last->bf_desc);
|
||||
|
||||
@ -1364,7 +1344,6 @@ static void ath_tx_addto_baw(struct ath_softc *sc,
|
||||
*/
|
||||
|
||||
static int ath_tx_send_ampdu(struct ath_softc *sc,
|
||||
struct ath_txq *txq,
|
||||
struct ath_atx_tid *tid,
|
||||
struct list_head *bf_head,
|
||||
struct ath_tx_control *txctl)
|
||||
@ -1378,8 +1357,6 @@ static int ath_tx_send_ampdu(struct ath_softc *sc,
|
||||
|
||||
bf = list_first_entry(bf_head, struct ath_buf, list);
|
||||
bf->bf_state.bf_type |= BUF_AMPDU;
|
||||
bf->bf_seqno = txctl->seqno; /* save seqno and tidno in buffer */
|
||||
bf->bf_tidno = txctl->tidno;
|
||||
|
||||
/*
|
||||
* Do not queue to h/w when any of the following conditions is true:
|
||||
@ -1390,13 +1367,13 @@ static int ath_tx_send_ampdu(struct ath_softc *sc,
|
||||
*/
|
||||
if (!list_empty(&tid->buf_q) || tid->paused ||
|
||||
!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
|
||||
txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
|
||||
txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
|
||||
/*
|
||||
* Add this frame to software queue for scheduling later
|
||||
* for aggregation.
|
||||
*/
|
||||
list_splice_tail_init(bf_head, &tid->buf_q);
|
||||
ath_tx_queue_tid(txq, tid);
|
||||
ath_tx_queue_tid(txctl->txq, tid);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1413,7 +1390,7 @@ static int ath_tx_send_ampdu(struct ath_softc *sc,
|
||||
bf->bf_nframes = 1;
|
||||
bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
|
||||
ath_buf_set_rate(sc, bf);
|
||||
ath_tx_txqaddbuf(sc, txq, bf_head);
|
||||
ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1836,46 +1813,27 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
|
||||
}
|
||||
}
|
||||
|
||||
static int ath_tx_start_dma(struct ath_softc *sc,
|
||||
struct sk_buff *skb,
|
||||
struct scatterlist *sg,
|
||||
u32 n_sg,
|
||||
struct ath_tx_control *txctl)
|
||||
static void ath_tx_setup_buffer(struct ath_softc *sc, struct ath_buf *bf,
|
||||
struct sk_buff *skb, struct scatterlist *sg,
|
||||
struct ath_tx_control *txctl)
|
||||
{
|
||||
struct ath_node *an = txctl->an;
|
||||
struct ath_buf *bf = NULL;
|
||||
struct list_head bf_head;
|
||||
struct ath_desc *ds;
|
||||
struct ath_hal *ah = sc->sc_ah;
|
||||
struct ath_txq *txq;
|
||||
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
|
||||
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
|
||||
struct ath_tx_info_priv *tx_info_priv;
|
||||
struct ath_rc_series *rcs;
|
||||
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
|
||||
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
|
||||
__le16 fc = hdr->frame_control;
|
||||
int hdrlen;
|
||||
__le16 fc;
|
||||
|
||||
if (unlikely(txctl->flags & ATH9K_TXDESC_CAB))
|
||||
txq = sc->sc_cabq;
|
||||
else
|
||||
txq = &sc->sc_txq[txctl->qnum];
|
||||
tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif;
|
||||
hdrlen = ieee80211_get_hdrlen_from_skb(skb);
|
||||
fc = hdr->frame_control;
|
||||
rcs = tx_info_priv->rcs;
|
||||
|
||||
/* For each sglist entry, allocate an ath_buf for DMA */
|
||||
INIT_LIST_HEAD(&bf_head);
|
||||
spin_lock_bh(&sc->sc_txbuflock);
|
||||
if (unlikely(list_empty(&sc->sc_txbuf))) {
|
||||
spin_unlock_bh(&sc->sc_txbuflock);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list);
|
||||
list_del(&bf->list);
|
||||
spin_unlock_bh(&sc->sc_txbuflock);
|
||||
|
||||
list_add_tail(&bf->list, &bf_head);
|
||||
|
||||
/* set up this buffer */
|
||||
ATH_TXBUF_RESET(bf);
|
||||
bf->bf_frmlen = txctl->frmlen;
|
||||
|
||||
/* Frame type */
|
||||
|
||||
bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
|
||||
|
||||
ieee80211_is_data(fc) ?
|
||||
(bf->bf_state.bf_type |= BUF_DATA) :
|
||||
@ -1889,121 +1847,143 @@ static int ath_tx_start_dma(struct ath_softc *sc,
|
||||
(sc->sc_flags & SC_OP_PREAMBLE_SHORT) ?
|
||||
(bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE) :
|
||||
(bf->bf_state.bf_type &= ~BUF_SHORT_PREAMBLE);
|
||||
(sc->hw->conf.ht.enabled &&
|
||||
(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) ?
|
||||
(bf->bf_state.bf_type |= BUF_HT) :
|
||||
(bf->bf_state.bf_type &= ~BUF_HT);
|
||||
|
||||
bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
|
||||
|
||||
/* Crypto */
|
||||
|
||||
bf->bf_keytype = get_hw_crypto_keytype(skb);
|
||||
|
||||
if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
|
||||
bf->bf_frmlen += tx_info->control.hw_key->icv_len;
|
||||
bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
|
||||
} else {
|
||||
bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
|
||||
}
|
||||
|
||||
/* Rate series */
|
||||
|
||||
setup_rate_retries(sc, skb);
|
||||
|
||||
bf->bf_flags = txctl->flags;
|
||||
bf->bf_keytype = txctl->keytype;
|
||||
/* XXX: HACK! */
|
||||
tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif;
|
||||
rcs = tx_info_priv->rcs;
|
||||
bf->bf_rcs[0] = rcs[0];
|
||||
bf->bf_rcs[1] = rcs[1];
|
||||
bf->bf_rcs[2] = rcs[2];
|
||||
bf->bf_rcs[3] = rcs[3];
|
||||
bf->bf_node = an;
|
||||
|
||||
/* Assign seqno, tidno */
|
||||
|
||||
if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR))
|
||||
assign_aggr_tid_seqno(skb, bf);
|
||||
|
||||
/* DMA setup */
|
||||
|
||||
bf->bf_mpdu = skb;
|
||||
bf->bf_buf_addr = sg_dma_address(sg);
|
||||
bf->bf_dmacontext = pci_map_single(sc->pdev, skb->data,
|
||||
skb->len, PCI_DMA_TODEVICE);
|
||||
bf->bf_buf_addr = bf->bf_dmacontext;
|
||||
}
|
||||
|
||||
/* FIXME: tx power */
|
||||
static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
|
||||
struct scatterlist *sg, u32 n_sg,
|
||||
struct ath_tx_control *txctl)
|
||||
{
|
||||
struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
|
||||
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
|
||||
struct ath_node *an = NULL;
|
||||
struct list_head bf_head;
|
||||
struct ath_desc *ds;
|
||||
struct ath_atx_tid *tid;
|
||||
struct ath_hal *ah = sc->sc_ah;
|
||||
int frm_type;
|
||||
|
||||
if (tx_info->control.sta) {
|
||||
an = (struct ath_node *)tx_info->control.sta->drv_priv;
|
||||
tid = ATH_AN_2_TID(an, bf->bf_tidno);
|
||||
}
|
||||
|
||||
frm_type = get_hw_packet_type(skb);
|
||||
|
||||
INIT_LIST_HEAD(&bf_head);
|
||||
list_add_tail(&bf->list, &bf_head);
|
||||
|
||||
/* setup descriptor */
|
||||
|
||||
ds = bf->bf_desc;
|
||||
ds->ds_link = 0;
|
||||
ds->ds_data = bf->bf_buf_addr;
|
||||
|
||||
/*
|
||||
* Save the DMA context in the first ath_buf
|
||||
*/
|
||||
bf->bf_dmacontext = txctl->dmacontext;
|
||||
/* Formulate first tx descriptor with tx controls */
|
||||
|
||||
/*
|
||||
* Formulate first tx descriptor with tx controls.
|
||||
*/
|
||||
ath9k_hw_set11n_txdesc(ah,
|
||||
ds,
|
||||
bf->bf_frmlen, /* frame length */
|
||||
txctl->atype, /* Atheros packet type */
|
||||
min(txctl->txpower, (u16)60), /* txpower */
|
||||
txctl->keyix, /* key cache index */
|
||||
txctl->keytype, /* key type */
|
||||
txctl->flags); /* flags */
|
||||
ath9k_hw_filltxdesc(ah,
|
||||
ds,
|
||||
sg_dma_len(sg), /* segment length */
|
||||
true, /* first segment */
|
||||
(n_sg == 1) ? true : false, /* last segment */
|
||||
ds); /* first descriptor */
|
||||
ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
|
||||
bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
|
||||
|
||||
ath9k_hw_filltxdesc(ah, ds,
|
||||
sg_dma_len(sg), /* segment length */
|
||||
true, /* first segment */
|
||||
(n_sg == 1) ? true : false, /* last segment */
|
||||
ds); /* first descriptor */
|
||||
|
||||
bf->bf_lastfrm = bf;
|
||||
(txctl->ht) ?
|
||||
(bf->bf_state.bf_type |= BUF_HT) :
|
||||
(bf->bf_state.bf_type &= ~BUF_HT);
|
||||
|
||||
spin_lock_bh(&txq->axq_lock);
|
||||
spin_lock_bh(&txctl->txq->axq_lock);
|
||||
|
||||
if (txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
|
||||
struct ath_atx_tid *tid = ATH_AN_2_TID(an, txctl->tidno);
|
||||
if (ath_aggr_query(sc, an, txctl->tidno)) {
|
||||
if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR)) {
|
||||
if (ath_aggr_query(sc, an, bf->bf_tidno)) {
|
||||
/*
|
||||
* Try aggregation if it's a unicast data frame
|
||||
* and the destination is HT capable.
|
||||
*/
|
||||
ath_tx_send_ampdu(sc, txq, tid, &bf_head, txctl);
|
||||
ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
|
||||
} else {
|
||||
/*
|
||||
* Send this frame as regular when ADDBA exchange
|
||||
* is neither complete nor pending.
|
||||
* Send this frame as regular when ADDBA
|
||||
* exchange is neither complete nor pending.
|
||||
*/
|
||||
ath_tx_send_normal(sc, txq, tid, &bf_head);
|
||||
ath_tx_send_normal(sc, txctl->txq,
|
||||
tid, &bf_head);
|
||||
}
|
||||
} else {
|
||||
bf->bf_lastbf = bf;
|
||||
bf->bf_nframes = 1;
|
||||
|
||||
ath_buf_set_rate(sc, bf);
|
||||
|
||||
if (ieee80211_is_back_req(fc)) {
|
||||
/* This is required for resuming tid
|
||||
* during BAR completion */
|
||||
bf->bf_tidno = txctl->tidno;
|
||||
}
|
||||
|
||||
ath_tx_txqaddbuf(sc, txq, &bf_head);
|
||||
ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
|
||||
}
|
||||
spin_unlock_bh(&txq->axq_lock);
|
||||
return 0;
|
||||
|
||||
spin_unlock_bh(&txctl->txq->axq_lock);
|
||||
}
|
||||
|
||||
static void xmit_map_sg(struct ath_softc *sc,
|
||||
struct sk_buff *skb,
|
||||
struct ath_tx_control *txctl)
|
||||
int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
|
||||
struct ath_tx_control *txctl)
|
||||
{
|
||||
struct ath_xmit_status tx_status;
|
||||
struct ath_atx_tid *tid;
|
||||
struct ath_buf *bf;
|
||||
struct scatterlist sg;
|
||||
|
||||
txctl->dmacontext = pci_map_single(sc->pdev, skb->data,
|
||||
skb->len, PCI_DMA_TODEVICE);
|
||||
/* Check if a tx buffer is available */
|
||||
|
||||
bf = ath_tx_get_buffer(sc);
|
||||
if (!bf) {
|
||||
DPRINTF(sc, ATH_DBG_XMIT, "%s: TX buffers are full\n",
|
||||
__func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
ath_tx_setup_buffer(sc, bf, skb, &sg, txctl);
|
||||
|
||||
/* Setup S/G */
|
||||
|
||||
/* setup S/G list */
|
||||
memset(&sg, 0, sizeof(struct scatterlist));
|
||||
sg_dma_address(&sg) = txctl->dmacontext;
|
||||
sg_dma_address(&sg) = bf->bf_dmacontext;
|
||||
sg_dma_len(&sg) = skb->len;
|
||||
|
||||
if (ath_tx_start_dma(sc, skb, &sg, 1, txctl) != 0) {
|
||||
/*
|
||||
* We have to do drop frame here.
|
||||
*/
|
||||
pci_unmap_single(sc->pdev, txctl->dmacontext,
|
||||
skb->len, PCI_DMA_TODEVICE);
|
||||
ath_tx_start_dma(sc, bf, &sg, 1, txctl);
|
||||
|
||||
tx_status.retries = 0;
|
||||
tx_status.flags = ATH_TX_ERROR;
|
||||
|
||||
if (txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
|
||||
/* Reclaim the seqno. */
|
||||
tid = ATH_AN_2_TID((struct ath_node *)
|
||||
txctl->an, txctl->tidno);
|
||||
DECR(tid->seq_next, IEEE80211_SEQ_MAX);
|
||||
}
|
||||
ath_tx_complete(sc, skb, &tx_status, txctl->an);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Initialize TX queue and h/w */
|
||||
@ -2189,6 +2169,34 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
|
||||
return qnum;
|
||||
}
|
||||
|
||||
/* Get a transmit queue, if available */
|
||||
|
||||
struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
|
||||
{
|
||||
struct ath_txq *txq = NULL;
|
||||
int qnum;
|
||||
|
||||
qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
|
||||
txq = &sc->sc_txq[qnum];
|
||||
|
||||
spin_lock_bh(&txq->axq_lock);
|
||||
|
||||
/* Try to avoid running out of descriptors */
|
||||
if (txq->axq_depth >= (ATH_TXBUF - 20)) {
|
||||
DPRINTF(sc, ATH_DBG_FATAL,
|
||||
"%s: TX queue: %d is full, depth: %d\n",
|
||||
__func__, qnum, txq->axq_depth);
|
||||
ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
|
||||
txq->stopped = 1;
|
||||
spin_unlock_bh(&txq->axq_lock);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
spin_unlock_bh(&txq->axq_lock);
|
||||
|
||||
return txq;
|
||||
}
|
||||
|
||||
/* Update parameters for a transmit queue */
|
||||
|
||||
int ath_txq_update(struct ath_softc *sc, int qnum,
|
||||
@ -2252,25 +2260,6 @@ int ath_cabq_update(struct ath_softc *sc)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb)
|
||||
{
|
||||
struct ath_tx_control txctl;
|
||||
int error = 0;
|
||||
|
||||
memset(&txctl, 0, sizeof(struct ath_tx_control));
|
||||
error = ath_tx_prepare(sc, skb, &txctl);
|
||||
if (error == 0)
|
||||
/*
|
||||
* Start DMA mapping.
|
||||
* ath_tx_start_dma() will be called either synchronously
|
||||
* or asynchrounsly once DMA is complete.
|
||||
*/
|
||||
xmit_map_sg(sc, skb, &txctl);
|
||||
|
||||
/* failed packets will be dropped by the caller */
|
||||
return error;
|
||||
}
|
||||
|
||||
/* Deferred processing of transmit interrupt */
|
||||
|
||||
void ath_tx_tasklet(struct ath_softc *sc)
|
||||
@ -2668,6 +2657,8 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
|
||||
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
|
||||
struct ath_tx_control txctl;
|
||||
|
||||
memset(&txctl, 0, sizeof(struct ath_tx_control));
|
||||
|
||||
/*
|
||||
* As a temporary workaround, assign seq# here; this will likely need
|
||||
* to be cleaned up to work better with Beacon transmission and virtual
|
||||
@ -2695,22 +2686,18 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
|
||||
memmove(skb->data, skb->data + padsize, hdrlen);
|
||||
}
|
||||
|
||||
txctl.txq = sc->sc_cabq;
|
||||
|
||||
DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting CABQ packet, skb: %p\n",
|
||||
__func__,
|
||||
skb);
|
||||
|
||||
memset(&txctl, 0, sizeof(struct ath_tx_control));
|
||||
txctl.flags = ATH9K_TXDESC_CAB;
|
||||
if (ath_tx_prepare(sc, skb, &txctl) == 0) {
|
||||
/*
|
||||
* Start DMA mapping.
|
||||
* ath_tx_start_dma() will be called either synchronously
|
||||
* or asynchrounsly once DMA is complete.
|
||||
*/
|
||||
xmit_map_sg(sc, skb, &txctl);
|
||||
} else {
|
||||
DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ failed\n", __func__);
|
||||
dev_kfree_skb_any(skb);
|
||||
if (ath_tx_start(sc, skb, &txctl) != 0) {
|
||||
DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
|
||||
goto exit;
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
exit:
|
||||
dev_kfree_skb_any(skb);
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user