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powerpc/b4860: Renamed the L2 caches

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To make provision for more than one L2 caches in the system, change the
name from L2 to L2_1; same as in T4 platforms.
* Also remove the L2 entry from common file
  "arch/powerpc/boot/dts/fsl/b4si-post.dtsi"
  Keep them only in separate files for b4860 and b4420.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
poonam aggrwal 2015-09-19 23:45:42 +05:30 committed by Scott Wood
parent dc37374b9c
commit 5224644551
5 changed files with 12 additions and 14 deletions
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4
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
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@ -89,7 +89,9 @@
compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0"; compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
}; };
L2: l2-cache-controller@c20000 { L2_1: l2-cache-controller@c20000 {
compatible = "fsl,b4420-l2-cache-controller"; compatible = "fsl,b4420-l2-cache-controller";
reg = <0xc20000 0x40000>;
next-level-cache = <&cpc>;
}; };
}; };

4
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
View File

@ -65,14 +65,14 @@
device_type = "cpu"; device_type = "cpu";
reg = <0 1>; reg = <0 1>;
clocks = <&mux0>; clocks = <&mux0>;
next-level-cache = <&L2>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu1: PowerPC,e6500@2 { cpu1: PowerPC,e6500@2 {
device_type = "cpu"; device_type = "cpu";
reg = <2 3>; reg = <2 3>;
clocks = <&mux0>; clocks = <&mux0>;
next-level-cache = <&L2>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
}; };

4
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
View File

@ -258,7 +258,9 @@
compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0"; compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0";
}; };
L2: l2-cache-controller@c20000 { L2_1: l2-cache-controller@c20000 {
compatible = "fsl,b4860-l2-cache-controller"; compatible = "fsl,b4860-l2-cache-controller";
reg = <0xc20000 0x40000>;
next-level-cache = <&cpc>;
}; };
}; };

8
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
View File

@ -65,28 +65,28 @@
device_type = "cpu"; device_type = "cpu";
reg = <0 1>; reg = <0 1>;
clocks = <&mux0>; clocks = <&mux0>;
next-level-cache = <&L2>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu1: PowerPC,e6500@2 { cpu1: PowerPC,e6500@2 {
device_type = "cpu"; device_type = "cpu";
reg = <2 3>; reg = <2 3>;
clocks = <&mux0>; clocks = <&mux0>;
next-level-cache = <&L2>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu2: PowerPC,e6500@4 { cpu2: PowerPC,e6500@4 {
device_type = "cpu"; device_type = "cpu";
reg = <4 5>; reg = <4 5>;
clocks = <&mux0>; clocks = <&mux0>;
next-level-cache = <&L2>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu3: PowerPC,e6500@6 { cpu3: PowerPC,e6500@6 {
device_type = "cpu"; device_type = "cpu";
reg = <6 7>; reg = <6 7>;
clocks = <&mux0>; clocks = <&mux0>;
next-level-cache = <&L2>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
}; };

6
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
View File

@ -465,10 +465,4 @@
bman: bman@31a000 { bman: bman@31a000 {
interrupts = <16 2 1 29>; interrupts = <16 2 1 29>;
}; };
L2: l2-cache-controller@c20000 {
compatible = "fsl,b4-l2-cache-controller";
reg = <0xc20000 0x1000>;
next-level-cache = <&cpc>;
};
}; };