ASoC: tlv320aic32x4: Model PLL in CCF
Model and manage the on-board PLL as a component in the Core Clock Framework. This should allow us to do some more complex clock management and power control. Also, some of the on-board chip clocks can be exposed to the outside, and this change will make those clocks easier to consume by other parts of the kernel. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Annaliese McDermond
Mark Brown
parent
8633d44002
commit
514b044cba
@ -1105,6 +1105,7 @@ config SND_SOC_TLV320AIC31XX
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config SND_SOC_TLV320AIC32X4
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tristate
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depends on COMMON_CLK
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config SND_SOC_TLV320AIC32X4_I2C
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tristate "Texas Instruments TLV320AIC32x4 audio CODECs - I2C"
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@ -193,7 +193,7 @@ snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o
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snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o
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snd-soc-tlv320aic26-objs := tlv320aic26.o
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snd-soc-tlv320aic31xx-objs := tlv320aic31xx.o
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snd-soc-tlv320aic32x4-objs := tlv320aic32x4.o
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snd-soc-tlv320aic32x4-objs := tlv320aic32x4.o tlv320aic32x4-clk.o
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snd-soc-tlv320aic32x4-i2c-objs := tlv320aic32x4-i2c.o
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snd-soc-tlv320aic32x4-spi-objs := tlv320aic32x4-spi.o
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snd-soc-tlv320aic3x-objs := tlv320aic3x.o
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323
sound/soc/codecs/tlv320aic32x4-clk.c
Normal file
323
sound/soc/codecs/tlv320aic32x4-clk.c
Normal file
@ -0,0 +1,323 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Clock Tree for the Texas Instruments TLV320AIC32x4
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*
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* Copyright 2019 Annaliese McDermond
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*
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* Author: Annaliese McDermond <nh6z@nh6z.net>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/regmap.h>
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#include <linux/device.h>
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#include "tlv320aic32x4.h"
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#define to_clk_aic32x4(_hw) container_of(_hw, struct clk_aic32x4, hw)
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struct clk_aic32x4 {
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struct clk_hw hw;
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struct device *dev;
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struct regmap *regmap;
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unsigned int reg;
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};
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/*
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* struct clk_aic32x4_pll_muldiv - Multiplier/divider settings
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* @p: Divider
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* @r: first multiplier
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* @j: integer part of second multiplier
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* @d: decimal part of second multiplier
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*/
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struct clk_aic32x4_pll_muldiv {
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u8 p;
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u16 r;
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u8 j;
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u16 d;
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};
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struct aic32x4_clkdesc {
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const char *name;
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const char * const *parent_names;
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unsigned int num_parents;
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const struct clk_ops *ops;
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unsigned int reg;
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};
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static int clk_aic32x4_pll_prepare(struct clk_hw *hw)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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return regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
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AIC32X4_PLLEN, AIC32X4_PLLEN);
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}
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static void clk_aic32x4_pll_unprepare(struct clk_hw *hw)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
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AIC32X4_PLLEN, 0);
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}
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static int clk_aic32x4_pll_is_prepared(struct clk_hw *hw)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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unsigned int val;
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int ret;
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ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
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if (ret < 0)
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return ret;
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return !!(val & AIC32X4_PLLEN);
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}
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static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll,
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struct clk_aic32x4_pll_muldiv *settings)
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{
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/* Change to use regmap_bulk_read? */
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unsigned int val;
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int ret;
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ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
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if (ret)
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return ret;
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settings->r = val & AIC32X4_PLL_R_MASK;
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settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT;
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ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val);
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if (ret < 0)
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return ret;
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settings->j = val;
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ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val);
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if (ret < 0)
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return ret;
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settings->d = val << 8;
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ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB, &val);
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if (ret < 0)
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return ret;
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settings->d |= val;
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return 0;
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}
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static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll,
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struct clk_aic32x4_pll_muldiv *settings)
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{
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int ret;
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/* Change to use regmap_bulk_write for some if not all? */
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ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
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AIC32X4_PLL_R_MASK, settings->r);
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if (ret < 0)
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return ret;
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ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
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AIC32X4_PLL_P_MASK,
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settings->p << AIC32X4_PLL_P_SHIFT);
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if (ret < 0)
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return ret;
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ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j);
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if (ret < 0)
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return ret;
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ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8));
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if (ret < 0)
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return ret;
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ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff));
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if (ret < 0)
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return ret;
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return 0;
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}
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static unsigned long clk_aic32x4_pll_calc_rate(
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struct clk_aic32x4_pll_muldiv *settings,
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unsigned long parent_rate)
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{
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u64 rate;
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/*
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* We scale j by 10000 to account for the decimal part of P and divide
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* it back out later.
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*/
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rate = (u64) parent_rate * settings->r *
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((settings->j * 10000) + settings->d);
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return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000);
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}
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static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings,
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unsigned long rate, unsigned long parent_rate)
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{
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u64 multiplier;
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settings->p = parent_rate / AIC32X4_MAX_PLL_CLKIN + 1;
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if (settings->p > 8)
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return -1;
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/*
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* We scale this figure by 10000 so that we can get the decimal part
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* of the multiplier. This is because we can't do floating point
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* math in the kernel.
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*/
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multiplier = (u64) rate * settings->p * 10000;
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do_div(multiplier, parent_rate);
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/*
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* J can't be over 64, so R can scale this.
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* R can't be greater than 4.
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*/
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settings->r = ((u32) multiplier / 640000) + 1;
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if (settings->r > 4)
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return -1;
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do_div(multiplier, settings->r);
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/*
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* J can't be < 1.
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*/
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if (multiplier < 10000)
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return -1;
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/* Figure out the integer part, J, and the fractional part, D. */
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settings->j = (u32) multiplier / 10000;
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settings->d = (u32) multiplier % 10000;
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return 0;
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}
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static unsigned long clk_aic32x4_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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struct clk_aic32x4_pll_muldiv settings;
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int ret;
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ret = clk_aic32x4_pll_get_muldiv(pll, &settings);
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if (ret < 0)
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return 0;
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return clk_aic32x4_pll_calc_rate(&settings, parent_rate);
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}
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static long clk_aic32x4_pll_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_aic32x4_pll_muldiv settings;
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int ret;
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ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, *parent_rate);
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if (ret < 0)
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return 0;
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return clk_aic32x4_pll_calc_rate(&settings, *parent_rate);
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}
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static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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struct clk_aic32x4_pll_muldiv settings;
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int ret;
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ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, parent_rate);
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if (ret < 0)
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return -EINVAL;
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return clk_aic32x4_pll_set_muldiv(pll, &settings);
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}
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static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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return regmap_update_bits(pll->regmap,
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AIC32X4_CLKMUX,
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AIC32X4_PLL_CLKIN_MASK,
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index << AIC32X4_PLL_CLKIN_SHIFT);
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}
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static u8 clk_aic32x4_pll_get_parent(struct clk_hw *hw)
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{
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struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
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unsigned int val;
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regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
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return (val & AIC32X4_PLL_CLKIN_MASK) >> AIC32X4_PLL_CLKIN_SHIFT;
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}
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static const struct clk_ops aic32x4_pll_ops = {
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.prepare = clk_aic32x4_pll_prepare,
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.unprepare = clk_aic32x4_pll_unprepare,
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.is_prepared = clk_aic32x4_pll_is_prepared,
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.recalc_rate = clk_aic32x4_pll_recalc_rate,
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.round_rate = clk_aic32x4_pll_round_rate,
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.set_rate = clk_aic32x4_pll_set_rate,
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.set_parent = clk_aic32x4_pll_set_parent,
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.get_parent = clk_aic32x4_pll_get_parent,
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};
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static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
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{
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.name = "pll",
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.parent_names =
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(const char* []) { "mclk", "bclk", "gpio", "din" },
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.num_parents = 4,
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.ops = &aic32x4_pll_ops,
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.reg = 0,
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},
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};
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static struct clk *aic32x4_register_clk(struct device *dev,
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struct aic32x4_clkdesc *desc)
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{
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struct clk_init_data init;
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struct clk_aic32x4 *priv;
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const char *devname = dev_name(dev);
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init.ops = desc->ops;
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init.name = desc->name;
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init.parent_names = desc->parent_names;
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init.num_parents = desc->num_parents;
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init.flags = 0;
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priv = devm_kzalloc(dev, sizeof(struct clk_aic32x4), GFP_KERNEL);
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if (priv == NULL)
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return (struct clk *) -ENOMEM;
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priv->dev = dev;
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priv->hw.init = &init;
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priv->regmap = dev_get_regmap(dev, NULL);
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priv->reg = desc->reg;
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clk_hw_register_clkdev(&priv->hw, desc->name, devname);
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return devm_clk_register(dev, &priv->hw);
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}
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int aic32x4_register_clocks(struct device *dev, const char *mclk_name)
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{
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int i;
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/*
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* These lines are here to preserve the current functionality of
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* the driver with regard to the DT. These should eventually be set
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* by DT nodes so that the connections can be set up in configuration
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* rather than code.
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*/
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aic32x4_clkdesc_array[0].parent_names =
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(const char* []) { mclk_name, "bclk", "gpio", "din" };
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for (i = 0; i < ARRAY_SIZE(aic32x4_clkdesc_array); ++i)
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aic32x4_register_clk(dev, &aic32x4_clkdesc_array[i]);
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return 0;
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}
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EXPORT_SYMBOL_GPL(aic32x4_register_clocks);
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@ -14,7 +14,7 @@
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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@ -33,6 +33,7 @@
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#include <linux/cdev.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/of_clk.h>
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#include <linux/regulator/consumer.h>
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#include <sound/tlv320aic32x4.h>
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@ -49,9 +50,7 @@
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struct aic32x4_rate_divs {
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u32 mclk;
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u32 rate;
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u8 p_val;
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u8 pll_j;
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u16 pll_d;
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unsigned long pll_rate;
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u16 dosr;
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u8 ndac;
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u8 mdac;
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@ -71,6 +70,7 @@ struct aic32x4_priv {
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bool swapdacs;
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int rstn_gpio;
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struct clk *mclk;
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const char *mclk_name;
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struct regulator *supply_ldo;
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struct regulator *supply_iov;
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@ -309,34 +309,34 @@ static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
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static const struct aic32x4_rate_divs aic32x4_divs[] = {
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/* 8k rate */
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{12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24, 1, 1},
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{24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24, 1, 1},
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{25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24, 1, 1},
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{ 12000000, 8000, 57120000, 768, 5, 3, 128, 5, 18, 24, 1, 1 },
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{ 24000000, 8000, 57120000, 768, 15, 1, 64, 45, 4, 24, 1, 1 },
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{ 25000000, 8000, 32620000, 768, 15, 1, 64, 45, 4, 24, 1, 1 },
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/* 11.025k rate */
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{12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16, 1, 1},
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{24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16, 1, 1},
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{ 12000000, 11025, 44217600, 512, 8, 2, 128, 8, 8, 16, 1, 1 },
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{ 24000000, 11025, 44217600, 512, 16, 1, 64, 32, 4, 16, 1, 1 },
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/* 16k rate */
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{12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12, 1, 1},
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{24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12, 1, 1},
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{25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12, 1, 1},
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{ 12000000, 16000, 57120000, 384, 5, 3, 128, 5, 9, 12, 1, 1 },
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{ 24000000, 16000, 57120000, 384, 15, 1, 64, 18, 5, 12, 1, 1 },
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{ 25000000, 16000, 32620000, 384, 15, 1, 64, 18, 5, 12, 1, 1 },
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/* 22.05k rate */
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{12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8, 1, 1},
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{24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8, 1, 1},
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{25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8, 1, 1},
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{ 12000000, 22050, 44217600, 256, 4, 4, 128, 4, 8, 8, 1, 1 },
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{ 24000000, 22050, 44217600, 256, 16, 1, 64, 16, 4, 8, 1, 1 },
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{ 25000000, 22050, 19713750, 256, 16, 1, 64, 16, 4, 8, 1, 1 },
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/* 32k rate */
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{12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6, 1, 1},
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{24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6, 1, 1},
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{ 12000000, 32000, 14112000, 192, 2, 7, 64, 2, 21, 6, 1, 1 },
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{ 24000000, 32000, 14112000, 192, 7, 2, 64, 7, 6, 6, 1, 1 },
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/* 44.1k rate */
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{12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4, 1, 1},
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{24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4, 1, 1},
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{25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4, 1, 1},
|
||||
{ 12000000, 44100, 44217600, 128, 2, 8, 128, 2, 8, 4, 1, 1 },
|
||||
{ 24000000, 44100, 44217600, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
|
||||
{ 25000000, 44100, 19713750, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
|
||||
/* 48k rate */
|
||||
{12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4, 1, 1},
|
||||
{24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4, 1, 1},
|
||||
{25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4, 1, 1},
|
||||
{ 12000000, 48000, 18432000, 128, 2, 8, 128, 2, 8, 4, 1, 1 },
|
||||
{ 24000000, 48000, 18432000, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
|
||||
{ 25000000, 48000, 75626250, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
|
||||
|
||||
/* 96k rate */
|
||||
{25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1, 1, 9},
|
||||
{ 25000000, 96000, 75626250, 64, 4, 4, 64, 4, 4, 1, 1, 9 },
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
|
||||
@ -393,7 +393,7 @@ static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
|
||||
SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
|
||||
};
|
||||
|
||||
/* Right mixer pins */
|
||||
/* Right mixer pins */
|
||||
static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
|
||||
static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
|
||||
static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
|
||||
@ -595,7 +595,7 @@ static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
|
||||
static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
|
||||
{
|
||||
.selector_reg = 0,
|
||||
.selector_mask = 0xff,
|
||||
.selector_mask = 0xff,
|
||||
.window_start = 0,
|
||||
.window_len = 128,
|
||||
.range_min = 0,
|
||||
@ -616,7 +616,7 @@ static inline int aic32x4_get_divs(int mclk, int rate)
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
|
||||
if ((aic32x4_divs[i].rate == rate)
|
||||
&& (aic32x4_divs[i].mclk == mclk)) {
|
||||
&& (aic32x4_divs[i].mclk == mclk)) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
@ -688,12 +688,12 @@ static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
|
||||
}
|
||||
|
||||
snd_soc_component_update_bits(component, AIC32X4_IFACE1,
|
||||
AIC32X4_IFACE1_DATATYPE_MASK |
|
||||
AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
|
||||
AIC32X4_IFACE1_DATATYPE_MASK |
|
||||
AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
|
||||
snd_soc_component_update_bits(component, AIC32X4_IFACE2,
|
||||
AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
|
||||
AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
|
||||
snd_soc_component_update_bits(component, AIC32X4_IFACE3,
|
||||
AIC32X4_BCLKINV_MASK, iface_reg_3);
|
||||
AIC32X4_BCLKINV_MASK, iface_reg_3);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -715,6 +715,11 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component,
|
||||
unsigned int parent_rate)
|
||||
{
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
struct clk_bulk_data clocks[] = {
|
||||
{ .id = "pll" },
|
||||
};
|
||||
|
||||
i = aic32x4_get_divs(parent_rate, sample_rate);
|
||||
if (i < 0) {
|
||||
@ -722,39 +727,29 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component,
|
||||
return i;
|
||||
}
|
||||
|
||||
ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
clk_set_rate(clocks[0].clk, sample_rate);
|
||||
|
||||
aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
|
||||
|
||||
/* MCLK as PLL_CLKIN */
|
||||
snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK,
|
||||
AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT);
|
||||
/* PLL as CODEC_CLKIN */
|
||||
snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_MASK,
|
||||
AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
|
||||
snd_soc_component_update_bits(component, AIC32X4_CLKMUX,
|
||||
AIC32X4_CODEC_CLKIN_MASK,
|
||||
AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
|
||||
/* DAC_MOD_CLK as BDIV_CLKIN */
|
||||
snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
|
||||
AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
|
||||
|
||||
/* We will fix R value to 1 and will make P & J=K.D as variable */
|
||||
snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_R_MASK, 0x01);
|
||||
|
||||
/* PLL P value */
|
||||
snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_P_MASK,
|
||||
aic32x4_divs[i].p_val << AIC32X4_PLL_P_SHIFT);
|
||||
|
||||
/* PLL J value */
|
||||
snd_soc_component_write(component, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
|
||||
|
||||
/* PLL D value */
|
||||
snd_soc_component_write(component, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
|
||||
snd_soc_component_write(component, AIC32X4_PLLDLSB, (aic32x4_divs[i].pll_d & 0xff));
|
||||
AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
|
||||
|
||||
/* NDAC divider value */
|
||||
snd_soc_component_update_bits(component, AIC32X4_NDAC,
|
||||
AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
|
||||
AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
|
||||
|
||||
/* MDAC divider value */
|
||||
snd_soc_component_update_bits(component, AIC32X4_MDAC,
|
||||
AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
|
||||
AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
|
||||
|
||||
/* DOSR MSB & LSB values */
|
||||
snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
|
||||
@ -762,18 +757,18 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component,
|
||||
|
||||
/* NADC divider value */
|
||||
snd_soc_component_update_bits(component, AIC32X4_NADC,
|
||||
AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
|
||||
AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
|
||||
|
||||
/* MADC divider value */
|
||||
snd_soc_component_update_bits(component, AIC32X4_MADC,
|
||||
AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
|
||||
AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
|
||||
|
||||
/* AOSR value */
|
||||
snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr);
|
||||
|
||||
/* BCLK N divider */
|
||||
snd_soc_component_update_bits(component, AIC32X4_BCLKN,
|
||||
AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
|
||||
AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -792,23 +787,23 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
|
||||
switch (params_width(params)) {
|
||||
case 16:
|
||||
iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
|
||||
AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
break;
|
||||
case 20:
|
||||
iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
|
||||
AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
break;
|
||||
case 24:
|
||||
iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
|
||||
AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
break;
|
||||
case 32:
|
||||
iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
|
||||
AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
AIC32X4_IFACE1_DATALEN_SHIFT);
|
||||
break;
|
||||
}
|
||||
snd_soc_component_update_bits(component, AIC32X4_IFACE1,
|
||||
AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
|
||||
AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
|
||||
|
||||
if (params_channels(params) == 1) {
|
||||
dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
|
||||
@ -819,7 +814,7 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
|
||||
dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
|
||||
}
|
||||
snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
|
||||
AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
|
||||
AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -829,7 +824,7 @@ static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
|
||||
struct snd_soc_component *component = dai->component;
|
||||
|
||||
snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
|
||||
AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
|
||||
AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -851,27 +846,27 @@ static int aic32x4_set_bias_level(struct snd_soc_component *component,
|
||||
|
||||
/* Switch on PLL */
|
||||
snd_soc_component_update_bits(component, AIC32X4_PLLPR,
|
||||
AIC32X4_PLLEN, AIC32X4_PLLEN);
|
||||
AIC32X4_PLLEN, AIC32X4_PLLEN);
|
||||
|
||||
/* Switch on NDAC Divider */
|
||||
snd_soc_component_update_bits(component, AIC32X4_NDAC,
|
||||
AIC32X4_NDACEN, AIC32X4_NDACEN);
|
||||
AIC32X4_NDACEN, AIC32X4_NDACEN);
|
||||
|
||||
/* Switch on MDAC Divider */
|
||||
snd_soc_component_update_bits(component, AIC32X4_MDAC,
|
||||
AIC32X4_MDACEN, AIC32X4_MDACEN);
|
||||
AIC32X4_MDACEN, AIC32X4_MDACEN);
|
||||
|
||||
/* Switch on NADC Divider */
|
||||
snd_soc_component_update_bits(component, AIC32X4_NADC,
|
||||
AIC32X4_NADCEN, AIC32X4_NADCEN);
|
||||
AIC32X4_NADCEN, AIC32X4_NADCEN);
|
||||
|
||||
/* Switch on MADC Divider */
|
||||
snd_soc_component_update_bits(component, AIC32X4_MADC,
|
||||
AIC32X4_MADCEN, AIC32X4_MADCEN);
|
||||
AIC32X4_MADCEN, AIC32X4_MADCEN);
|
||||
|
||||
/* Switch on BCLK_N Divider */
|
||||
snd_soc_component_update_bits(component, AIC32X4_BCLKN,
|
||||
AIC32X4_BCLKEN, AIC32X4_BCLKEN);
|
||||
AIC32X4_BCLKEN, AIC32X4_BCLKEN);
|
||||
break;
|
||||
case SND_SOC_BIAS_PREPARE:
|
||||
break;
|
||||
@ -882,27 +877,27 @@ static int aic32x4_set_bias_level(struct snd_soc_component *component,
|
||||
|
||||
/* Switch off BCLK_N Divider */
|
||||
snd_soc_component_update_bits(component, AIC32X4_BCLKN,
|
||||
AIC32X4_BCLKEN, 0);
|
||||
AIC32X4_BCLKEN, 0);
|
||||
|
||||
/* Switch off MADC Divider */
|
||||
snd_soc_component_update_bits(component, AIC32X4_MADC,
|
||||
AIC32X4_MADCEN, 0);
|
||||
AIC32X4_MADCEN, 0);
|
||||
|
||||
/* Switch off NADC Divider */
|
||||
snd_soc_component_update_bits(component, AIC32X4_NADC,
|
||||
AIC32X4_NADCEN, 0);
|
||||
AIC32X4_NADCEN, 0);
|
||||
|
||||
/* Switch off MDAC Divider */
|
||||
snd_soc_component_update_bits(component, AIC32X4_MDAC,
|
||||
AIC32X4_MDACEN, 0);
|
||||
AIC32X4_MDACEN, 0);
|
||||
|
||||
/* Switch off NDAC Divider */
|
||||
snd_soc_component_update_bits(component, AIC32X4_NDAC,
|
||||
AIC32X4_NDACEN, 0);
|
||||
AIC32X4_NDACEN, 0);
|
||||
|
||||
/* Switch off PLL */
|
||||
snd_soc_component_update_bits(component, AIC32X4_PLLPR,
|
||||
AIC32X4_PLLEN, 0);
|
||||
AIC32X4_PLLEN, 0);
|
||||
|
||||
/* Switch off master clock */
|
||||
clk_disable_unprepare(aic32x4->mclk);
|
||||
@ -914,7 +909,7 @@ static int aic32x4_set_bias_level(struct snd_soc_component *component,
|
||||
}
|
||||
|
||||
#define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000
|
||||
#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
|
||||
#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
|
||||
| SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
|
||||
|
||||
static const struct snd_soc_dai_ops aic32x4_ops = {
|
||||
@ -927,17 +922,17 @@ static const struct snd_soc_dai_ops aic32x4_ops = {
|
||||
static struct snd_soc_dai_driver aic32x4_dai = {
|
||||
.name = "tlv320aic32x4-hifi",
|
||||
.playback = {
|
||||
.stream_name = "Playback",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = AIC32X4_RATES,
|
||||
.formats = AIC32X4_FORMATS,},
|
||||
.stream_name = "Playback",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = AIC32X4_RATES,
|
||||
.formats = AIC32X4_FORMATS,},
|
||||
.capture = {
|
||||
.stream_name = "Capture",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = AIC32X4_RATES,
|
||||
.formats = AIC32X4_FORMATS,},
|
||||
.stream_name = "Capture",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = AIC32X4_RATES,
|
||||
.formats = AIC32X4_FORMATS,},
|
||||
.ops = &aic32x4_ops,
|
||||
.symmetric_rates = 1,
|
||||
};
|
||||
@ -950,7 +945,7 @@ static void aic32x4_setup_gpios(struct snd_soc_component *component)
|
||||
/* MFP1 */
|
||||
if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
|
||||
snd_soc_component_write(component, AIC32X4_DINCTL,
|
||||
aic32x4->setup->gpio_func[0]);
|
||||
aic32x4->setup->gpio_func[0]);
|
||||
snd_soc_add_component_controls(component, aic32x4_mfp1,
|
||||
ARRAY_SIZE(aic32x4_mfp1));
|
||||
}
|
||||
@ -958,7 +953,7 @@ static void aic32x4_setup_gpios(struct snd_soc_component *component)
|
||||
/* MFP2 */
|
||||
if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
|
||||
snd_soc_component_write(component, AIC32X4_DOUTCTL,
|
||||
aic32x4->setup->gpio_func[1]);
|
||||
aic32x4->setup->gpio_func[1]);
|
||||
snd_soc_add_component_controls(component, aic32x4_mfp2,
|
||||
ARRAY_SIZE(aic32x4_mfp2));
|
||||
}
|
||||
@ -966,7 +961,7 @@ static void aic32x4_setup_gpios(struct snd_soc_component *component)
|
||||
/* MFP3 */
|
||||
if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
|
||||
snd_soc_component_write(component, AIC32X4_SCLKCTL,
|
||||
aic32x4->setup->gpio_func[2]);
|
||||
aic32x4->setup->gpio_func[2]);
|
||||
snd_soc_add_component_controls(component, aic32x4_mfp3,
|
||||
ARRAY_SIZE(aic32x4_mfp3));
|
||||
}
|
||||
@ -974,7 +969,7 @@ static void aic32x4_setup_gpios(struct snd_soc_component *component)
|
||||
/* MFP4 */
|
||||
if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
|
||||
snd_soc_component_write(component, AIC32X4_MISOCTL,
|
||||
aic32x4->setup->gpio_func[3]);
|
||||
aic32x4->setup->gpio_func[3]);
|
||||
snd_soc_add_component_controls(component, aic32x4_mfp4,
|
||||
ARRAY_SIZE(aic32x4_mfp4));
|
||||
}
|
||||
@ -982,7 +977,7 @@ static void aic32x4_setup_gpios(struct snd_soc_component *component)
|
||||
/* MFP5 */
|
||||
if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
|
||||
snd_soc_component_write(component, AIC32X4_GPIOCTL,
|
||||
aic32x4->setup->gpio_func[4]);
|
||||
aic32x4->setup->gpio_func[4]);
|
||||
snd_soc_add_component_controls(component, aic32x4_mfp5,
|
||||
ARRAY_SIZE(aic32x4_mfp5));
|
||||
}
|
||||
@ -1006,8 +1001,8 @@ static int aic32x4_component_probe(struct snd_soc_component *component)
|
||||
|
||||
/* Power platform configuration */
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
|
||||
snd_soc_component_write(component, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
|
||||
AIC32X4_MICBIAS_2075V);
|
||||
snd_soc_component_write(component, AIC32X4_MICBIAS,
|
||||
AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
|
||||
}
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
|
||||
snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
|
||||
@ -1070,12 +1065,18 @@ static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
|
||||
struct device_node *np)
|
||||
{
|
||||
struct aic32x4_setup_data *aic32x4_setup;
|
||||
int ret;
|
||||
|
||||
aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
|
||||
GFP_KERNEL);
|
||||
if (!aic32x4_setup)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = of_property_match_string(np, "clock-names", "mclk");
|
||||
if (ret < 0)
|
||||
return -EINVAL;
|
||||
aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
|
||||
|
||||
aic32x4->swapdacs = false;
|
||||
aic32x4->micpga_routing = 0;
|
||||
aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
|
||||
@ -1197,7 +1198,7 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap)
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
|
||||
GFP_KERNEL);
|
||||
GFP_KERNEL);
|
||||
if (aic32x4 == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
@ -1209,6 +1210,7 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap)
|
||||
aic32x4->swapdacs = pdata->swapdacs;
|
||||
aic32x4->micpga_routing = pdata->micpga_routing;
|
||||
aic32x4->rstn_gpio = pdata->rstn_gpio;
|
||||
aic32x4->mclk_name = "mclk";
|
||||
} else if (np) {
|
||||
ret = aic32x4_parse_dt(aic32x4, np);
|
||||
if (ret) {
|
||||
@ -1220,6 +1222,7 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap)
|
||||
aic32x4->swapdacs = false;
|
||||
aic32x4->micpga_routing = 0;
|
||||
aic32x4->rstn_gpio = -1;
|
||||
aic32x4->mclk_name = "mclk";
|
||||
}
|
||||
|
||||
aic32x4->mclk = devm_clk_get(dev, "mclk");
|
||||
@ -1228,6 +1231,10 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap)
|
||||
return PTR_ERR(aic32x4->mclk);
|
||||
}
|
||||
|
||||
ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (gpio_is_valid(aic32x4->rstn_gpio)) {
|
||||
ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
|
||||
GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
|
||||
|
||||
@ -16,6 +16,7 @@ struct regmap_config;
|
||||
extern const struct regmap_config aic32x4_regmap_config;
|
||||
int aic32x4_probe(struct device *dev, struct regmap *regmap);
|
||||
int aic32x4_remove(struct device *dev);
|
||||
int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
|
||||
|
||||
/* tlv320aic32x4 register space (in decimal to match datasheet) */
|
||||
|
||||
@ -205,4 +206,8 @@ int aic32x4_remove(struct device *dev);
|
||||
#define AIC32X4_RMICPGANIN_IN1L_10K 0x10
|
||||
#define AIC32X4_RMICPGANIN_CM1R_10K 0x40
|
||||
|
||||
/* Clock Limits */
|
||||
#define AIC32X4_MAX_PLL_CLKIN 20000000
|
||||
|
||||
|
||||
#endif /* _TLV320AIC32X4_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user