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tile/PCI: use cached pci_dev->pcie_mpss to simplify code

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The PCI core caches the "PCIe Max Payload Size Supported" in
pci_dev->pcie_mpss, so use that instead of pcie_capability_read_dword().

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Yijing Wang 2013-09-09 21:13:04 +08:00 committed by Bjorn Helgaas
parent f1c66c4678
commit 503275bf37
1 changed files with 2 additions and 5 deletions
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7
arch/tile/kernel/pci.c
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@ -251,15 +251,12 @@ static void fixup_read_and_payload_sizes(void)
/* Scan for the smallest maximum payload size. */
for_each_pci_dev(dev) {
u32 devcap;
int max_payload;
if (!pci_is_pcie(dev))
continue;
pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap);
max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
if (max_payload < smallest_max_payload)
smallest_max_payload = max_payload;
if (dev->pcie_mpss < smallest_max_payload)
smallest_max_payload = dev->pcie_mpss;
}
/* Now, set the max_payload_size for all devices to that value. */