forked from Minki/linux
net: phy: Fixed checkpatch errors for Microsemi PHYs.
The existing VSC85xx PHY driver did not follow the coding style and caused "checkpatch" to complain. This commit fixes this. Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Raju Lakkaraju
David S. Miller
parent
05f1b12f71
commit
4ffd03f5e4
@ -274,9 +274,9 @@ config MICROCHIP_PHY
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Supports the LAN88XX PHYs.
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config MICROSEMI_PHY
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tristate "Microsemi PHYs"
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---help---
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Currently supports the VSC8531 and VSC8541 PHYs
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tristate "Microsemi PHYs"
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---help---
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Currently supports the VSC8531 and VSC8541 PHYs
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config NATIONAL_PHY
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tristate "National Semiconductor PHYs"
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@ -13,135 +13,135 @@
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#include <linux/phy.h>
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enum rgmii_rx_clock_delay {
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RGMII_RX_CLK_DELAY_0_2_NS = 0,
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RGMII_RX_CLK_DELAY_0_8_NS = 1,
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RGMII_RX_CLK_DELAY_1_1_NS = 2,
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RGMII_RX_CLK_DELAY_1_7_NS = 3,
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RGMII_RX_CLK_DELAY_2_0_NS = 4,
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RGMII_RX_CLK_DELAY_2_3_NS = 5,
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RGMII_RX_CLK_DELAY_2_6_NS = 6,
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RGMII_RX_CLK_DELAY_3_4_NS = 7
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RGMII_RX_CLK_DELAY_0_2_NS = 0,
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RGMII_RX_CLK_DELAY_0_8_NS = 1,
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RGMII_RX_CLK_DELAY_1_1_NS = 2,
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RGMII_RX_CLK_DELAY_1_7_NS = 3,
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RGMII_RX_CLK_DELAY_2_0_NS = 4,
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RGMII_RX_CLK_DELAY_2_3_NS = 5,
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RGMII_RX_CLK_DELAY_2_6_NS = 6,
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RGMII_RX_CLK_DELAY_3_4_NS = 7
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};
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#define MII_VSC85XX_INT_MASK 25
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#define MII_VSC85XX_INT_MASK_MASK 0xa000
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#define MII_VSC85XX_INT_STATUS 26
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#define MII_VSC85XX_INT_MASK 25
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#define MII_VSC85XX_INT_MASK_MASK 0xa000
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#define MII_VSC85XX_INT_STATUS 26
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#define MSCC_EXT_PAGE_ACCESS 31
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#define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
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#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
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#define MSCC_EXT_PAGE_ACCESS 31
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#define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
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#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
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/* Extended Page 2 Registers */
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#define MSCC_PHY_RGMII_CNTL 20
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#define RGMII_RX_CLK_DELAY_MASK 0x0070
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#define RGMII_RX_CLK_DELAY_POS 4
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#define MSCC_PHY_RGMII_CNTL 20
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#define RGMII_RX_CLK_DELAY_MASK 0x0070
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#define RGMII_RX_CLK_DELAY_POS 4
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/* Microsemi PHY ID's */
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#define PHY_ID_VSC8531 0x00070570
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#define PHY_ID_VSC8541 0x00070770
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#define PHY_ID_VSC8531 0x00070570
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#define PHY_ID_VSC8541 0x00070770
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static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
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{
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int rc;
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int rc;
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rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
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return rc;
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rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
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return rc;
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}
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static int vsc85xx_default_config(struct phy_device *phydev)
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{
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int rc;
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u16 reg_val;
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int rc;
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u16 reg_val;
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mutex_lock(&phydev->lock);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
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if (rc != 0)
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goto out_unlock;
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mutex_lock(&phydev->lock);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
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if (rc != 0)
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goto out_unlock;
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reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
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reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
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reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);
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phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
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reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
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reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
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reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);
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phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
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out_unlock:
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mutex_unlock(&phydev->lock);
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mutex_unlock(&phydev->lock);
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return rc;
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return rc;
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}
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static int vsc85xx_config_init(struct phy_device *phydev)
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{
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int rc;
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int rc;
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rc = vsc85xx_default_config(phydev);
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if (rc)
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return rc;
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rc = genphy_config_init(phydev);
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rc = vsc85xx_default_config(phydev);
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if (rc)
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return rc;
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rc = genphy_config_init(phydev);
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return rc;
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return rc;
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}
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static int vsc85xx_ack_interrupt(struct phy_device *phydev)
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{
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int rc = 0;
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int rc = 0;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
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return (rc < 0) ? rc : 0;
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return (rc < 0) ? rc : 0;
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}
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static int vsc85xx_config_intr(struct phy_device *phydev)
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{
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int rc;
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int rc;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
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MII_VSC85XX_INT_MASK_MASK);
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} else {
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rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
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if (rc < 0)
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return rc;
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rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
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}
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
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MII_VSC85XX_INT_MASK_MASK);
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} else {
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rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
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if (rc < 0)
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return rc;
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rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
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}
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return rc;
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return rc;
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}
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/* Microsemi VSC85xx PHYs */
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static struct phy_driver vsc85xx_driver[] = {
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{
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.phy_id = PHY_ID_VSC8531,
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.name = "Microsemi VSC8531",
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.phy_id_mask = 0xfffffff0,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.soft_reset = &genphy_soft_reset,
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.config_init = &vsc85xx_config_init,
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.config_aneg = &genphy_config_aneg,
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.aneg_done = &genphy_aneg_done,
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.read_status = &genphy_read_status,
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.ack_interrupt = &vsc85xx_ack_interrupt,
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.config_intr = &vsc85xx_config_intr,
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.suspend = &genphy_suspend,
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.resume = &genphy_resume,
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.phy_id = PHY_ID_VSC8531,
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.name = "Microsemi VSC8531",
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.phy_id_mask = 0xfffffff0,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.soft_reset = &genphy_soft_reset,
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.config_init = &vsc85xx_config_init,
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.config_aneg = &genphy_config_aneg,
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.aneg_done = &genphy_aneg_done,
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.read_status = &genphy_read_status,
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.ack_interrupt = &vsc85xx_ack_interrupt,
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.config_intr = &vsc85xx_config_intr,
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.suspend = &genphy_suspend,
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.resume = &genphy_resume,
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},
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{
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.phy_id = PHY_ID_VSC8541,
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.name = "Microsemi VSC8541 SyncE",
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.phy_id_mask = 0xfffffff0,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.soft_reset = &genphy_soft_reset,
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.config_init = &vsc85xx_config_init,
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.config_aneg = &genphy_config_aneg,
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.aneg_done = &genphy_aneg_done,
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.read_status = &genphy_read_status,
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.ack_interrupt = &vsc85xx_ack_interrupt,
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.config_intr = &vsc85xx_config_intr,
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.suspend = &genphy_suspend,
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.resume = &genphy_resume,
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.phy_id = PHY_ID_VSC8541,
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.name = "Microsemi VSC8541 SyncE",
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.phy_id_mask = 0xfffffff0,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.soft_reset = &genphy_soft_reset,
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.config_init = &vsc85xx_config_init,
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.config_aneg = &genphy_config_aneg,
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.aneg_done = &genphy_aneg_done,
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.read_status = &genphy_read_status,
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.ack_interrupt = &vsc85xx_ack_interrupt,
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.config_intr = &vsc85xx_config_intr,
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.suspend = &genphy_suspend,
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.resume = &genphy_resume,
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}
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};
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@ -149,9 +149,9 @@ static struct phy_driver vsc85xx_driver[] = {
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module_phy_driver(vsc85xx_driver);
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static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
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{ PHY_ID_VSC8531, 0xfffffff0, },
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{ PHY_ID_VSC8541, 0xfffffff0, },
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{ }
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{ PHY_ID_VSC8531, 0xfffffff0, },
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{ PHY_ID_VSC8541, 0xfffffff0, },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
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