mtd: spi-nor: Expose stuctures and functions to manufacturer drivers
Expose the flash_info struct and some function prototypes that will be used by manufacturers. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Boris Brezillon
Tudor Ambarus
parent
cb481b92d1
commit
4f50e102e2
@ -38,101 +38,9 @@
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*/
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#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
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#define SPI_NOR_MAX_ID_LEN 6
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#define SPI_NOR_MAX_ADDR_WIDTH 4
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/**
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* struct spi_nor_fixups - SPI NOR fixup hooks
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* @default_init: called after default flash parameters init. Used to tweak
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* flash parameters when information provided by the flash_info
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* table is incomplete or wrong.
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* @post_bfpt: called after the BFPT table has been parsed
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* @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
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* that do not support RDSFDP). Typically used to tweak various
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* parameters that could not be extracted by other means (i.e.
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* when information provided by the SFDP/flash_info tables are
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* incomplete or wrong).
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*
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* Those hooks can be used to tweak the SPI NOR configuration when the SFDP
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* table is broken or not available.
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*/
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struct spi_nor_fixups {
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void (*default_init)(struct spi_nor *nor);
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int (*post_bfpt)(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params);
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void (*post_sfdp)(struct spi_nor *nor);
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};
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struct flash_info {
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char *name;
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/*
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* This array stores the ID bytes.
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* The first three bytes are the JEDIC ID.
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* JEDEC ID zero means "no ID" (mostly older chips).
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*/
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u8 id[SPI_NOR_MAX_ID_LEN];
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u8 id_len;
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/* The size listed here is what works with SPINOR_OP_SE, which isn't
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* necessarily called a "sector" by the vendor.
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*/
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unsigned sector_size;
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u16 n_sectors;
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u16 page_size;
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u16 addr_width;
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u32 flags;
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#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
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#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
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#define SST_WRITE BIT(2) /* use SST byte programming */
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#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
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#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
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#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
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#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
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#define USE_FSR BIT(7) /* use flag status register */
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#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
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#define SPI_NOR_HAS_TB BIT(9) /*
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* Flash SR has Top/Bottom (TB) protect
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* bit. Must be used with
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* SPI_NOR_HAS_LOCK.
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*/
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#define SPI_NOR_XSR_RDY BIT(10) /*
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* S3AN flashes have specific opcode to
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* read the status register.
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* Flags SPI_NOR_XSR_RDY and SPI_S3AN
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* use the same bit as one implies the
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* other, but we will get rid of
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* SPI_S3AN soon.
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*/
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#define SPI_S3AN BIT(10) /*
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* Xilinx Spartan 3AN In-System Flash
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* (MFR cannot be used for probing
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* because it has the same value as
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* ATMEL flashes)
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*/
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#define SPI_NOR_4B_OPCODES BIT(11) /*
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* Use dedicated 4byte address op codes
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* to support memory size above 128Mib.
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*/
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#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
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#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
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#define USE_CLSR BIT(14) /* use CLSR command */
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#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
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#define SPI_NOR_TB_SR_BIT6 BIT(16) /*
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* Top/Bottom (TB) is bit 6 of
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* status register. Must be used with
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* SPI_NOR_HAS_TB.
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*/
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/* Part specific fixup hooks. */
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const struct spi_nor_fixups *fixups;
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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#define JEDEC_MFR(info) ((info)->id[0])
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/**
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* spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data
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@ -295,8 +203,8 @@ static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
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*
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* Return: number of bytes written successfully, -errno otherwise
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*/
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static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
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const u8 *buf)
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ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
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const u8 *buf)
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{
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if (nor->spimem)
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return spi_nor_spimem_write_data(nor, to, len, buf);
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@ -310,7 +218,7 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_write_enable(struct spi_nor *nor)
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int spi_nor_write_enable(struct spi_nor *nor)
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{
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int ret;
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@ -339,7 +247,7 @@ static int spi_nor_write_enable(struct spi_nor *nor)
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_write_disable(struct spi_nor *nor)
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int spi_nor_write_disable(struct spi_nor *nor)
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{
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int ret;
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@ -463,7 +371,7 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
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int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
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{
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int ret;
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@ -556,7 +464,7 @@ static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
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int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
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{
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int ret;
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@ -621,7 +529,7 @@ static int winbond_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
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int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
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{
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int ret;
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@ -834,7 +742,7 @@ static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_wait_till_ready(struct spi_nor *nor)
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int spi_nor_wait_till_ready(struct spi_nor *nor)
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{
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return spi_nor_wait_till_ready_with_timeout(nor,
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DEFAULT_READY_WAIT_JIFFIES);
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@ -1142,11 +1050,6 @@ static int spi_nor_erase_chip(struct spi_nor *nor)
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return ret;
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}
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static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
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{
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return mtd->priv;
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}
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static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
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{
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size_t i;
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@ -1225,7 +1128,7 @@ static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
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}
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}
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static int spi_nor_lock_and_prep(struct spi_nor *nor)
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int spi_nor_lock_and_prep(struct spi_nor *nor)
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{
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int ret = 0;
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@ -1241,7 +1144,7 @@ static int spi_nor_lock_and_prep(struct spi_nor *nor)
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return ret;
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}
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static void spi_nor_unlock_and_unprep(struct spi_nor *nor)
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void spi_nor_unlock_and_unprep(struct spi_nor *nor)
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{
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if (nor->controller_ops && nor->controller_ops->unprepare)
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nor->controller_ops->unprepare(nor);
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@ -2104,56 +2007,6 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
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return 0;
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}
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/* Used when the "_ext_id" is two bytes at most */
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#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff, \
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((_ext_id) >> 8) & 0xff, \
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(_ext_id) & 0xff, \
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}, \
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.id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
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.sector_size = (_sector_size), \
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.n_sectors = (_n_sectors), \
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.page_size = 256, \
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.flags = (_flags),
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#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff, \
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((_ext_id) >> 16) & 0xff, \
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((_ext_id) >> 8) & 0xff, \
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(_ext_id) & 0xff, \
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}, \
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.id_len = 6, \
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.sector_size = (_sector_size), \
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.n_sectors = (_n_sectors), \
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.page_size = 256, \
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.flags = (_flags),
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#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
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.sector_size = (_sector_size), \
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.n_sectors = (_n_sectors), \
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.page_size = (_page_size), \
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.addr_width = (_addr_width), \
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.flags = (_flags),
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#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff \
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}, \
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.id_len = 3, \
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.sector_size = (8*_page_size), \
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.n_sectors = (_n_sectors), \
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.page_size = _page_size, \
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.addr_width = 3, \
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.flags = SPI_NOR_NO_FR | SPI_S3AN,
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static int
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is25lp256_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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@ -9,12 +9,165 @@
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#include "sfdp.h"
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#define SPI_NOR_MAX_ID_LEN 6
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/**
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* struct spi_nor_fixups - SPI NOR fixup hooks
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* @default_init: called after default flash parameters init. Used to tweak
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* flash parameters when information provided by the flash_info
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* table is incomplete or wrong.
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* @post_bfpt: called after the BFPT table has been parsed
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* @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
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* that do not support RDSFDP). Typically used to tweak various
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* parameters that could not be extracted by other means (i.e.
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* when information provided by the SFDP/flash_info tables are
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* incomplete or wrong).
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*
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* Those hooks can be used to tweak the SPI NOR configuration when the SFDP
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* table is broken or not available.
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*/
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struct spi_nor_fixups {
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void (*default_init)(struct spi_nor *nor);
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int (*post_bfpt)(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params);
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void (*post_sfdp)(struct spi_nor *nor);
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};
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struct flash_info {
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char *name;
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/*
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* This array stores the ID bytes.
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* The first three bytes are the JEDIC ID.
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* JEDEC ID zero means "no ID" (mostly older chips).
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*/
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u8 id[SPI_NOR_MAX_ID_LEN];
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u8 id_len;
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/* The size listed here is what works with SPINOR_OP_SE, which isn't
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* necessarily called a "sector" by the vendor.
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*/
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unsigned sector_size;
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u16 n_sectors;
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u16 page_size;
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u16 addr_width;
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u32 flags;
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#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
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#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
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#define SST_WRITE BIT(2) /* use SST byte programming */
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#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
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#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
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#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
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#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
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#define USE_FSR BIT(7) /* use flag status register */
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#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
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#define SPI_NOR_HAS_TB BIT(9) /*
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* Flash SR has Top/Bottom (TB) protect
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* bit. Must be used with
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* SPI_NOR_HAS_LOCK.
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*/
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#define SPI_NOR_XSR_RDY BIT(10) /*
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* S3AN flashes have specific opcode to
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* read the status register.
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* Flags SPI_NOR_XSR_RDY and SPI_S3AN
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* use the same bit as one implies the
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* other, but we will get rid of
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* SPI_S3AN soon.
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*/
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#define SPI_S3AN BIT(10) /*
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* Xilinx Spartan 3AN In-System Flash
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* (MFR cannot be used for probing
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* because it has the same value as
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* ATMEL flashes)
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*/
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#define SPI_NOR_4B_OPCODES BIT(11) /*
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* Use dedicated 4byte address op codes
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* to support memory size above 128Mib.
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*/
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#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
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#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
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#define USE_CLSR BIT(14) /* use CLSR command */
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#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
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#define SPI_NOR_TB_SR_BIT6 BIT(16) /*
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* Top/Bottom (TB) is bit 6 of
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* status register. Must be used with
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* SPI_NOR_HAS_TB.
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*/
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/* Part specific fixup hooks. */
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const struct spi_nor_fixups *fixups;
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};
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/* Used when the "_ext_id" is two bytes at most */
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#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff, \
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((_ext_id) >> 8) & 0xff, \
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(_ext_id) & 0xff, \
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}, \
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.id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
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.sector_size = (_sector_size), \
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.n_sectors = (_n_sectors), \
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.page_size = 256, \
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.flags = (_flags),
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#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff, \
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((_ext_id) >> 16) & 0xff, \
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((_ext_id) >> 8) & 0xff, \
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(_ext_id) & 0xff, \
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}, \
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.id_len = 6, \
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.sector_size = (_sector_size), \
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.n_sectors = (_n_sectors), \
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.page_size = 256, \
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.flags = (_flags),
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#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
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.sector_size = (_sector_size), \
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.n_sectors = (_n_sectors), \
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.page_size = (_page_size), \
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.addr_width = (_addr_width), \
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.flags = (_flags),
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#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff \
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}, \
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.id_len = 3, \
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.sector_size = (8*_page_size), \
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.n_sectors = (_n_sectors), \
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.page_size = _page_size, \
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.addr_width = 3, \
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.flags = SPI_NOR_NO_FR | SPI_S3AN,
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int spi_nor_write_enable(struct spi_nor *nor);
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int spi_nor_write_disable(struct spi_nor *nor);
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int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable);
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int spi_nor_write_ear(struct spi_nor *nor, u8 ear);
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int spi_nor_wait_till_ready(struct spi_nor *nor);
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int spi_nor_lock_and_prep(struct spi_nor *nor);
|
||||
void spi_nor_unlock_and_unprep(struct spi_nor *nor);
|
||||
int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
|
||||
int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
|
||||
int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
|
||||
|
||||
int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr);
|
||||
ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
|
||||
u8 *buf);
|
||||
ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
|
||||
const u8 *buf);
|
||||
|
||||
int spi_nor_hwcaps_read2cmd(u32 hwcaps);
|
||||
u8 spi_nor_convert_3to4_read(u8 opcode);
|
||||
@ -33,4 +186,9 @@ int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
|
||||
const struct sfdp_bfpt *bfpt,
|
||||
struct spi_nor_flash_parameter *params);
|
||||
|
||||
static struct spi_nor __maybe_unused *mtd_to_spi_nor(struct mtd_info *mtd)
|
||||
{
|
||||
return mtd->priv;
|
||||
}
|
||||
|
||||
#endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user