ARM: SMP: use idmap_pgd for mapping MMU enable during secondary booting
The ARM SMP booting code allocates a temporary set of page tables containing an identity mapping of the kernel image and provides this to secondary CPUs for initial booting. In reality, we only need to include the __turn_mmu_on function in the identity mapping since the rest of the kernel is executing from virtual addresses after this point. This patch adds __turn_mmu_on to the .idmap.text section, allowing the SMP booting code to use the idmap_pgd directly and not have to populate its own set of page table. As a result of this patch, we can make the identity_mapping_add function static (since it is only used within mm/idmap.c) and also remove the identity_mapping_del function. The identity map population is moved to an early initcall so that it is setup in time for secondary CPU bringup. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -9,9 +9,6 @@
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extern pgd_t *idmap_pgd;
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extern pgd_t *idmap_pgd;
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void identity_mapping_add(pgd_t *, unsigned long, unsigned long);
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void identity_mapping_del(pgd_t *, unsigned long, unsigned long);
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void setup_mm_for_reboot(void);
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void setup_mm_for_reboot(void);
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#endif /* __ASM_IDMAP_H */
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#endif /* __ASM_IDMAP_H */
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@ -398,7 +398,8 @@ ENDPROC(__enable_mmu)
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* other registers depend on the function called upon completion
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* other registers depend on the function called upon completion
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*/
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*/
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.align 5
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.align 5
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__turn_mmu_on:
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.pushsection .idmap.text, "ax"
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ENTRY(__turn_mmu_on)
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mov r0, r0
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mov r0, r0
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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mrc p15, 0, r3, c0, c0, 0 @ read id reg
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mrc p15, 0, r3, c0, c0, 0 @ read id reg
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@ -407,6 +408,7 @@ __turn_mmu_on:
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mov pc, r3
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mov pc, r3
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__turn_mmu_on_end:
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__turn_mmu_on_end:
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ENDPROC(__turn_mmu_on)
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ENDPROC(__turn_mmu_on)
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.popsection
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#ifdef CONFIG_SMP_ON_UP
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#ifdef CONFIG_SMP_ON_UP
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@ -62,7 +62,6 @@ int __cpuinit __cpu_up(unsigned int cpu)
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{
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{
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struct cpuinfo_arm *ci = &per_cpu(cpu_data, cpu);
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struct cpuinfo_arm *ci = &per_cpu(cpu_data, cpu);
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struct task_struct *idle = ci->idle;
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struct task_struct *idle = ci->idle;
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pgd_t *pgd;
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int ret;
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int ret;
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/*
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/*
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@ -84,30 +83,12 @@ int __cpuinit __cpu_up(unsigned int cpu)
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init_idle(idle, cpu);
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init_idle(idle, cpu);
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}
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}
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/*
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* Allocate initial page tables to allow the new CPU to
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* enable the MMU safely. This essentially means a set
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* of our "standard" page tables, with the addition of
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* a 1:1 mapping for the physical address of the kernel.
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*/
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pgd = pgd_alloc(&init_mm);
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if (!pgd)
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return -ENOMEM;
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if (PHYS_OFFSET != PAGE_OFFSET) {
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#ifndef CONFIG_HOTPLUG_CPU
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identity_mapping_add(pgd, __pa(__init_begin), __pa(__init_end));
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#endif
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identity_mapping_add(pgd, __pa(_stext), __pa(_etext));
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identity_mapping_add(pgd, __pa(_sdata), __pa(_edata));
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}
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/*
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/*
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* We need to tell the secondary core where to find
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* We need to tell the secondary core where to find
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* its stack and the page tables.
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* its stack and the page tables.
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*/
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*/
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secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
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secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
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secondary_data.pgdir = virt_to_phys(pgd);
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secondary_data.pgdir = virt_to_phys(idmap_pgd);
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secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
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secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
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__cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
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__cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
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outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
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outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
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@ -143,16 +124,6 @@ int __cpuinit __cpu_up(unsigned int cpu)
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secondary_data.stack = NULL;
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secondary_data.stack = NULL;
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secondary_data.pgdir = 0;
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secondary_data.pgdir = 0;
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if (PHYS_OFFSET != PAGE_OFFSET) {
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#ifndef CONFIG_HOTPLUG_CPU
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identity_mapping_del(pgd, __pa(__init_begin), __pa(__init_end));
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#endif
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identity_mapping_del(pgd, __pa(_stext), __pa(_etext));
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identity_mapping_del(pgd, __pa(_sdata), __pa(_edata));
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}
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pgd_free(&init_mm, pgd);
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return ret;
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return ret;
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}
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}
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@ -32,7 +32,7 @@ static void idmap_add_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
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} while (pud++, addr = next, addr != end);
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} while (pud++, addr = next, addr != end);
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}
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}
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void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end)
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static void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end)
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{
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{
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unsigned long prot, next;
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unsigned long prot, next;
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@ -47,36 +47,6 @@ void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end)
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} while (pgd++, addr = next, addr != end);
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} while (pgd++, addr = next, addr != end);
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}
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}
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#ifdef CONFIG_SMP
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static void idmap_del_pmd(pud_t *pud, unsigned long addr, unsigned long end)
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{
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pmd_t *pmd = pmd_offset(pud, addr);
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pmd_clear(pmd);
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}
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static void idmap_del_pud(pgd_t *pgd, unsigned long addr, unsigned long end)
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{
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pud_t *pud = pud_offset(pgd, addr);
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unsigned long next;
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do {
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next = pud_addr_end(addr, end);
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idmap_del_pmd(pud, addr, next);
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} while (pud++, addr = next, addr != end);
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}
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void identity_mapping_del(pgd_t *pgd, unsigned long addr, unsigned long end)
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{
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unsigned long next;
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pgd += pgd_index(addr);
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do {
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next = pgd_addr_end(addr, end);
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idmap_del_pud(pgd, addr, next);
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} while (pgd++, addr = next, addr != end);
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}
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#endif
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extern char __idmap_text_start[], __idmap_text_end[];
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extern char __idmap_text_start[], __idmap_text_end[];
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static int __init init_static_idmap(void)
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static int __init init_static_idmap(void)
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@ -97,7 +67,7 @@ static int __init init_static_idmap(void)
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return 0;
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return 0;
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}
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}
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arch_initcall(init_static_idmap);
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early_initcall(init_static_idmap);
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/*
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/*
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* In order to soft-boot, we need to switch to a 1:1 mapping for the
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* In order to soft-boot, we need to switch to a 1:1 mapping for the
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