leandrof/linux
1
0
Fork 0
forked from Minki/linux
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'ide-dcr' of git://git.kernel.org/pub/scm/linux/kernel/git/bart/misc

Browse Source
This commit is contained in:
David S. Miller 2009-12-03 13:25:13 -08:00
commit 4e5b932c82
6 changed files with 2 additions and 102 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/ide/alim15x3.c
View File

@ -39,16 +39,6 @@
#define DRV_NAME "alim15x3"
/*
* Allow UDMA on M1543C-E chipset for WDC disks that ignore CRC checking
* (this is DANGEROUS and could result in data corruption).
*/
static int wdc_udma;
module_param(wdc_udma, bool, 0);
MODULE_PARM_DESC(wdc_udma,
"allow UDMA on M1543C-E chipset for WDC disks (DANGEROUS)");
/*
* ALi devices are not plug in. Otherwise these static values would
* need to go. They ought to go away anyway
@ -132,7 +122,7 @@ static u8 ali_udma_filter(ide_drive_t *drive)
if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
if (drive->media != ide_disk)
return 0;
if (wdc_udma == 0 && chip_is_1543c_e &&
if (chip_is_1543c_e &&
strstr((char *)&drive->id[ATA_ID_PROD], "WDC "))
return 0;
}

17
drivers/ide/cmd64x.c
View File

@ -20,14 +20,6 @@
#define DRV_NAME "cmd64x"
#define CMD_DEBUG 0
#if CMD_DEBUG
#define cmdprintk(x...) printk(x)
#else
#define cmdprintk(x...)
#endif
/*
* CMD64x specific registers definition.
*/
@ -76,9 +68,6 @@ static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_
{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
cycle_time, active_time);
cycle_count = quantize_timing( cycle_time, clock_time);
active_count = quantize_timing(active_time, clock_time);
recovery_count = cycle_count - active_count;
@ -94,9 +83,6 @@ static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_
if (active_count > 16) /* shouldn't actually happen... */
active_count = 16;
cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
cycle_count, active_count, recovery_count);
/*
* Convert values to internal chipset representation
*/
@ -106,7 +92,6 @@ static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_
/* Program the active/recovery counts into the DRWTIM register */
drwtim = (active_count << 4) | recovery_count;
(void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
}
/*
@ -150,7 +135,6 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
if (setup_count > 5) /* shouldn't actually happen... */
setup_count = 5;
cmdprintk("Final address setup count: %d\n", setup_count);
/*
* Program the address setup clocks into the ARTTIM registers.
@ -162,7 +146,6 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
arttim &= ~0xc0;
arttim |= setup_values[setup_count];
(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
}
/*

27
drivers/ide/cy82c693.c
View File

@ -50,11 +50,6 @@
#define DRV_NAME "cy82c693"
/*
* The following are used to debug the driver.
*/
#define CY82C693_DEBUG_INFO 0
/*
* NOTE: the value for busmaster timeout is tricky and I got it by
* trial and error! By using a to low value will cause DMA timeouts
@ -176,11 +171,6 @@ static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
outb(index, CY82_INDEX_PORT);
outb(data, CY82_DATA_PORT);
#if CY82C693_DEBUG_INFO
printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
drive->name, hwif->channel, drive->dn & 1, mode & 3, single);
#endif /* CY82C693_DEBUG_INFO */
/*
* note: below we set the value for Bus Master IDE TimeOut Register
* I'm not absolutly sure what this does, but it solved my problem
@ -194,11 +184,6 @@ static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
data = BUSMASTER_TIMEOUT;
outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
outb(data, CY82_DATA_PORT);
#if CY82C693_DEBUG_INFO
printk(KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
drive->name, data);
#endif /* CY82C693_DEBUG_INFO */
}
static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
@ -239,8 +224,6 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
addrCtrl &= 0xF;
} else {
/*
* set slave drive
@ -257,17 +240,7 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
addrCtrl >>= 4;
addrCtrl &= 0xF;
}
#if CY82C693_DEBUG_INFO
printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
drive->name, hwif->channel, drive->dn & 1,
addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
#endif /* CY82C693_DEBUG_INFO */
}
static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)

15
drivers/ide/pdc202xx_old.c
View File

@ -21,8 +21,6 @@
#define DRV_NAME "pdc202xx_old"
#define PDC202XX_DEBUG_DRIVE_INFO 0
static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
@ -34,11 +32,6 @@ static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
u8 AP = 0, BP = 0, CP = 0;
u8 TA = 0, TB = 0, TC = 0;
#if PDC202XX_DEBUG_DRIVE_INFO
u32 drive_conf = 0;
pci_read_config_dword(dev, drive_pci, &drive_conf);
#endif
/*
* TODO: do this once per channel
*/
@ -89,14 +82,6 @@ static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
pci_write_config_byte(dev, drive_pci + 1, BP | TB);
pci_write_config_byte(dev, drive_pci + 2, CP | TC);
}
#if PDC202XX_DEBUG_DRIVE_INFO
printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
drive->name, ide_xfer_verbose(speed),
drive->dn, drive_conf);
pci_read_config_dword(dev, drive_pci, &drive_conf);
printk("0x%08x\n", drive_conf);
#endif
}
static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)

9
drivers/ide/sis5513.c
View File

@ -632,12 +632,3 @@ module_exit(sis5513_ide_exit);
MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
MODULE_DESCRIPTION("PCI driver module for SIS IDE");
MODULE_LICENSE("GPL");
/*
* TODO:
* - CLEANUP
* - More checks in the config registers (force values instead of
* relying on the BIOS setting them correctly).
* - Further optimisations ?
* . for example ATA66+ regs 0x48 & 0x4A
*/

24
drivers/ide/sl82c105.c
View File

@ -24,13 +24,6 @@
#define DRV_NAME "sl82c105"
#undef DEBUG
#ifdef DEBUG
#define DBG(arg) printk arg
#else
#define DBG(fmt,...)
#endif
/*
* SL82C105 PCI config register 0x40 bits.
*/
@ -104,9 +97,6 @@ static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
unsigned long timings = (unsigned long)ide_get_drivedata(drive);
u16 drv_ctrl;
DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
drive->name, ide_xfer_verbose(speed)));
drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
/*
@ -196,8 +186,6 @@ static void sl82c105_dma_start(ide_drive_t *drive)
struct pci_dev *dev = to_pci_dev(hwif->dev);
int reg = 0x44 + drive->dn * 4;
DBG(("%s(drive:%s)\n", __func__, drive->name));
pci_write_config_word(dev, reg,
(unsigned long)ide_get_drivedata(drive) >> 16);
@ -209,8 +197,6 @@ static void sl82c105_dma_clear(ide_drive_t *drive)
{
struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
DBG(("sl82c105_dma_clear(drive:%s)\n", drive->name));
sl82c105_reset_host(dev);
}
@ -218,11 +204,7 @@ static int sl82c105_dma_end(ide_drive_t *drive)
{
struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
int reg = 0x44 + drive->dn * 4;
int ret;
DBG(("%s(drive:%s)\n", __func__, drive->name));
ret = ide_dma_end(drive);
int ret = ide_dma_end(drive);
pci_write_config_word(dev, reg,
(unsigned long)ide_get_drivedata(drive));
@ -239,8 +221,6 @@ static void sl82c105_resetproc(ide_drive_t *drive)
struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
u32 val;
DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
pci_read_config_dword(dev, 0x40, &val);
val |= (CTRL_P1F16 | CTRL_P0F16);
pci_write_config_dword(dev, 0x40, val);
@ -291,8 +271,6 @@ static int init_chipset_sl82c105(struct pci_dev *dev)
{
u32 val;
DBG(("init_chipset_sl82c105()\n"));
pci_read_config_dword(dev, 0x40, &val);
val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
pci_write_config_dword(dev, 0x40, val);