forked from Minki/linux
ath9k_hw: optimize interrupt mask changes
OProfile showed that ath9k was spending way too much time in ath9k_hw_set_interrupts. Since most of the interrupt mask changes only need to globally enable/disable interrupts, it makes sense to split this part into separate functions, replacing all calls to ath9k_hw_set_interrupts(ah, 0) with ath9k_hw_disable_interrupts(ah). ath9k_hw_set_interrupts(ah, ah->imask) only gets changed to ath9k_hw_enable_interrupts(ah), whenever ah->imask was not changed since the point where interrupts were disabled. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
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790a11f268
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@ -503,7 +503,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
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/* Set the computed AP beacon timers */
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_disable_interrupts(ah);
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ath9k_beacon_init(sc, nexttbtt, intval);
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sc->beacon.bmisscnt = 0;
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ath9k_hw_set_interrupts(ah, ah->imask);
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@ -638,7 +638,7 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
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/* Set the computed STA beacon timers */
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_disable_interrupts(ah);
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ath9k_hw_set_sta_beacon_timers(ah, &bs);
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ah->imask |= ATH9K_INT_BMISS;
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ath9k_hw_set_interrupts(ah, ah->imask);
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@ -686,7 +686,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
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/* Set the computed ADHOC beacon timers */
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_disable_interrupts(ah);
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ath9k_beacon_init(sc, nexttbtt, intval);
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sc->beacon.bmisscnt = 0;
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ath9k_hw_set_interrupts(ah, ah->imask);
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@ -259,7 +259,7 @@ static void ath9k_gen_timer_start(struct ath_hw *ah,
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ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
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if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_disable_interrupts(ah);
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ah->imask |= ATH9K_INT_GENTIMER;
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ath9k_hw_set_interrupts(ah, ah->imask);
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}
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@ -273,7 +273,7 @@ static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
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/* if no timer is enabled, turn off interrupt mask */
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if (timer_table->timer_mask.val == 0) {
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_disable_interrupts(ah);
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ah->imask &= ~ATH9K_INT_GENTIMER;
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ath9k_hw_set_interrupts(ah, ah->imask);
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}
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@ -117,12 +117,11 @@ EXPORT_SYMBOL(ath9k_hw_numtxpending);
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bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
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{
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u32 txcfg, curLevel, newLevel;
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enum ath9k_int omask;
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if (ah->tx_trig_level >= ah->config.max_txtrig_level)
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return false;
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omask = ath9k_hw_set_interrupts(ah, ah->imask & ~ATH9K_INT_GLOBAL);
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ath9k_hw_disable_interrupts(ah);
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txcfg = REG_READ(ah, AR_TXCFG);
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curLevel = MS(txcfg, AR_FTRIG);
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@ -136,7 +135,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
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REG_WRITE(ah, AR_TXCFG,
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(txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
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ath9k_hw_set_interrupts(ah, omask);
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ath9k_hw_enable_interrupts(ah);
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ah->tx_trig_level = newLevel;
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@ -849,29 +848,60 @@ bool ath9k_hw_intrpend(struct ath_hw *ah)
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}
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EXPORT_SYMBOL(ath9k_hw_intrpend);
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enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
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enum ath9k_int ints)
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void ath9k_hw_disable_interrupts(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
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REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
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(void) REG_READ(ah, AR_IER);
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if (!AR_SREV_9100(ah)) {
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REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
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(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
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REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
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(void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
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}
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}
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EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
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void ath9k_hw_enable_interrupts(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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if (!(ah->imask & ATH9K_INT_GLOBAL))
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return;
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ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
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REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
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if (!AR_SREV_9100(ah)) {
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REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
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AR_INTR_MAC_IRQ);
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REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
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REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
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AR_INTR_SYNC_DEFAULT);
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REG_WRITE(ah, AR_INTR_SYNC_MASK,
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AR_INTR_SYNC_DEFAULT);
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}
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ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
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REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
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}
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EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
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void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
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{
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enum ath9k_int omask = ah->imask;
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u32 mask, mask2;
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struct ath9k_hw_capabilities *pCap = &ah->caps;
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struct ath_common *common = ath9k_hw_common(ah);
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if (!(ints & ATH9K_INT_GLOBAL))
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ath9k_hw_enable_interrupts(ah);
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ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
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if (omask & ATH9K_INT_GLOBAL) {
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ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
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REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
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(void) REG_READ(ah, AR_IER);
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if (!AR_SREV_9100(ah)) {
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REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
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(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
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REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
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(void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
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}
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}
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/* TODO: global int Ref count */
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mask = ints & ATH9K_INT_COMMON;
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mask2 = 0;
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@ -946,24 +976,8 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
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REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
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}
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if (ints & ATH9K_INT_GLOBAL) {
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ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
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REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
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if (!AR_SREV_9100(ah)) {
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REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
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AR_INTR_MAC_IRQ);
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REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
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ath9k_hw_enable_interrupts(ah);
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REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
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AR_INTR_SYNC_DEFAULT);
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REG_WRITE(ah, AR_INTR_SYNC_MASK,
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AR_INTR_SYNC_DEFAULT);
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}
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ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
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REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
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}
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return omask;
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return;
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}
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EXPORT_SYMBOL(ath9k_hw_set_interrupts);
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@ -669,6 +669,7 @@ enum ath9k_key_type {
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struct ath_hw;
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struct ath9k_channel;
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enum ath9k_int;
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u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
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void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
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@ -700,8 +701,9 @@ int ath9k_hw_beaconq_setup(struct ath_hw *ah);
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/* Interrupt Handling */
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bool ath9k_hw_intrpend(struct ath_hw *ah);
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enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
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enum ath9k_int ints);
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void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
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void ath9k_hw_enable_interrupts(struct ath_hw *ah);
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void ath9k_hw_disable_interrupts(struct ath_hw *ah);
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void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
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@ -239,7 +239,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
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* hardware at the new frequency, and then re-enable
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* the relevant bits of the h/w.
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*/
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_disable_interrupts(ah);
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ath_drain_all_txq(sc, false);
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spin_lock_bh(&sc->rx.pcu_lock);
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@ -653,7 +653,7 @@ void ath9k_tasklet(unsigned long data)
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ath_gen_timer_isr(sc->sc_ah);
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/* re-enable hardware interrupt */
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ath9k_hw_set_interrupts(ah, ah->imask);
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ath9k_hw_enable_interrupts(ah);
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ath9k_ps_restore(sc);
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}
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@ -752,7 +752,7 @@ irqreturn_t ath_isr(int irq, void *dev)
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* interrupt; otherwise it will continue to
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* fire.
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*/
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_disable_interrupts(ah);
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/*
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* Let the hal handle the event. We assume
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* it will clear whatever condition caused
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@ -761,7 +761,7 @@ irqreturn_t ath_isr(int irq, void *dev)
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spin_lock(&common->cc_lock);
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ath9k_hw_proc_mib_event(ah);
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spin_unlock(&common->cc_lock);
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ath9k_hw_set_interrupts(ah, ah->imask);
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ath9k_hw_enable_interrupts(ah);
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}
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if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
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@ -778,8 +778,8 @@ chip_reset:
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ath_debug_stat_interrupt(sc, status);
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if (sched) {
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/* turn off every interrupt except SWBA */
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ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
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/* turn off every interrupt */
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ath9k_hw_disable_interrupts(ah);
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tasklet_schedule(&sc->intr_tq);
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}
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@ -937,7 +937,7 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
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}
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/* Disable interrupts */
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_disable_interrupts(ah);
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ath_drain_all_txq(sc, false); /* clear pending tx frames */
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@ -980,7 +980,7 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
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ieee80211_stop_queues(hw);
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_disable_interrupts(ah);
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ath_drain_all_txq(sc, retry_tx);
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spin_lock_bh(&sc->rx.pcu_lock);
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@ -1394,7 +1394,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
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/* make sure h/w will not generate any interrupt
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* before setting the invalid flag. */
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_disable_interrupts(ah);
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spin_lock_bh(&sc->rx.pcu_lock);
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if (!(sc->sc_flags & SC_OP_INVALID)) {
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