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Merge branches 'clk-socfpga', 'clk-mstar', 'clk-qcom' and 'clk-warnings' into clk-next

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- PLL support on MStar/SigmaStar ARMv7 SoCs
 - CPU clks for Qualcomm SDX55
 - GCC and RPMh clks for Qualcomm SC8180x and SC7280 SoCs
 - GCC clks for Qualcomm SM8350
 - Video clk fixups on Qualcomm SM8250
 - GPU clks for Qualcomm SDM660/SDM630
 - Improvements for multimedia clks on Qualcomm MSM8998
 - Fix many warnings with W=1 enabled builds under drivers/clk/

* clk-socfpga:
  clk: socfpga: agilex: add clock driver for eASIC N5X platform
  dt-bindings: documentation: add clock bindings information for eASIC N5X

* clk-mstar:
  clk: mstar: msc313-mpll: Fix format specifier
  clk: mstar: Allow MStar clk drivers to be compile tested
  clk: mstar: MStar/SigmaStar MPLL driver
  clk: fixed: add devm helper for clk_hw_register_fixed_factor()
  dt-bindings: clk: mstar msc313 mpll binding description
  dt-bindings: clk: mstar msc313 mpll binding header

* clk-qcom: (42 commits)
  clk: qcom: Add Global Clock controller (GCC) driver for SC7280
  dt-bindings: clock: Add SC7280 GCC clock binding
  clk: qcom: rpmh: Add support for RPMH clocks on SC7280
  dt-bindings: clock: Add RPMHCC bindings for SC7280
  clk: qcom: gcc-sm8350: add gdsc
  dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings
  clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver
  clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d
  clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers
  dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc
  clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver
  clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical
  clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical
  clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting
  clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc
  clk: qcom: gdsc: Implement NO_RET_PERIPH flag
  clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on
  clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks
  clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs
  clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as critical
  ...

* clk-warnings: (27 commits)
  clk: zynq: clkc: Remove various instances of an unused variable 'clk'
  clk: versatile: clk-icst: Fix worthy struct documentation block
  clk: ti: gate: Fix possible doc-rot in 'omap36xx_gate_clk_enable_with_hsdiv_restore'
  clk: ti: dpll: Fix misnaming of '_register_dpll()'s 'user' parameter
  clk: ti: clockdomain: Fix description for 'omap2_init_clk_clkdm's hw param
  clk: st: clkgen-fsyn: Fix worthy struct documentation demote partially filled one
  clk: st: clkgen-pll: Demote unpopulated kernel-doc header
  clk: mvebu: ap-cpu-clk: Demote non-conformant kernel-doc header
  clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc'
  clk: socfpga: clk-pll: Remove unused variable 'rc'
  clk: sifive: fu540-prci: Declare static const variable 'prci_clk_fu540' where it's used
  clk: bcm: clk-iproc-pll: Demote kernel-doc abuse
  clk: zynqmp: divider: Add missing description for 'max_div'
  clk: spear: Move prototype to accessible header
  clk: qcom: clk-rpm: Remove a bunch of superfluous code
  clk: clk-xgene: Add description for 'mask' and fix formatting for 'flags'
  clk: qcom: mmcc-msm8974: Remove unused static const tables 'mmcc_xo_mmpll0_1_2_gpll0{map}'
  clk: clk-npcm7xx: Remove unused static const tables 'npcm7xx_gates' and 'npcm7xx_divs_fx'
  clk: clk-fixed-mmio: Demote obvious kernel-doc abuse
  clk: qcom: gcc-ipq4019: Remove unused variable 'ret'
  ...
This commit is contained in:
Stephen Boyd 2021-02-16 14:09:24 -08:00
commit 4d5c4ae329
85 changed files with 18208 additions and 451 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
Documentation/devicetree/bindings/clock/intel,easic-n5x.yaml Normal file
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@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/intel,easic-n5x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel SoCFPGA eASIC N5X platform clock controller binding
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
description:
The Intel eASIC N5X Clock controller is an integrated clock controller, which
generates and supplies to all modules.
properties:
compatible:
const: intel,easic-n5x-clkmgr
'#clock-cells':
const: 1
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
# Clock controller node:
- |
clkmgr: clock-controller@ffd10000 {
compatible = "intel,easic-n5x-clkmgr";
reg = <0xffd10000 0x1000>;
clocks = <&osc1>;
#clock-cells = <1>;
};
...

46
Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml Normal file
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@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MStar/Sigmastar MSC313 MPLL
maintainers:
- Daniel Palmer <daniel@thingy.jp>
description: |
The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that
takes the external xtal input and multiplies it to create a high
frequency clock and divides that down into a number of clocks that
peripherals use.
properties:
compatible:
const: mstar,msc313-mpll
"#clock-cells":
const: 1
clocks:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- "#clock-cells"
- clocks
- reg
additionalProperties: false
examples:
- |
mpll@206000 {
compatible = "mstar,msc313-mpll";
reg = <0x206000 0x200>;
#clock-cells = <1>;
clocks = <&xtal>;
};

51
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml Normal file
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@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm A7 PLL Binding
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
frequency clock to the CPU.
properties:
compatible:
enum:
- qcom,sdx55-a7pll
reg:
maxItems: 1
'#clock-cells':
const: 0
clocks:
items:
- description: board XO clock
clock-names:
items:
- const: bi_tcxo
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
a7pll: clock@17808000 {
compatible = "qcom,sdx55-a7pll";
reg = <0x17808000 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <0>;
};

92
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml Normal file
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@ -0,0 +1,92 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SC7280.
See also:
- dt-bindings/clock/qcom,gcc-sc7280.h
properties:
compatible:
const: qcom,gcc-sc7280
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
- description: PCIE-0 pipe clock source
- description: PCIE-1 pipe clock source
- description: USF phy rx symbol 0 clock source
- description: USF phy rx symbol 1 clock source
- description: USF phy tx symbol 0 clock source
- description: USB30 phy wrapper pipe clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
- const: pcie_0_pipe_clk
- const: pcie_1_pipe_clk
- const: ufs_phy_rx_symbol_0_clk
- const: ufs_phy_rx_symbol_1_clk
- const: ufs_phy_tx_symbol_0_clk
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,gcc-sc7280";
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
<&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk",
"pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

76
Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml Normal file
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@ -0,0 +1,76 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8180x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SC8180x
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SC8180x.
See also:
- dt-bindings/clock/qcom,gcc-sc8180x.h
properties:
compatible:
const: qcom,gcc-sc8180x
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,gcc-sc8180x";
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

96
Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml Normal file
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@ -0,0 +1,96 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM8350
maintainers:
- Vinod Koul <vkoul@kernel.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM8350.
See also:
- dt-bindings/clock/qcom,gcc-sm8350.h
properties:
compatible:
const: qcom,gcc-sm8350
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PLL test clock source (Optional clock)
- description: PCIE 0 Pipe clock source (Optional clock)
- description: PCIE 1 Pipe clock source (Optional clock)
- description: UFS card Rx symbol 0 clock source (Optional clock)
- description: UFS card Rx symbol 1 clock source (Optional clock)
- description: UFS card Tx symbol 0 clock source (Optional clock)
- description: UFS phy Rx symbol 0 clock source (Optional clock)
- description: UFS phy Rx symbol 1 clock source (Optional clock)
- description: UFS phy Tx symbol 0 clock source (Optional clock)
- description: USB3 phy wrapper pipe clock source (Optional clock)
- description: USB3 phy sec pipe clock source (Optional clock)
minItems: 2
maxItems: 13
clock-names:
items:
- const: bi_tcxo
- const: sleep_clk
- const: core_bi_pll_test_se # Optional clock
- const: pcie_0_pipe_clk # Optional clock
- const: pcie_1_pipe_clk # Optional clock
- const: ufs_card_rx_symbol_0_clk # Optional clock
- const: ufs_card_rx_symbol_1_clk # Optional clock
- const: ufs_card_tx_symbol_0_clk # Optional clock
- const: ufs_phy_rx_symbol_0_clk # Optional clock
- const: ufs_phy_rx_symbol_1_clk # Optional clock
- const: ufs_phy_tx_symbol_0_clk # Optional clock
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
- const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
minItems: 2
maxItems: 13
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,gcc-sm8350";
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

76
Documentation/devicetree/bindings/clock/qcom,gpucc-sdm660.yaml Normal file
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@ -0,0 +1,76 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller Binding for SDM630 and SDM660
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
power domains on SDM630 and SDM660.
See also dt-bindings/clock/qcom,gpucc-sdm660.h.
properties:
compatible:
enum:
- qcom,gpucc-sdm630
- qcom,gpucc-sdm660
clocks:
items:
- description: Board XO source
- description: GPLL0 main gpu branch
- description: GPLL0 divider gpu branch
clock-names:
items:
- const: xo
- const: gcc_gpu_gpll0_clk
- const: gcc_gpu_gpll0_div_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm660.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
clock-controller@5065000 {
compatible = "qcom,gpucc-sdm660";
reg = <0x05065000 0x9038>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_CLK>,
<&gcc GCC_GPU_GPLL0_DIV_CLK>;
clock-names = "xo", "gcc_gpu_gpll0_clk",
"gcc_gpu_gpll0_div_clk";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...

2
Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
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@ -24,6 +24,8 @@ properties:
- qcom,mmcc-msm8974
- qcom,mmcc-msm8996
- qcom,mmcc-msm8998
- qcom,mmcc-sdm630
- qcom,mmcc-sdm660
clocks:
items:

2
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View File

@ -18,6 +18,8 @@ properties:
compatible:
enum:
- qcom,sc7180-rpmh-clk
- qcom,sc7280-rpmh-clk
- qcom,sc8180x-rpmh-clk
- qcom,sdm845-rpmh-clk
- qcom,sdx55-rpmh-clk
- qcom,sm8150-rpmh-clk

3
MAINTAINERS
View File

@ -2146,10 +2146,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
W: http://linux-chenxing.org/
F: Documentation/devicetree/bindings/arm/mstar/*
F: Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml
F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml
F: arch/arm/boot/dts/mstar-*
F: arch/arm/mach-mstar/
F: drivers/clk/mstar/
F: drivers/gpio/gpio-msc313.c
F: include/dt-bindings/clock/mstar-*
F: include/dt-bindings/gpio/msc313-gpio.h
ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT

12
arch/arm/mach-spear/generic.h
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@ -43,16 +43,4 @@ void spear13xx_cpu_die(unsigned int cpu);
extern const struct smp_operations spear13xx_smp_ops;
#ifdef CONFIG_MACH_SPEAR1310
void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base);
#else
static inline void spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) {}
#endif
#ifdef CONFIG_MACH_SPEAR1340
void __init spear1340_clk_init(void __iomem *misc_base);
#else
static inline void spear1340_clk_init(void __iomem *misc_base) {}
#endif
#endif /* __MACH_GENERIC_H */

1
arch/arm/mach-spear/spear13xx.c
View File

@ -15,6 +15,7 @@
#include <linux/amba/pl022.h>
#include <linux/clk.h>
#include <linux/clk/spear.h>
#include <linux/clocksource.h>
#include <linux/err.h>
#include <linux/of.h>

1
drivers/clk/Kconfig
View File

@ -380,6 +380,7 @@ source "drivers/clk/ingenic/Kconfig"
source "drivers/clk/keystone/Kconfig"
source "drivers/clk/mediatek/Kconfig"
source "drivers/clk/meson/Kconfig"
source "drivers/clk/mstar/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/qcom/Kconfig"
source "drivers/clk/renesas/Kconfig"

1
drivers/clk/Makefile
View File

@ -92,6 +92,7 @@ obj-$(CONFIG_MACH_PIC32) += microchip/
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP) += mmp/
endif
obj-y += mstar/
obj-y += mvebu/
obj-$(CONFIG_ARCH_MXS) += mxs/
obj-$(CONFIG_COMMON_CLK_NXP) += nxp/

2
drivers/clk/bcm/clk-iproc-pll.c
View File

@ -704,7 +704,7 @@ static const struct clk_ops iproc_clk_ops = {
.set_rate = iproc_clk_set_rate,
};
/**
/*
* Some PLLs require the PLL SW override bit to be set before changes can be
* applied to the PLL
*/

39
drivers/clk/clk-fixed-factor.c
View File

@ -64,10 +64,16 @@ const struct clk_ops clk_fixed_factor_ops = {
};
EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void *res)
{
clk_hw_unregister_fixed_factor(&((struct clk_fixed_factor *)res)->hw);
}
static struct clk_hw *
__clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
const char *name, const char *parent_name, int index,
unsigned long flags, unsigned int mult, unsigned int div)
unsigned long flags, unsigned int mult, unsigned int div,
bool devm)
{
struct clk_fixed_factor *fix;
struct clk_init_data init = { };
@ -75,7 +81,15 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
struct clk_hw *hw;
int ret;
fix = kmalloc(sizeof(*fix), GFP_KERNEL);
/* You can't use devm without a dev */
if (devm && !dev)
return ERR_PTR(-EINVAL);
if (devm)
fix = devres_alloc(devm_clk_hw_register_fixed_factor_release,
sizeof(*fix), GFP_KERNEL);
else
fix = kmalloc(sizeof(*fix), GFP_KERNEL);
if (!fix)
return ERR_PTR(-ENOMEM);
@ -99,9 +113,13 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
else
ret = of_clk_hw_register(np, hw);
if (ret) {
kfree(fix);
if (devm)
devres_free(fix);
else
kfree(fix);
hw = ERR_PTR(ret);
}
} else if (devm)
devres_add(dev, fix);
return hw;
}
@ -111,7 +129,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
unsigned int mult, unsigned int div)
{
return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
flags, mult, div);
flags, mult, div, false);
}
EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
@ -153,6 +171,15 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw)
}
EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);
struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div)
{
return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
flags, mult, div, true);
}
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
#ifdef CONFIG_OF
static const struct of_device_id set_rate_parent_matches[] = {
{ .compatible = "allwinner,sun4i-a10-pll3-2x-clk" },
@ -185,7 +212,7 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)
flags |= CLK_SET_RATE_PARENT;
hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0,
flags, mult, div);
flags, mult, div, false);
if (IS_ERR(hw)) {
/*
* Clear OF_POPULATED flag so that clock registration can be

2
drivers/clk/clk-fixed-mmio.c
View File

@ -55,7 +55,7 @@ static void __init of_fixed_mmio_clk_setup(struct device_node *node)
}
CLK_OF_DECLARE(fixed_mmio_clk, "fixed-mmio-clock", of_fixed_mmio_clk_setup);
/**
/*
* This is not executed when of_fixed_mmio_clk_setup succeeded.
*/
static int of_fixed_mmio_clk_probe(struct platform_device *pdev)

108
drivers/clk/clk-npcm7xx.c
View File

@ -361,13 +361,6 @@ static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = {
dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
};
/* fixed ratio dividers (no register): */
static const struct npcm7xx_clk_div_fixed_data npcm7xx_divs_fx[] __initconst = {
{ 1, 2, NPCM7XX_CLK_S_MC, NPCM7XX_CLK_S_MC_MUX, 0, NPCM7XX_CLK_MC},
{ 1, 2, NPCM7XX_CLK_S_PLL1_DIV2, NPCM7XX_CLK_S_PLL1, 0, -1},
{ 1, 2, NPCM7XX_CLK_S_PLL2_DIV2, NPCM7XX_CLK_S_PLL2, 0, -1},
};
/* configurable dividers: */
static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = {
{NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC,
@ -435,107 +428,6 @@ static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = {
};
static const struct npcm7xx_clk_gate_data npcm7xx_gates[] __initconst = {
{NPCM7XX_CLKEN1, 31, "smb1-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN1, 30, "smb0-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN1, 29, "smb7-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN1, 28, "smb6-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN1, 27, "adc-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN1, 26, "wdt-gate", NPCM7XX_CLK_S_TIMER, 0},
{NPCM7XX_CLKEN1, 25, "usbdev3-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN1, 24, "usbdev6-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN1, 23, "usbdev5-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN1, 22, "usbdev4-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN1, 21, "emc2-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN1, 20, "timer5_9-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN1, 19, "timer0_4-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN1, 18, "pwmm0-gate", NPCM7XX_CLK_S_APB3, 0},
{NPCM7XX_CLKEN1, 17, "huart-gate", NPCM7XX_CLK_S_UART, 0},
{NPCM7XX_CLKEN1, 16, "smb5-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN1, 15, "smb4-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN1, 14, "smb3-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN1, 13, "smb2-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN1, 12, "mc-gate", NPCM7XX_CLK_S_MC, 0},
{NPCM7XX_CLKEN1, 11, "uart01-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN1, 10, "aes-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN1, 9, "peci-gate", NPCM7XX_CLK_S_APB3, 0},
{NPCM7XX_CLKEN1, 8, "usbdev2-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN1, 7, "uart23-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN1, 6, "emc1-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN1, 5, "usbdev1-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN1, 4, "shm-gate", NPCM7XX_CLK_S_AHB, 0},
/* bit 3 is reserved */
{NPCM7XX_CLKEN1, 2, "kcs-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN1, 1, "spi3-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN1, 0, "spi0-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN2, 31, "cp-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN2, 30, "tock-gate", NPCM7XX_CLK_S_TOCK, 0},
/* bit 29 is reserved */
{NPCM7XX_CLKEN2, 28, "gmac1-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN2, 27, "usbif-gate", NPCM7XX_CLK_S_USBIF, 0},
{NPCM7XX_CLKEN2, 26, "usbhost-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN2, 25, "gmac2-gate", NPCM7XX_CLK_S_AHB, 0},
/* bit 24 is reserved */
{NPCM7XX_CLKEN2, 23, "pspi2-gate", NPCM7XX_CLK_S_APB5, 0},
{NPCM7XX_CLKEN2, 22, "pspi1-gate", NPCM7XX_CLK_S_APB5, 0},
{NPCM7XX_CLKEN2, 21, "3des-gate", NPCM7XX_CLK_S_AHB, 0},
/* bit 20 is reserved */
{NPCM7XX_CLKEN2, 19, "siox2-gate", NPCM7XX_CLK_S_APB3, 0},
{NPCM7XX_CLKEN2, 18, "siox1-gate", NPCM7XX_CLK_S_APB3, 0},
/* bit 17 is reserved */
{NPCM7XX_CLKEN2, 16, "fuse-gate", NPCM7XX_CLK_S_APB4, 0},
/* bit 15 is reserved */
{NPCM7XX_CLKEN2, 14, "vcd-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN2, 13, "ece-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN2, 12, "vdma-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN2, 10, "gfxsys-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN2, 9, "sdhc-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN2, 8, "mmc-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN2, 7, "mft7-gate", NPCM7XX_CLK_S_APB4, 0},
{NPCM7XX_CLKEN2, 6, "mft6-gate", NPCM7XX_CLK_S_APB4, 0},
{NPCM7XX_CLKEN2, 5, "mft5-gate", NPCM7XX_CLK_S_APB4, 0},
{NPCM7XX_CLKEN2, 4, "mft4-gate", NPCM7XX_CLK_S_APB4, 0},
{NPCM7XX_CLKEN2, 3, "mft3-gate", NPCM7XX_CLK_S_APB4, 0},
{NPCM7XX_CLKEN2, 2, "mft2-gate", NPCM7XX_CLK_S_APB4, 0},
{NPCM7XX_CLKEN2, 1, "mft1-gate", NPCM7XX_CLK_S_APB4, 0},
{NPCM7XX_CLKEN2, 0, "mft0-gate", NPCM7XX_CLK_S_APB4, 0},
{NPCM7XX_CLKEN3, 31, "gpiom7-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN3, 30, "gpiom6-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN3, 29, "gpiom5-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN3, 28, "gpiom4-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN3, 27, "gpiom3-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN3, 26, "gpiom2-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN3, 25, "gpiom1-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN3, 24, "gpiom0-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN3, 23, "espi-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN3, 22, "smb11-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN3, 21, "smb10-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN3, 20, "smb9-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN3, 19, "smb8-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN3, 18, "smb15-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN3, 17, "rng-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN3, 16, "timer10_14-gate", NPCM7XX_CLK_S_APB1, 0},
{NPCM7XX_CLKEN3, 15, "pcirc-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN3, 14, "sececc-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN3, 13, "sha-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN3, 12, "smb14-gate", NPCM7XX_CLK_S_APB2, 0},
/* bit 11 is reserved */
/* bit 10 is reserved */
{NPCM7XX_CLKEN3, 9, "pcimbx-gate", NPCM7XX_CLK_S_AHB, 0},
/* bit 8 is reserved */
{NPCM7XX_CLKEN3, 7, "usbdev9-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN3, 6, "usbdev8-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN3, 5, "usbdev7-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN3, 4, "usbdev0-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN3, 3, "smb13-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN3, 2, "spix-gate", NPCM7XX_CLK_S_AHB, 0},
{NPCM7XX_CLKEN3, 1, "smb12-gate", NPCM7XX_CLK_S_APB2, 0},
{NPCM7XX_CLKEN3, 0, "pwmm1-gate", NPCM7XX_CLK_S_APB3, 0},
};
static DEFINE_SPINLOCK(npcm7xx_clk_lock);
static void __init npcm7xx_clk_init(struct device_node *clk_np)

5
drivers/clk/clk-xgene.c
View File

@ -206,17 +206,16 @@ static void xgene_pcppllclk_init(struct device_node *np)
* @hw: handle between common and hardware-specific interfaces
* @reg: register containing the fractional scale multiplier (scaler)
* @shift: shift to the unit bit field
* @mask: mask to the unit bit field
* @denom: 1/denominator unit
* @lock: register lock
* Flags:
* XGENE_CLK_PMD_SCALE_INVERTED - By default the scaler is the value read
* @flags: XGENE_CLK_PMD_SCALE_INVERTED - By default the scaler is the value read
* from the register plus one. For example,
* 0 for (0 + 1) / denom,
* 1 for (1 + 1) / denom and etc.
* If this flag is set, it is
* 0 for (denom - 0) / denom,
* 1 for (denom - 1) / denom and etc.
*
*/
struct xgene_clk_pmd {
struct clk_hw hw;

9
drivers/clk/mstar/Kconfig Normal file
View File

@ -0,0 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-only
config MSTAR_MSC313_MPLL
bool "MStar MPLL driver"
depends on ARCH_MSTARV7 || COMPILE_TEST
default ARCH_MSTARV7
select REGMAP_MMIO
help
Support for the MPLL PLL and dividers block present on
MStar/Sigmastar SoCs.

6
drivers/clk/mstar/Makefile Normal file
View File

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for mstar specific clk
#
obj-$(CONFIG_MSTAR_MSC313_MPLL) += clk-msc313-mpll.o

155
drivers/clk/mstar/clk-msc313-mpll.c Normal file
View File

@ -0,0 +1,155 @@
// SPDX-License-Identifier: GPL-2.0
/*
* MStar MSC313 MPLL driver
*
* Copyright (C) 2020 Daniel Palmer <daniel@thingy.jp>
*/
#include <linux/platform_device.h>
#include <linux/of_address.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#define REG_CONFIG1 0x8
#define REG_CONFIG2 0xc
static const struct regmap_config msc313_mpll_regmap_config = {
.reg_bits = 16,
.val_bits = 16,
.reg_stride = 4,
};
static const struct reg_field config1_loop_div_first = REG_FIELD(REG_CONFIG1, 8, 9);
static const struct reg_field config1_input_div_first = REG_FIELD(REG_CONFIG1, 4, 5);
static const struct reg_field config2_output_div_first = REG_FIELD(REG_CONFIG2, 12, 13);
static const struct reg_field config2_loop_div_second = REG_FIELD(REG_CONFIG2, 0, 7);
static const unsigned int output_dividers[] = {
2, 3, 4, 5, 6, 7, 10
};
#define NUMOUTPUTS (ARRAY_SIZE(output_dividers) + 1)
struct msc313_mpll {
struct clk_hw clk_hw;
struct regmap_field *input_div;
struct regmap_field *loop_div_first;
struct regmap_field *loop_div_second;
struct regmap_field *output_div;
struct clk_hw_onecell_data *clk_data;
};
#define to_mpll(_hw) container_of(_hw, struct msc313_mpll, clk_hw)
static unsigned long msc313_mpll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct msc313_mpll *mpll = to_mpll(hw);
unsigned int input_div, output_div, loop_first, loop_second;
unsigned long output_rate;
regmap_field_read(mpll->input_div, &input_div);
regmap_field_read(mpll->output_div, &output_div);
regmap_field_read(mpll->loop_div_first, &loop_first);
regmap_field_read(mpll->loop_div_second, &loop_second);
output_rate = parent_rate / (1 << input_div);
output_rate *= (1 << loop_first) * max(loop_second, 1U);
output_rate /= max(output_div, 1U);
return output_rate;
}
static const struct clk_ops msc313_mpll_ops = {
.recalc_rate = msc313_mpll_recalc_rate,
};
static const struct clk_parent_data mpll_parent = {
.index = 0,
};
static int msc313_mpll_probe(struct platform_device *pdev)
{
void __iomem *base;
struct msc313_mpll *mpll;
struct clk_init_data clk_init = { };
struct device *dev = &pdev->dev;
struct regmap *regmap;
char *outputname;
struct clk_hw *divhw;
int ret, i;
mpll = devm_kzalloc(dev, sizeof(*mpll), GFP_KERNEL);
if (!mpll)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, &msc313_mpll_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
mpll->input_div = devm_regmap_field_alloc(dev, regmap, config1_input_div_first);
if (IS_ERR(mpll->input_div))
return PTR_ERR(mpll->input_div);
mpll->output_div = devm_regmap_field_alloc(dev, regmap, config2_output_div_first);
if (IS_ERR(mpll->output_div))
return PTR_ERR(mpll->output_div);
mpll->loop_div_first = devm_regmap_field_alloc(dev, regmap, config1_loop_div_first);
if (IS_ERR(mpll->loop_div_first))
return PTR_ERR(mpll->loop_div_first);
mpll->loop_div_second = devm_regmap_field_alloc(dev, regmap, config2_loop_div_second);
if (IS_ERR(mpll->loop_div_second))
return PTR_ERR(mpll->loop_div_second);
mpll->clk_data = devm_kzalloc(dev, struct_size(mpll->clk_data, hws,
ARRAY_SIZE(output_dividers)), GFP_KERNEL);
if (!mpll->clk_data)
return -ENOMEM;
clk_init.name = dev_name(dev);
clk_init.ops = &msc313_mpll_ops;
clk_init.parent_data = &mpll_parent;
clk_init.num_parents = 1;
mpll->clk_hw.init = &clk_init;
ret = devm_clk_hw_register(dev, &mpll->clk_hw);
if (ret)
return ret;
mpll->clk_data->num = NUMOUTPUTS;
mpll->clk_data->hws[0] = &mpll->clk_hw;
for (i = 0; i < ARRAY_SIZE(output_dividers); i++) {
outputname = devm_kasprintf(dev, GFP_KERNEL, "%s_div_%u",
clk_init.name, output_dividers[i]);
if (!outputname)
return -ENOMEM;
divhw = devm_clk_hw_register_fixed_factor(dev, outputname,
clk_init.name, 0, 1, output_dividers[i]);
if (IS_ERR(divhw))
return PTR_ERR(divhw);
mpll->clk_data->hws[i + 1] = divhw;
}
platform_set_drvdata(pdev, mpll);
return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
mpll->clk_data);
}
static const struct of_device_id msc313_mpll_of_match[] = {
{ .compatible = "mstar,msc313-mpll", },
{}
};
static struct platform_driver msc313_mpll_driver = {
.driver = {
.name = "mstar-msc313-mpll",
.of_match_table = msc313_mpll_of_match,
},
.probe = msc313_mpll_probe,
};
builtin_platform_driver(msc313_mpll_driver);

2
drivers/clk/mvebu/ap-cpu-clk.c
View File

@ -30,7 +30,7 @@
#define APN806_MAX_DIVIDER 32
/**
/*
* struct cpu_dfs_regs: CPU DFS register mapping
* @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
* @force_reg: request to force new ratio regardless of relation to other clocks

61
drivers/clk/qcom/Kconfig
View File

@ -28,6 +28,14 @@ config QCOM_A53PLL
Say Y if you want to support higher CPU frequencies on MSM8916
devices.
config QCOM_A7PLL
tristate "SDX55 A7 PLL"
help
Support for the A7 PLL on SDX55 devices. It provides the CPU with
frequencies above 1GHz.
Say Y if you want to support higher CPU frequencies on SDX55
devices.
config QCOM_CLK_APCS_MSM8916
tristate "MSM8916 APCS Clock Controller"
depends on QCOM_APCS_IPC || COMPILE_TEST
@ -46,6 +54,15 @@ config QCOM_CLK_APCC_MSM8996
Say Y if you want to support CPU clock scaling using CPUfreq
drivers for dynamic power management.
config QCOM_CLK_APCS_SDX55
tristate "SDX55 APCS Clock Controller"
depends on QCOM_APCS_IPC || COMPILE_TEST
help
Support for the APCS Clock Controller on SDX55 platform. The
APCS is managing the mux and divider which feeds the CPUs.
Say Y if you want to support CPU frequency scaling on devices
such as SDX55.
config QCOM_CLK_RPM
tristate "RPM based Clock Controller"
depends on MFD_QCOM_RPM
@ -317,6 +334,24 @@ config SC_GCC_7180
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, UFS, SDCC, etc.
config SC_GCC_7280
tristate "SC7280 Global Clock Controller"
select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on SC7280 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, UFS, SDCC, PCIe etc.
config SC_GCC_8180X
tristate "SC8180X Global Clock Controller"
select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on SC8180X devices.
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, UFS, SDCC, etc.
config SC_LPASS_CORECC_7180
tristate "SC7180 LPASS Core Clock Controller"
select SC_GCC_7180
@ -366,6 +401,24 @@ config SDM_GCC_660
Say Y if you want to use peripheral devices such as UART, SPI,
i2C, USB, UFS, SDDC, PCIe, etc.
config SDM_MMCC_660
tristate "SDM660 Multimedia Clock Controller"
select SDM_GCC_660
select QCOM_GDSC
help
Support for the multimedia clock controller on SDM660 devices.
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
config SDM_GPUCC_660
tristate "SDM660 Graphics Clock Controller"
select SDM_GCC_660
select QCOM_GDSC
help
Support for the graphics clock controller on SDM630/636/660 devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics
config QCS_TURING_404
tristate "QCS404 Turing Clock Controller"
help
@ -454,6 +507,14 @@ config SM_GCC_8250
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GCC_8350
tristate "SM8350 Global Clock Controller"
select QCOM_GDSC
help
Support for the global clock controller on SM8350 devices.
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GPUCC_8150
tristate "SM8150 Graphics Clock Controller"
select SM_GCC_8150

7
drivers/clk/qcom/Makefile
View File

@ -44,8 +44,10 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
obj-$(CONFIG_MSM_MMCC_8998) += mmcc-msm8998.o
obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
obj-$(CONFIG_QCOM_A7PLL) += a7-pll.o
obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o
obj-$(CONFIG_QCOM_CLK_APCS_SDX55) += apcs-sdx55.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
@ -55,6 +57,8 @@ obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
obj-$(CONFIG_SC_CAMCC_7180) += camcc-sc7180.o
obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o
obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o
obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o
obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o
@ -62,6 +66,8 @@ obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o
obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
obj-$(CONFIG_SDM_MMCC_660) += mmcc-sdm660.o
obj-$(CONFIG_SDM_GPUCC_660) += gpucc-sdm660.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
@ -70,6 +76,7 @@ obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o

100
drivers/clk/qcom/a7-pll.c Normal file
View File

@ -0,0 +1,100 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Qualcomm A7 PLL driver
*
* Copyright (c) 2020, Linaro Limited
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "clk-alpha-pll.h"
#define LUCID_PLL_OFF_L_VAL 0x04
static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct clk_alpha_pll a7pll = {
.offset = 0x100,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "a7pll",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct alpha_pll_config a7pll_config = {
.l = 0x39,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x2261,
.config_ctl_hi1_val = 0x029A699C,
.user_ctl_val = 0x1,
.user_ctl_hi_val = 0x805,
};
static const struct regmap_config a7pll_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1000,
.fast_io = true,
};
static int qcom_a7pll_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct regmap *regmap;
void __iomem *base;
u32 l_val;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, &a7pll_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Configure PLL only if the l_val is zero */
regmap_read(regmap, a7pll.offset + LUCID_PLL_OFF_L_VAL, &l_val);
if (!l_val)
clk_lucid_pll_configure(&a7pll, regmap, &a7pll_config);
ret = devm_clk_register_regmap(dev, &a7pll.clkr);
if (ret)
return ret;
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
&a7pll.clkr.hw);
}
static const struct of_device_id qcom_a7pll_match_table[] = {
{ .compatible = "qcom,sdx55-a7pll" },
{ }
};
static struct platform_driver qcom_a7pll_driver = {
.probe = qcom_a7pll_probe,
.driver = {
.name = "qcom-a7pll",
.of_match_table = qcom_a7pll_match_table,
},
};
module_platform_driver(qcom_a7pll_driver);
MODULE_DESCRIPTION("Qualcomm A7 PLL Driver");
MODULE_LICENSE("GPL v2");

149
drivers/clk/qcom/apcs-sdx55.c Normal file
View File

@ -0,0 +1,149 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Qualcomm SDX55 APCS clock controller driver
*
* Copyright (c) 2020, Linaro Limited
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/cpu.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "clk-regmap.h"
#include "clk-regmap-mux-div.h"
static const u32 apcs_mux_clk_parent_map[] = { 0, 1, 5 };
static const struct clk_parent_data pdata[] = {
{ .fw_name = "ref" },
{ .fw_name = "aux" },
{ .fw_name = "pll" },
};
/*
* We use the notifier function for switching to a temporary safe configuration
* (mux and divider), while the A7 PLL is reconfigured.
*/
static int a7cc_notifier_cb(struct notifier_block *nb, unsigned long event,
void *data)
{
int ret = 0;
struct clk_regmap_mux_div *md = container_of(nb,
struct clk_regmap_mux_div,
clk_nb);
if (event == PRE_RATE_CHANGE)
/* set the mux and divider to safe frequency (400mhz) */
ret = mux_div_set_src_div(md, 1, 2);
return notifier_from_errno(ret);
}
static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device *parent = dev->parent;
struct device *cpu_dev;
struct clk_regmap_mux_div *a7cc;
struct regmap *regmap;
struct clk_init_data init = { };
int ret;
regmap = dev_get_regmap(parent, NULL);
if (!regmap) {
dev_err_probe(dev, -ENODEV, "Failed to get parent regmap\n");
return -ENODEV;
}
a7cc = devm_kzalloc(dev, sizeof(*a7cc), GFP_KERNEL);
if (!a7cc)
return -ENOMEM;
init.name = "a7mux";
init.parent_data = pdata;
init.num_parents = ARRAY_SIZE(pdata);
init.ops = &clk_regmap_mux_div_ops;
a7cc->clkr.hw.init = &init;
a7cc->clkr.regmap = regmap;
a7cc->reg_offset = 0x8;
a7cc->hid_width = 5;
a7cc->hid_shift = 0;
a7cc->src_width = 3;
a7cc->src_shift = 8;
a7cc->parent_map = apcs_mux_clk_parent_map;
a7cc->pclk = devm_clk_get(parent, "pll");
if (IS_ERR(a7cc->pclk)) {
ret = PTR_ERR(a7cc->pclk);
if (ret != -EPROBE_DEFER)
dev_err_probe(dev, ret, "Failed to get PLL clk\n");
return ret;
}
a7cc->clk_nb.notifier_call = a7cc_notifier_cb;
ret = clk_notifier_register(a7cc->pclk, &a7cc->clk_nb);
if (ret) {
dev_err_probe(dev, ret, "Failed to register clock notifier\n");
return ret;
}
ret = devm_clk_register_regmap(dev, &a7cc->clkr);
if (ret) {
dev_err_probe(dev, ret, "Failed to register regmap clock\n");
goto err;
}
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
&a7cc->clkr.hw);
if (ret) {
dev_err_probe(dev, ret, "Failed to add clock provider\n");
goto err;
}
platform_set_drvdata(pdev, a7cc);
/*
* Attach the power domain to cpudev. Since there is no dedicated driver
* for CPUs and the SDX55 platform lacks hardware specific CPUFreq
* driver, there seems to be no better place to do this. So do it here!
*/
cpu_dev = get_cpu_device(0);
dev_pm_domain_attach(cpu_dev, true);
return 0;
err:
clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb);
return ret;
}
static int qcom_apcs_sdx55_clk_remove(struct platform_device *pdev)
{
struct device *cpu_dev = get_cpu_device(0);
struct clk_regmap_mux_div *a7cc = platform_get_drvdata(pdev);
clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb);
dev_pm_domain_detach(cpu_dev, true);
return 0;
}
static struct platform_driver qcom_apcs_sdx55_clk_driver = {
.probe = qcom_apcs_sdx55_clk_probe,
.remove = qcom_apcs_sdx55_clk_remove,
.driver = {
.name = "qcom-sdx55-acps-clk",
},
};
module_platform_driver(qcom_apcs_sdx55_clk_driver);
MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Qualcomm SDX55 APCS clock driver");

209
drivers/clk/qcom/clk-alpha-pll.c
View File

@ -156,6 +156,12 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
/* LUCID PLL specific settings and offsets */
#define LUCID_PCAL_DONE BIT(27)
/* LUCID 5LPE PLL specific settings and offsets */
#define LUCID_5LPE_PCAL_DONE BIT(11)
#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13)
#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
#define pll_alpha_width(p) \
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@ -777,15 +783,15 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
struct regmap *regmap)
{
u32 mode_regval, opmode_regval;
u32 mode_val, opmode_val;
int ret;
ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);
ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval);
ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
if (ret)
return 0;
return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL));
return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
}
static int clk_trion_pll_is_enabled(struct clk_hw *hw)
@ -1445,12 +1451,12 @@ EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 regval;
u32 val;
int ret;
/* Return early if calibration is not needed. */
regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);
if (regval & pcal_done)
regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
if (val & pcal_done)
return 0;
/* On/off to calibrate */
@ -1471,12 +1477,12 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw)
return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
}
static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate, u32 latch_bit, u32 latch_ack)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
unsigned long rrate;
u32 regval, l, alpha_width = pll_alpha_width(pll);
u32 val, l, alpha_width = pll_alpha_width(pll);
u64 a;
int ret;
@ -1490,22 +1496,20 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
/* Latch the PLL input */
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_UPDATE, PLL_UPDATE);
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
if (ret)
return ret;
/* Wait for 2 reference cycles before checking the ACK bit. */
udelay(1);
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
if (!(regval & ALPHA_PLL_ACK_LATCH)) {
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (!(val & latch_ack)) {
pr_err("Lucid PLL latch failed. Output may be unstable!\n");
return -EINVAL;
}
/* Return the latch input to 0 */
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_UPDATE, 0);
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
if (ret)
return ret;
@ -1520,6 +1524,12 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
}
const struct clk_ops clk_alpha_pll_trion_ops = {
.prepare = alpha_pll_trion_prepare,
.enable = clk_trion_pll_enable,
@ -1600,3 +1610,170 @@ const struct clk_ops clk_alpha_pll_agera_ops = {
.set_rate = clk_alpha_pll_agera_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val;
int ret;
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
if (ret)
return ret;
/* If in FSM mode, just vote for it */
if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
ret = clk_enable_regmap(hw);
if (ret)
return ret;
return wait_for_pll_enable_lock(pll);
}
/* Check if PLL is already enabled, return if enabled */
ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
if (ret < 0)
return ret;
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
if (ret)
return ret;
regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;
/* Enable the PLL outputs */
ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
if (ret)
return ret;
/* Enable the global PLL outputs */
return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
}
static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val;
int ret;
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
if (ret)
return;
/* If in FSM mode, just unvote it */
if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
clk_disable_regmap(hw);
return;
}
/* Disable the global PLL output */
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
if (ret)
return;
/* Disable the PLL outputs */
ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
if (ret)
return;
/* Place the PLL mode in STANDBY */
regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
}
/*
* The Lucid 5LPE PLL requires a power-on self-calibration which happens
* when the PLL comes out of reset. Calibrate in case it is not completed.
*/
static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct clk_hw *p;
u32 val = 0;
int ret;
/* Return early if calibration is not needed. */
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (val & LUCID_5LPE_PCAL_DONE)
return 0;
p = clk_hw_get_parent(hw);
if (!p)
return -EINVAL;
ret = alpha_pll_lucid_5lpe_enable(hw);
if (ret)
return ret;
alpha_pll_lucid_5lpe_disable(hw);
return 0;
}
static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
return __alpha_pll_trion_set_rate(hw, rate, prate,
LUCID_5LPE_PLL_LATCH_INPUT,
LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
}
static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
int i, val = 0, div, ret;
u32 mask;
/*
* If the PLL is in FSM mode, then treat set_rate callback as a
* no-operation.
*/
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
if (ret)
return ret;
if (val & LUCID_5LPE_ENABLE_VOTE_RUN)
return 0;
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
for (i = 0; i < pll->num_post_div; i++) {
if (pll->post_div_table[i].div == div) {
val = pll->post_div_table[i].val;
break;
}
}
mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
mask, val << pll->post_div_shift);
}
const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
.prepare = alpha_pll_lucid_5lpe_prepare,
.enable = alpha_pll_lucid_5lpe_enable,
.disable = alpha_pll_lucid_5lpe_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = alpha_pll_lucid_5lpe_set_rate,
};
EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops);
const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
.enable = alpha_pll_lucid_5lpe_enable,
.disable = alpha_pll_lucid_5lpe_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
};
EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_5lpe_ops);
const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
};
EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);

4
drivers/clk/qcom/clk-alpha-pll.h
View File

@ -144,6 +144,10 @@ extern const struct clk_ops clk_alpha_pll_lucid_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
extern const struct clk_ops clk_alpha_pll_agera_ops;
extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

9
drivers/clk/qcom/clk-rcg.h
View File

@ -153,6 +153,15 @@ struct clk_rcg2 {
#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
struct clk_rcg2_gfx3d {
u8 div;
struct clk_rcg2 rcg;
struct clk_hw **hws;
};
#define to_clk_rcg2_gfx3d(_hw) \
container_of(to_clk_rcg2(_hw), struct clk_rcg2_gfx3d, rcg)
extern const struct clk_ops clk_rcg2_ops;
extern const struct clk_ops clk_rcg2_floor_ops;
extern const struct clk_ops clk_edp_pixel_ops;

57
drivers/clk/qcom/clk-rcg2.c
View File

@ -728,40 +728,51 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rate_request parent_req = { };
struct clk_hw *p2, *p8, *p9, *xo;
unsigned long p9_rate;
struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw);
struct clk_hw *xo, *p0, *p1, *p2;
unsigned long request, p0_rate;
int ret;
p0 = cgfx->hws[0];
p1 = cgfx->hws[1];
p2 = cgfx->hws[2];
/*
* This function does ping-pong the RCG between PLLs: if we don't
* have at least one fixed PLL and two variable ones,
* then it's not going to work correctly.
*/
if (WARN_ON(!p0 || !p1 || !p2))
return -EINVAL;
xo = clk_hw_get_parent_by_index(hw, 0);
if (req->rate == clk_hw_get_rate(xo)) {
req->best_parent_hw = xo;
return 0;
}
p9 = clk_hw_get_parent_by_index(hw, 2);
p2 = clk_hw_get_parent_by_index(hw, 3);
p8 = clk_hw_get_parent_by_index(hw, 4);
request = req->rate;
if (cgfx->div > 1)
parent_req.rate = request = request * cgfx->div;
/* PLL9 is a fixed rate PLL */
p9_rate = clk_hw_get_rate(p9);
/* This has to be a fixed rate PLL */
p0_rate = clk_hw_get_rate(p0);
parent_req.rate = req->rate = min(req->rate, p9_rate);
if (req->rate == p9_rate) {
req->rate = req->best_parent_rate = p9_rate;
req->best_parent_hw = p9;
if (request == p0_rate) {
req->rate = req->best_parent_rate = p0_rate;
req->best_parent_hw = p0;
return 0;
}
if (req->best_parent_hw == p9) {
if (req->best_parent_hw == p0) {
/* Are we going back to a previously used rate? */
if (clk_hw_get_rate(p8) == req->rate)
req->best_parent_hw = p8;
else
if (clk_hw_get_rate(p2) == request)
req->best_parent_hw = p2;
} else if (req->best_parent_hw == p8) {
req->best_parent_hw = p2;
else
req->best_parent_hw = p1;
} else if (req->best_parent_hw == p2) {
req->best_parent_hw = p1;
} else {
req->best_parent_hw = p8;
req->best_parent_hw = p2;
}
ret = __clk_determine_rate(req->best_parent_hw, &parent_req);
@ -769,6 +780,8 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw,
return ret;
req->rate = req->best_parent_rate = parent_req.rate;
if (cgfx->div > 1)
req->rate /= cgfx->div;
return 0;
}
@ -776,12 +789,16 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw,
static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate, u8 index)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw);
struct clk_rcg2 *rcg = &cgfx->rcg;
u32 cfg;
int ret;
/* Just mux it, we don't use the division or m/n hardware */
cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
/* On some targets, the GFX3D RCG may need to divide PLL frequency */
if (cgfx->div > 1)
cfg |= ((2 * cgfx->div) - 1) << CFG_SRC_DIV_SHIFT;
ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
if (ret)
return ret;

1
drivers/clk/qcom/clk-regmap.c
View File

@ -87,6 +87,7 @@ EXPORT_SYMBOL_GPL(clk_disable_regmap);
/**
* devm_clk_register_regmap - register a clk_regmap clock
*
* @dev: reference to the caller's device
* @rclk: clk to operate on
*
* Clocks that use regmap for their register I/O should register their

63
drivers/clk/qcom/clk-rpm.c
View File

@ -73,62 +73,6 @@
}, \
}
#define DEFINE_CLK_RPM_PXO_BRANCH(_platform, _name, _active, r_id, r) \
static struct clk_rpm _platform##_##_active; \
static struct clk_rpm _platform##_##_name = { \
.rpm_clk_id = (r_id), \
.active_only = true, \
.peer = &_platform##_##_active, \
.rate = (r), \
.branch = true, \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpm_branch_ops, \
.name = #_name, \
.parent_names = (const char *[]){ "pxo_board" }, \
.num_parents = 1, \
}, \
}; \
static struct clk_rpm _platform##_##_active = { \
.rpm_clk_id = (r_id), \
.peer = &_platform##_##_name, \
.rate = (r), \
.branch = true, \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpm_branch_ops, \
.name = #_active, \
.parent_names = (const char *[]){ "pxo_board" }, \
.num_parents = 1, \
}, \
}
#define DEFINE_CLK_RPM_CXO_BRANCH(_platform, _name, _active, r_id, r) \
static struct clk_rpm _platform##_##_active; \
static struct clk_rpm _platform##_##_name = { \
.rpm_clk_id = (r_id), \
.peer = &_platform##_##_active, \
.rate = (r), \
.branch = true, \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpm_branch_ops, \
.name = #_name, \
.parent_names = (const char *[]){ "cxo_board" }, \
.num_parents = 1, \
}, \
}; \
static struct clk_rpm _platform##_##_active = { \
.rpm_clk_id = (r_id), \
.active_only = true, \
.peer = &_platform##_##_name, \
.rate = (r), \
.branch = true, \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpm_branch_ops, \
.name = #_active, \
.parent_names = (const char *[]){ "cxo_board" }, \
.num_parents = 1, \
}, \
}
#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
struct rpm_cc;
@ -450,13 +394,6 @@ static const struct clk_ops clk_rpm_ops = {
.recalc_rate = clk_rpm_recalc_rate,
};
static const struct clk_ops clk_rpm_branch_ops = {
.prepare = clk_rpm_prepare,
.unprepare = clk_rpm_unprepare,
.round_rate = clk_rpm_round_rate,
.recalc_rate = clk_rpm_recalc_rate,
};
/* MSM8660/APQ8060 */
DEFINE_CLK_RPM(msm8660, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
DEFINE_CLK_RPM(msm8660, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);

49
drivers/clk/qcom/clk-rpmh.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
@ -348,6 +348,10 @@ DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, rf_clk3_ao, "rfclkd3", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, rf_clk4_ao, "rfclkd4", 1);
DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0");
@ -431,6 +435,26 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
.num_clks = ARRAY_SIZE(sc7180_rpmh_clocks),
};
static struct clk_hw *sc8180x_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
[RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw,
[RPMH_RF_CLK3] = &sc8180x_rf_clk3.hw,
[RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
.clks = sc8180x_rpmh_clocks,
.num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks),
};
DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);
static struct clk_hw *sm8250_rpmh_clocks[] = {
@ -486,6 +510,27 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
.num_clks = ARRAY_SIZE(sm8350_rpmh_clocks),
};
static struct clk_hw *sc7280_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
[RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
[RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
[RPMH_PKA_CLK] = &sm8350_pka.hw,
[RPMH_HWKM_CLK] = &sm8350_hwkm.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
.clks = sc7280_rpmh_clocks,
.num_clks = ARRAY_SIZE(sc7280_rpmh_clocks),
};
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@ -570,11 +615,13 @@ static int clk_rpmh_probe(struct platform_device *pdev)
static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
{ .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
{ .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
{ .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
{ .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
{ }
};
MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);

7
drivers/clk/qcom/gcc-ipq4019.c
View File

@ -1276,16 +1276,15 @@ static int clk_cpu_div_set_rate(struct clk_hw *hw, unsigned long rate,
struct clk_fepll *pll = to_clk_fepll(hw);
const struct freq_tbl *f;
u32 mask;
int ret;
f = qcom_find_freq(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift;
ret = regmap_update_bits(pll->cdiv.clkr.regmap,
pll->cdiv.reg, mask,
f->pre_div << pll->cdiv.shift);
regmap_update_bits(pll->cdiv.clkr.regmap,
pll->cdiv.reg, mask,
f->pre_div << pll->cdiv.shift);
/*
* There is no status bit which can be checked for successful CPU
* divider update operation so using delay for the same.

143
drivers/clk/qcom/gcc-msm8998.c
View File

@ -135,7 +135,7 @@ static struct pll_vco fabia_vco[] = {
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr = {
@ -145,58 +145,58 @@ static struct clk_alpha_pll gpll0 = {
.name = "gpll0",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
},
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_names = (const char *[]){ "gpll0" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll0_out_main = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_main",
.parent_names = (const char *[]){ "gpll0" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll0_out_odd = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_odd",
.parent_names = (const char *[]){ "gpll0" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll0_out_test = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_test",
.parent_names = (const char *[]){ "gpll0" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll gpll1 = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr = {
@ -206,58 +206,58 @@ static struct clk_alpha_pll gpll1 = {
.name = "gpll1",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
},
};
static struct clk_alpha_pll_postdiv gpll1_out_even = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1_out_even",
.parent_names = (const char *[]){ "gpll1" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll1_out_main = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1_out_main",
.parent_names = (const char *[]){ "gpll1" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll1_out_odd = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1_out_odd",
.parent_names = (const char *[]){ "gpll1" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll1_out_test = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1_out_test",
.parent_names = (const char *[]){ "gpll1" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll gpll2 = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr = {
@ -267,58 +267,58 @@ static struct clk_alpha_pll gpll2 = {
.name = "gpll2",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
},
};
static struct clk_alpha_pll_postdiv gpll2_out_even = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2_out_even",
.parent_names = (const char *[]){ "gpll2" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll2_out_main = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2_out_main",
.parent_names = (const char *[]){ "gpll2" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll2_out_odd = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2_out_odd",
.parent_names = (const char *[]){ "gpll2" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll2_out_test = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2_out_test",
.parent_names = (const char *[]){ "gpll2" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll gpll3 = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr = {
@ -328,58 +328,58 @@ static struct clk_alpha_pll gpll3 = {
.name = "gpll3",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
},
};
static struct clk_alpha_pll_postdiv gpll3_out_even = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3_out_even",
.parent_names = (const char *[]){ "gpll3" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll3_out_main = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3_out_main",
.parent_names = (const char *[]){ "gpll3" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll3_out_odd = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3_out_odd",
.parent_names = (const char *[]){ "gpll3" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll3_out_test = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3_out_test",
.parent_names = (const char *[]){ "gpll3" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll gpll4 = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr = {
@ -389,52 +389,52 @@ static struct clk_alpha_pll gpll4 = {
.name = "gpll4",
.parent_names = (const char *[]){ "xo" },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
},
};
static struct clk_alpha_pll_postdiv gpll4_out_even = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4_out_even",
.parent_names = (const char *[]){ "gpll4" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll4_out_main = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4_out_main",
.parent_names = (const char *[]){ "gpll4" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll4_out_odd = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4_out_odd",
.parent_names = (const char *[]){ "gpll4" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll4_out_test = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4_out_test",
.parent_names = (const char *[]){ "gpll4" },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
@ -1341,6 +1341,22 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
},
};
static struct clk_branch gcc_mmss_gpll0_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_gpll0_clk",
.parent_names = (const char *[]){
"gpll0_out_main",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
@ -2065,6 +2081,12 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
.ops = &clk_branch2_ops,
/*
* The GPU IOMMU depends on this clock and hypervisor
* will crash the SoC if this clock goes down, due to
* secure contexts protection.
*/
.flags = CLK_IS_CRITICAL,
},
},
};
@ -2144,6 +2166,25 @@ static struct clk_branch gcc_hmss_trig_clk = {
},
};
static struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 hmss_gpll0_clk_src = {
.cmd_rcgr = 0x4805c,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_hmss_gpll0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "hmss_gpll0_clk_src",
.parent_names = gcc_parent_names_1,
.num_parents = ARRAY_SIZE(gcc_parent_names_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
.halt_reg = 0x9004,
.halt_check = BRANCH_HALT,
@ -2944,6 +2985,8 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
[GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
[GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
[HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
};
static struct gdsc *gcc_msm8998_gdscs[] = {

47
drivers/clk/qcom/gcc-sc7180.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
@ -934,19 +934,6 @@ static struct clk_branch gcc_camera_throttle_hf_axi_clk = {
},
};
static struct clk_branch gcc_camera_xo_clk = {
.halt_reg = 0xb02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_ahb_clk = {
.halt_reg = 0x4100c,
.halt_check = BRANCH_HALT_VOTED,
@ -1111,19 +1098,6 @@ static struct clk_branch gcc_disp_throttle_hf_axi_clk = {
},
};
static struct clk_branch gcc_disp_xo_clk = {
.halt_reg = 0xb030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
@ -2174,19 +2148,6 @@ static struct clk_branch gcc_video_throttle_axi_clk = {
},
};
static struct clk_branch gcc_video_xo_clk = {
.halt_reg = 0xb028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x8a000,
.halt_check = BRANCH_HALT,
@ -2320,7 +2281,6 @@ static struct clk_regmap *gcc_sc7180_clocks[] = {
[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr,
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
@ -2333,7 +2293,6 @@ static struct clk_regmap *gcc_sc7180_clocks[] = {
[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr,
[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
@ -2429,7 +2388,6 @@ static struct clk_regmap *gcc_sc7180_clocks[] = {
[GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
[GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr,
[GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL6] = &gpll6.clkr,
@ -2525,6 +2483,9 @@ static int gcc_sc7180_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,

3603
drivers/clk/qcom/gcc-sc7280.c Normal file
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File diff suppressed because it is too large Load Diff

4629
drivers/clk/qcom/gcc-sc8180x.c Normal file
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File diff suppressed because it is too large Load Diff

7
drivers/clk/qcom/gcc-sdm660.c
View File

@ -1571,6 +1571,7 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
.ops = &clk_branch2_ops,
.flags = CLK_IS_CRITICAL,
},
},
};
@ -1684,6 +1685,12 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_noc_cfg_ahb_clk",
.ops = &clk_branch2_ops,
/*
* Any access to mmss depends on this clock.
* Gating this clock has been shown to crash the system
* when mmssnoc_axi_rpm_clk is inited in rpmcc.
*/
.flags = CLK_IS_CRITICAL,
},
},
};

3890
drivers/clk/qcom/gcc-sm8350.c Normal file
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File diff suppressed because it is too large Load Diff

10
drivers/clk/qcom/gdsc.c
View File

@ -183,7 +183,10 @@ static inline int gdsc_assert_reset(struct gdsc *sc)
static inline void gdsc_force_mem_on(struct gdsc *sc)
{
int i;
u32 mask = RETAIN_MEM | RETAIN_PERIPH;
u32 mask = RETAIN_MEM;
if (!(sc->flags & NO_RET_PERIPH))
mask |= RETAIN_PERIPH;
for (i = 0; i < sc->cxc_count; i++)
regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
@ -192,7 +195,10 @@ static inline void gdsc_force_mem_on(struct gdsc *sc)
static inline void gdsc_clear_mem_on(struct gdsc *sc)
{
int i;
u32 mask = RETAIN_MEM | RETAIN_PERIPH;
u32 mask = RETAIN_MEM;
if (!(sc->flags & NO_RET_PERIPH))
mask |= RETAIN_PERIPH;
for (i = 0; i < sc->cxc_count; i++)
regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);

3
drivers/clk/qcom/gdsc.h
View File

@ -42,7 +42,7 @@ struct gdsc {
#define PWRSTS_ON BIT(2)
#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
const u8 flags;
const u16 flags;
#define VOTABLE BIT(0)
#define CLAMP_IO BIT(1)
#define HW_CTRL BIT(2)
@ -51,6 +51,7 @@ struct gdsc {
#define POLL_CFG_GDSCR BIT(5)
#define ALWAYS_ON BIT(6)
#define RETAIN_FF_ENABLE BIT(7)
#define NO_RET_PERIPH BIT(8)
struct reset_controller_dev *rcdev;
unsigned int *resets;
unsigned int reset_count;

18
drivers/clk/qcom/gpucc-msm8998.c
View File

@ -50,6 +50,11 @@ static struct clk_branch gpucc_cxo_clk = {
},
};
static struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
{ 125000000, 1000000000, 1 },
};
static const struct clk_div_table post_div_table_fabia_even[] = {
{ 0x0, 1 },
{ 0x1, 2 },
@ -61,11 +66,13 @@ static const struct clk_div_table post_div_table_fabia_even[] = {
static struct clk_alpha_pll gpupll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "gpupll0",
.parent_hws = (const struct clk_hw *[]){ &gpucc_cxo_clk.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
.ops = &clk_alpha_pll_fabia_ops,
},
};
@ -80,6 +87,7 @@ static struct clk_alpha_pll_postdiv gpupll0_out_even = {
.name = "gpupll0_out_even",
.parent_hws = (const struct clk_hw *[]){ &gpupll0.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
@ -253,12 +261,16 @@ static struct gdsc gpu_cx_gdsc = {
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x1094,
.clamp_io_ctrl = 0x130,
.resets = (unsigned int []){ GPU_GX_BCR },
.reset_count = 1,
.cxcs = (unsigned int []){ 0x1098 },
.cxc_count = 1,
.pd = {
.name = "gpu_gx",
},
.parent = &gpu_cx_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | AON_RESET,
.pwrsts = PWRSTS_OFF_ON | PWRSTS_RET,
.flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
};
static struct clk_regmap *gpucc_msm8998_clocks[] = {

349
drivers/clk/qcom/gpucc-sdm660.c Normal file
View File

@ -0,0 +1,349 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2020, AngeloGioacchino Del Regno
* <angelogioacchino.delregno@somainline.org>
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gpucc-sdm660.h>
#include "clk-alpha-pll.h"
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_GPU_XO,
P_CORE_BI_PLL_TEST_SE,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_PLL0_PLL_OUT_MAIN,
P_GPU_PLL1_PLL_OUT_MAIN,
};
static struct clk_branch gpucc_cxo_clk = {
.halt_reg = 0x1020,
.clkr = {
.enable_reg = 0x1020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cxo_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo"
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_IS_CRITICAL,
},
},
};
static struct pll_vco gpu_vco[] = {
{ 1000000000, 2000000000, 0 },
{ 500000000, 1000000000, 2 },
{ 250000000, 500000000, 3 },
};
static struct clk_alpha_pll gpu_pll0_pll_out_main = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = gpu_vco,
.num_vco = ARRAY_SIZE(gpu_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_pll0_pll_out_main",
.parent_data = &(const struct clk_parent_data){
.hw = &gpucc_cxo_clk.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static struct clk_alpha_pll gpu_pll1_pll_out_main = {
.offset = 0x40,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = gpu_vco,
.num_vco = ARRAY_SIZE(gpu_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_pll1_pll_out_main",
.parent_data = &(const struct clk_parent_data){
.hw = &gpucc_cxo_clk.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static const struct parent_map gpucc_parent_map_1[] = {
{ P_GPU_XO, 0 },
{ P_GPU_PLL0_PLL_OUT_MAIN, 1 },
{ P_GPU_PLL1_PLL_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data gpucc_parent_data_1[] = {
{ .hw = &gpucc_cxo_clk.clkr.hw },
{ .hw = &gpu_pll0_pll_out_main.clkr.hw },
{ .hw = &gpu_pll1_pll_out_main.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk", .name = "gcc_gpu_gpll0_clk" },
};
static struct clk_rcg2_gfx3d gfx3d_clk_src = {
.div = 2,
.rcg = {
.cmd_rcgr = 0x1070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpucc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_data = gpucc_parent_data_1,
.num_parents = 4,
.ops = &clk_gfx3d_ops,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
},
},
.hws = (struct clk_hw*[]){
&gpucc_cxo_clk.clkr.hw,
&gpu_pll0_pll_out_main.clkr.hw,
&gpu_pll1_pll_out_main.clkr.hw,
}
};
static struct clk_branch gpucc_gfx3d_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1098,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_gfx3d_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gfx3d_clk_src.rcg.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct parent_map gpucc_parent_map_0[] = {
{ P_GPU_XO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpucc_parent_data_0[] = {
{ .hw = &gpucc_cxo_clk.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk", .name = "gcc_gpu_gpll0_clk" },
{ .fw_name = "gcc_gpu_gpll0_div_clk", .name = "gcc_gpu_gpll0_div_clk" },
};
static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
F(19200000, P_GPU_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 rbbmtimer_clk_src = {
.cmd_rcgr = 0x10b0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpucc_parent_map_0,
.freq_tbl = ftbl_rbbmtimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbbmtimer_clk_src",
.parent_data = gpucc_parent_data_0,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
F(19200000, P_GPU_XO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0),
{ }
};
static struct clk_rcg2 rbcpr_clk_src = {
.cmd_rcgr = 0x1030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpucc_parent_map_0,
.freq_tbl = ftbl_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbcpr_clk_src",
.parent_data = gpucc_parent_data_0,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gpucc_rbbmtimer_clk = {
.halt_reg = 0x10d0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_rbbmtimer_clk",
.parent_names = (const char *[]){
"rbbmtimer_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_rbcpr_clk = {
.halt_reg = 0x1054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_rbcpr_clk",
.parent_names = (const char *[]){
"rbcpr_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x1004,
.gds_hw_ctrl = 0x1008,
.pd = {
.name = "gpu_cx",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x1094,
.clamp_io_ctrl = 0x130,
.resets = (unsigned int []){ GPU_GX_BCR },
.reset_count = 1,
.cxcs = (unsigned int []){ 0x1098 },
.cxc_count = 1,
.pd = {
.name = "gpu_gx",
},
.parent = &gpu_cx_gdsc.pd,
.pwrsts = PWRSTS_OFF | PWRSTS_ON | PWRSTS_RET,
.flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
};
static struct gdsc *gpucc_sdm660_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct qcom_reset_map gpucc_sdm660_resets[] = {
[GPU_CX_BCR] = { 0x1000 },
[RBCPR_BCR] = { 0x1050 },
[GPU_GX_BCR] = { 0x1090 },
[SPDM_BCR] = { 0x10E0 },
};
static struct clk_regmap *gpucc_sdm660_clocks[] = {
[GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr,
[GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr,
[GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
[GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr,
[GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr,
[GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr,
};
static const struct regmap_config gpucc_660_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9034,
.fast_io = true,
};
static const struct qcom_cc_desc gpucc_sdm660_desc = {
.config = &gpucc_660_regmap_config,
.clks = gpucc_sdm660_clocks,
.num_clks = ARRAY_SIZE(gpucc_sdm660_clocks),
.resets = gpucc_sdm660_resets,
.num_resets = ARRAY_SIZE(gpucc_sdm660_resets),
.gdscs = gpucc_sdm660_gdscs,
.num_gdscs = ARRAY_SIZE(gpucc_sdm660_gdscs),
};
static const struct of_device_id gpucc_sdm660_match_table[] = {
{ .compatible = "qcom,gpucc-sdm660" },
{ .compatible = "qcom,gpucc-sdm630" },
{ }
};
MODULE_DEVICE_TABLE(of, gpucc_sdm660_match_table);
static int gpucc_sdm660_probe(struct platform_device *pdev)
{
struct regmap *regmap;
struct alpha_pll_config gpu_pll_config = {
.config_ctl_val = 0x4001055b,
.alpha = 0xaaaaab00,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = 0x3 << 20,
.main_output_mask = 0x1,
};
regmap = qcom_cc_map(pdev, &gpucc_sdm660_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* 800MHz configuration for GPU PLL0 */
gpu_pll_config.l = 0x29;
gpu_pll_config.alpha_hi = 0xaa;
clk_alpha_pll_configure(&gpu_pll0_pll_out_main, regmap, &gpu_pll_config);
/* 740MHz configuration for GPU PLL1 */
gpu_pll_config.l = 0x26;
gpu_pll_config.alpha_hi = 0x8a;
clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, &gpu_pll_config);
return qcom_cc_really_probe(pdev, &gpucc_sdm660_desc, regmap);
}
static struct platform_driver gpucc_sdm660_driver = {
.probe = gpucc_sdm660_probe,
.driver = {
.name = "gpucc-sdm660",
.of_match_table = gpucc_sdm660_match_table,
},
};
module_platform_driver(gpucc_sdm660_driver);
MODULE_DESCRIPTION("Qualcomm SDM630/SDM660 GPUCC Driver");
MODULE_LICENSE("GPL v2");

8
drivers/clk/qcom/lpass-gfm-sm8250.c
View File

@ -33,14 +33,13 @@ struct clk_gfm {
void __iomem *gfm_mux;
};
#define GFM_MASK BIT(1)
#define to_clk_gfm(_hw) container_of(_hw, struct clk_gfm, hw)
static u8 clk_gfm_get_parent(struct clk_hw *hw)
{
struct clk_gfm *clk = to_clk_gfm(hw);
return readl(clk->gfm_mux) & GFM_MASK;
return readl(clk->gfm_mux) & clk->mux_mask;
}
static int clk_gfm_set_parent(struct clk_hw *hw, u8 index)
@ -51,9 +50,10 @@ static int clk_gfm_set_parent(struct clk_hw *hw, u8 index)
val = readl(clk->gfm_mux);
if (index)
val |= GFM_MASK;
val |= clk->mux_mask;
else
val &= ~GFM_MASK;
val &= ~clk->mux_mask;
writel(val, clk->gfm_mux);

16
drivers/clk/qcom/mmcc-msm8974.c
View File

@ -74,22 +74,6 @@ static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
"dsi1pll",
};
static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_MMPLL2, 3 }
};
static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
"xo",
"mmpll0_vote",
"mmpll1_vote",
"mmss_gpll0_vote",
"mmpll2",
};
static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },

29
drivers/clk/qcom/mmcc-msm8996.c
View File

@ -528,16 +528,23 @@ static struct clk_rcg2 maxi_clk_src = {
},
};
static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x4000,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
.num_parents = 6,
.ops = &clk_gfx3d_ops,
.flags = CLK_SET_RATE_PARENT,
static struct clk_rcg2_gfx3d gfx3d_clk_src = {
.rcg = {
.cmd_rcgr = 0x4000,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
.num_parents = 6,
.ops = &clk_gfx3d_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
.hws = (struct clk_hw*[]) {
&mmpll9.clkr.hw,
&mmpll2.clkr.hw,
&mmpll8.clkr.hw
},
};
@ -3089,7 +3096,7 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = {
[AHB_CLK_SRC] = &ahb_clk_src.clkr,
[AXI_CLK_SRC] = &axi_clk_src.clkr,
[MAXI_CLK_SRC] = &maxi_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
[ISENSE_CLK_SRC] = &isense_clk_src.clkr,
[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,

12
drivers/clk/qcom/mmcc-msm8998.c
View File

@ -1211,6 +1211,8 @@ static struct clk_rcg2 vfe1_clk_src = {
static struct clk_branch misc_ahb_clk = {
.halt_reg = 0x328,
.hwcg_reg = 0x328,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x328,
.enable_mask = BIT(0),
@ -1241,6 +1243,8 @@ static struct clk_branch video_core_clk = {
static struct clk_branch video_ahb_clk = {
.halt_reg = 0x1030,
.hwcg_reg = 0x1030,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1030,
.enable_mask = BIT(0),
@ -1315,6 +1319,8 @@ static struct clk_branch video_subcore1_clk = {
static struct clk_branch mdss_ahb_clk = {
.halt_reg = 0x2308,
.hwcg_reg = 0x2308,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2308,
.enable_mask = BIT(0),
@ -2496,6 +2502,8 @@ static struct clk_branch mnoc_ahb_clk = {
static struct clk_branch bimc_smmu_ahb_clk = {
.halt_reg = 0xe004,
.hwcg_reg = 0xe004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xe004,
.enable_mask = BIT(0),
@ -2511,6 +2519,8 @@ static struct clk_branch bimc_smmu_ahb_clk = {
static struct clk_branch bimc_smmu_axi_clk = {
.halt_reg = 0xe008,
.hwcg_reg = 0xe008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xe008,
.enable_mask = BIT(0),
@ -2653,7 +2663,7 @@ static struct gdsc bimc_smmu_gdsc = {
.name = "bimc_smmu",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
.flags = HW_CTRL | ALWAYS_ON,
};
static struct clk_regmap *mmcc_msm8998_clocks[] = {

2864
drivers/clk/qcom/mmcc-sdm660.c Normal file
View File

File diff suppressed because it is too large Load Diff

39
drivers/clk/qcom/videocc-sm8250.c
View File

@ -169,6 +169,21 @@ static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
},
};
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
.reg = 0xd54,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "video_cc_mvs0_div_clk_src",
.parent_data = &(const struct clk_parent_data){
.hw = &video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
.reg = 0xcf4,
.shift = 0,
@ -202,6 +217,24 @@ static struct clk_branch video_cc_mvs0c_clk = {
},
};
static struct clk_branch video_cc_mvs0_clk = {
.halt_reg = 0xd34,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xd34,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &video_cc_mvs0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1_div2_clk = {
.halt_reg = 0xdf4,
.halt_check = BRANCH_HALT_VOTED,
@ -245,6 +278,7 @@ static struct gdsc mvs0c_gdsc = {
},
.flags = 0,
.pwrsts = PWRSTS_OFF_ON,
.supply = "mmcx",
};
static struct gdsc mvs1c_gdsc = {
@ -254,6 +288,7 @@ static struct gdsc mvs1c_gdsc = {
},
.flags = 0,
.pwrsts = PWRSTS_OFF_ON,
.supply = "mmcx",
};
static struct gdsc mvs0_gdsc = {
@ -263,6 +298,7 @@ static struct gdsc mvs0_gdsc = {
},
.flags = HW_CTRL,
.pwrsts = PWRSTS_OFF_ON,
.supply = "mmcx",
};
static struct gdsc mvs1_gdsc = {
@ -272,10 +308,13 @@ static struct gdsc mvs1_gdsc = {
},
.flags = HW_CTRL,
.pwrsts = PWRSTS_OFF_ON,
.supply = "mmcx",
};
static struct clk_regmap *video_cc_sm8250_clocks[] = {
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,

5
drivers/clk/sifive/fu540-prci.h
View File

@ -13,9 +13,4 @@
extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540];
static const struct prci_clk_desc prci_clk_fu540 = {
.clks = __prci_init_clocks_fu540,
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
};
#endif /* __SIFIVE_CLK_FU540_PRCI_H */

5
drivers/clk/sifive/sifive-prci.c
View File

@ -12,6 +12,11 @@
#include "fu540-prci.h"
#include "fu740-prci.h"
static const struct prci_clk_desc prci_clk_fu540 = {
.clks = __prci_init_clocks_fu540,
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
};
/*
* Private functions
*/

88
drivers/clk/socfpga/clk-agilex.c
View File

@ -196,6 +196,17 @@ static const struct stratix10_pll_clock agilex_pll_clks[] = {
0, 0x9c},
};
static const struct n5x_perip_c_clock n5x_main_perip_c_clks[] = {
{ AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x54, 0},
{ AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x54, 8},
{ AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x54, 16},
{ AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x54, 24},
{ AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xA8, 0},
{ AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xA8, 8},
{ AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xA8, 16},
{ AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xA8, 24},
};
static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
{ AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
{ AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
@ -289,6 +300,25 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
10, 0, 0, 0, 0, 0, 4},
};
static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
int nums, struct stratix10_clock_data *data)
{
struct clk *clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
clk = n5x_register_periph(&clks[i], base);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
data->clk_data.clks[clks[i].id] = clk;
}
return 0;
}
static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
int nums, struct stratix10_clock_data *data)
{
@ -367,6 +397,26 @@ static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
return 0;
}
static int n5x_clk_register_pll(const struct stratix10_pll_clock *clks,
int nums, struct stratix10_clock_data *data)
{
struct clk *clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
clk = n5x_register_pll(&clks[i], base);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
data->clk_data.clks[clks[i].id] = clk;
}
return 0;
}
static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_device *pdev,
int nr_clks)
{
@ -401,7 +451,7 @@ static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_de
return clk_data;
}
static int agilex_clkmgr_probe(struct platform_device *pdev)
static int agilex_clkmgr_init(struct platform_device *pdev)
{
struct stratix10_clock_data *clk_data;
@ -423,9 +473,43 @@ static int agilex_clkmgr_probe(struct platform_device *pdev)
return 0;
}
static int n5x_clkmgr_init(struct platform_device *pdev)
{
struct stratix10_clock_data *clk_data;
clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
if (IS_ERR(clk_data))
return PTR_ERR(clk_data);
n5x_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
n5x_clk_register_c_perip(n5x_main_perip_c_clks,
ARRAY_SIZE(n5x_main_perip_c_clks), clk_data);
agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
ARRAY_SIZE(agilex_main_perip_cnt_clks),
clk_data);
agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
clk_data);
return 0;
}
static int agilex_clkmgr_probe(struct platform_device *pdev)
{
int (*probe_func)(struct platform_device *init_func);
probe_func = of_device_get_match_data(&pdev->dev);
if (!probe_func)
return -ENODEV;
return probe_func(pdev);
}
static const struct of_device_id agilex_clkmgr_match_table[] = {
{ .compatible = "intel,agilex-clkmgr",
.data = agilex_clkmgr_probe },
.data = agilex_clkmgr_init },
{ .compatible = "intel,easic-n5x-clkmgr",
.data = n5x_clkmgr_init },
{ }
};

53
drivers/clk/socfpga/clk-periph-s10.c
View File

@ -15,6 +15,21 @@
#define to_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
static unsigned long n5x_clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
unsigned long div;
unsigned long shift = socfpgaclk->shift;
u32 val;
val = readl(socfpgaclk->hw.reg);
val &= (0x1f << shift);
div = (val >> shift) + 1;
return parent_rate / div;
}
static unsigned long clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
@ -63,6 +78,11 @@ static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
return parent;
}
static const struct clk_ops n5x_peri_c_clk_ops = {
.recalc_rate = n5x_clk_peri_c_clk_recalc_rate,
.get_parent = clk_periclk_get_parent,
};
static const struct clk_ops peri_c_clk_ops = {
.recalc_rate = clk_peri_c_clk_recalc_rate,
.get_parent = clk_periclk_get_parent,
@ -107,6 +127,39 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
return clk;
}
struct clk *n5x_register_periph(const struct n5x_perip_c_clock *clks,
void __iomem *regbase)
{
struct clk *clk;
struct socfpga_periph_clk *periph_clk;
struct clk_init_data init;
const char *name = clks->name;
const char *parent_name = clks->parent_name;
periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
if (WARN_ON(!periph_clk))
return NULL;
periph_clk->hw.reg = regbase + clks->offset;
periph_clk->shift = clks->shift;
init.name = name;
init.ops = &n5x_peri_c_clk_ops;
init.flags = clks->flags;
init.num_parents = clks->num_parents;
init.parent_names = parent_name ? &parent_name : NULL;
periph_clk->hw.hw.init = &init;
clk = clk_register(NULL, &periph_clk->hw.hw);
if (WARN_ON(IS_ERR(clk))) {
kfree(periph_clk);
return NULL;
}
return clk;
}
struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
void __iomem *regbase)
{

3
drivers/clk/socfpga/clk-pll-a10.c
View File

@ -73,7 +73,6 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node,
const char *parent_name[SOCFGPA_MAX_PARENTS];
struct clk_init_data init;
struct device_node *clkmgr_np;
int rc;
int i = 0;
of_property_read_u32(node, "reg", &reg);
@ -108,7 +107,7 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node,
kfree(pll_clk);
return NULL;
}
rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
of_clk_add_provider(node, of_clk_src_simple_get, clk);
return clk;
}

83
drivers/clk/socfpga/clk-pll-s10.c
View File

@ -27,10 +27,37 @@
#define SWCTRLBTCLKSEL_MASK 0x200
#define SWCTRLBTCLKSEL_SHIFT 9
#define SOCFPGA_N5X_PLLDIV_FDIV_MASK GENMASK(16, 8)
#define SOCFPGA_N5X_PLLDIV_FDIV_SHIFT 8
#define SOCFPGA_N5X_PLLDIV_RDIV_MASK GENMASK(5, 0)
#define SOCFPGA_N5X_PLLDIV_QDIV_MASK GENMASK(26, 24)
#define SOCFPGA_N5X_PLLDIV_QDIV_SHIFT 24
#define SOCFPGA_BOOT_CLK "boot_clk"
#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
static unsigned long n5x_clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
unsigned long fdiv, reg, rdiv, qdiv;
u32 power = 1;
/* read VCO1 reg for numerator and denominator */
reg = readl(socfpgaclk->hw.reg + 0x8);
fdiv = (reg & SOCFPGA_N5X_PLLDIV_FDIV_MASK) >> SOCFPGA_N5X_PLLDIV_FDIV_SHIFT;
rdiv = (reg & SOCFPGA_N5X_PLLDIV_RDIV_MASK);
qdiv = (reg & SOCFPGA_N5X_PLLDIV_QDIV_MASK) >> SOCFPGA_N5X_PLLDIV_QDIV_SHIFT;
while (qdiv) {
power *= 2;
qdiv--;
}
return ((parent_rate * 2 * (fdiv + 1)) / ((rdiv + 1) * power));
}
static unsigned long agilex_clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
@ -123,6 +150,25 @@ static int clk_pll_prepare(struct clk_hw *hwclk)
return 0;
}
static int n5x_clk_pll_prepare(struct clk_hw *hwclk)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
u32 reg;
/* Bring PLL out of reset */
reg = readl(socfpgaclk->hw.reg + 0x4);
reg |= SOCFPGA_PLL_RESET_MASK;
writel(reg, socfpgaclk->hw.reg + 0x4);
return 0;
}
static const struct clk_ops n5x_clk_pll_ops = {
.recalc_rate = n5x_clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
.prepare = n5x_clk_pll_prepare,
};
static const struct clk_ops agilex_clk_pll_ops = {
.recalc_rate = agilex_clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
@ -214,3 +260,40 @@ struct clk *agilex_register_pll(const struct stratix10_pll_clock *clks,
}
return clk;
}
struct clk *n5x_register_pll(const struct stratix10_pll_clock *clks,
void __iomem *reg)
{
struct clk *clk;
struct socfpga_pll *pll_clk;
struct clk_init_data init;
const char *name = clks->name;
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
if (WARN_ON(!pll_clk))
return NULL;
pll_clk->hw.reg = reg + clks->offset;
if (streq(name, SOCFPGA_BOOT_CLK))
init.ops = &clk_boot_ops;
else
init.ops = &n5x_clk_pll_ops;
init.name = name;
init.flags = clks->flags;
init.num_parents = clks->num_parents;
init.parent_names = NULL;
init.parent_data = clks->parent_data;
pll_clk->hw.hw.init = &init;
pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
clk = clk_register(NULL, &pll_clk->hw.hw);
if (WARN_ON(IS_ERR(clk))) {
kfree(pll_clk);
return NULL;
}
return clk;
}

3
drivers/clk/socfpga/clk-pll.c
View File

@ -80,7 +80,6 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct device_node *clkmgr_np;
int rc;
of_property_read_u32(node, "reg", &reg);
@ -111,7 +110,7 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
kfree(pll_clk);
return NULL;
}
rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
of_clk_add_provider(node, of_clk_src_simple_get, clk);
return clk;
}

17
drivers/clk/socfpga/stratix10-clk.h
View File

@ -30,6 +30,17 @@ struct stratix10_perip_c_clock {
unsigned long offset;
};
struct n5x_perip_c_clock {
unsigned int id;
const char *name;
const char *parent_name;
const char *const *parent_names;
u8 num_parents;
unsigned long flags;
unsigned long offset;
unsigned long shift;
};
struct stratix10_perip_cnt_clock {
unsigned int id;
const char *name;
@ -64,8 +75,12 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *,
void __iomem *);
struct clk *agilex_register_pll(const struct stratix10_pll_clock *,
void __iomem *);
struct clk *n5x_register_pll(const struct stratix10_pll_clock *clks,
void __iomem *reg);
struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
void __iomem *);
void __iomem *reg);
struct clk *n5x_register_periph(const struct n5x_perip_c_clock *clks,
void __iomem *reg);
struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
void __iomem *);
struct clk *s10_register_gate(const struct stratix10_gate_clock *,

1
drivers/clk/spear/spear1310_clock.c
View File

@ -12,6 +12,7 @@
*/
#include <linux/clkdev.h>
#include <linux/clk/spear.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of_platform.h>

1
drivers/clk/spear/spear1340_clock.c
View File

@ -12,6 +12,7 @@
*/
#include <linux/clkdev.h>
#include <linux/clk/spear.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of_platform.h>

6
drivers/clk/st/clkgen-fsyn.c
View File

@ -172,10 +172,10 @@ static const struct clkgen_quadfs_data st_fs660c32_D = {
* ST quad channel frequency synthesizer block
*
* @hw: handle between common and hardware-specific interfaces.
* @ndiv: regmap field for the ndiv control.
* @regs_base: base address of the configuration registers.
* @lock: spinlock.
*
* @data: local driver data
* @ndiv: regmap field for the ndiv control.
*/
struct st_clk_quadfs_pll {
struct clk_hw hw;
@ -426,7 +426,7 @@ static struct clk * __init st_clk_register_quadfs_pll(
* parent - fixed parent. No clk_set_parent support
*/
/**
/*
* struct st_clk_quadfs_fsynth - One clock output from a four channel digital
* frequency synthesizer (fsynth) block.
*

3
drivers/clk/st/clkgen-pll.c
View File

@ -130,12 +130,11 @@ static struct clkgen_pll_data st_pll4600c28_418_a9 = {
* parent - fixed parent. No clk_set_parent support
*/
/**
/*
* PLL clock that is integrated in the ClockGenA instances on the STiH415
* and STiH416.
*
* @hw: handle between common and hardware-specific interfaces.
* @type: PLL instance type.
* @regs_base: base of the PLL configuration register(s).
*
*/

5
drivers/clk/tegra/clk-tegra30.c
View File

@ -1104,12 +1104,9 @@ static void tegra30_cpu_out_of_reset(u32 cpu)
static void tegra30_enable_cpu_clock(u32 cpu)
{
unsigned int reg;
writel(CPU_CLOCK(cpu),
clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
reg = readl(clk_base +
TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
readl(clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
}
static void tegra30_disable_cpu_clock(u32 cpu)

1
drivers/clk/tegra/cvb.c
View File

@ -86,6 +86,7 @@ static int build_opp_table(struct device *dev, const struct cvb_table *table,
* @dev: the struct device * for which the OPP table is built
* @tables: array of CVB tables
* @count: size of the previously mentioned array
* @align: parameters of the regulator step and offset
* @process_id: process id of the HW module
* @speedo_id: speedo id of the HW module
* @speedo_value: speedo value of the HW module

3
drivers/clk/ti/clkt_dpll.c
View File

@ -269,8 +269,9 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
/**
* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
* @clk: struct clk * for a DPLL
* @hw: struct clk_hw containing the struct clk * for a DPLL
* @target_rate: desired DPLL clock rate
* @parent_rate: parent's DPLL clock rate
*
* Given a DPLL and a desired target rate, round the target rate to a
* possible, programmable rate for this DPLL. Attempts to select the

2
drivers/clk/ti/clockdomain.c
View File

@ -97,7 +97,7 @@ void omap2_clkops_disable_clkdm(struct clk_hw *hw)
/**
* omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
* @clk: OMAP clock struct ptr to use
* @hw: Pointer to clk_hw_omap used to obtain OMAP clock struct ptr to use
*
* Convert a clockdomain name stored in a struct clk 'clk' into a
* clockdomain pointer, and save it into the struct clk. Intended to be

2
drivers/clk/ti/dpll.c
View File

@ -151,7 +151,7 @@ static const struct clk_ops dpll_x2_ck_ops = {
/**
* _register_dpll - low level registration of a DPLL clock
* @hw: hardware clock definition for the clock
* @user: pointer to the hardware clock definition for the clock
* @node: device node for the clock
*
* Finalizes DPLL registration process. In case a failure (clk-ref or

20
drivers/clk/ti/dpll3xxx.c
View File

@ -125,7 +125,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
return f;
}
/*
/**
* _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
* @clk: pointer to a DPLL struct clk
*
@ -168,7 +168,7 @@ done:
return r;
}
/*
/**
* _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
* @clk: pointer to a DPLL struct clk
*
@ -204,7 +204,7 @@ static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
return r;
}
/*
/**
* _omap3_noncore_dpll_stop - instruct a DPLL to stop
* @clk: pointer to a DPLL struct clk
*
@ -291,7 +291,7 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
*sd_div = sd;
}
/*
/**
* _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
* @clk: struct clk * of DPLL to set
* @freqsel: FREQSEL value to set
@ -406,7 +406,8 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
/**
* omap3_dpll_recalc - recalculate DPLL rate
* @clk: DPLL struct clk
* @hw: struct clk_hw containing the DPLL struct clk
* @parent_rate: clock rate of the DPLL parent
*
* Recalculate and propagate the DPLL rate.
*/
@ -421,7 +422,7 @@ unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
/**
* omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
* @clk: pointer to a DPLL struct clk
* @hw: struct clk_hw containing then pointer to a DPLL struct clk
*
* Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
* The choice of modes depends on the DPLL's programmed rate: if it is
@ -470,7 +471,7 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)
/**
* omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
* @clk: pointer to a DPLL struct clk
* @hw: struct clk_hw containing then pointer to a DPLL struct clk
*
* Instructs a non-CORE DPLL to enter low-power stop. This function is
* intended for use in struct clkops. No return value.
@ -745,7 +746,8 @@ static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
/**
* omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
* @clk: DPLL output struct clk
* @hw: pointer struct clk_hw
* @parent_rate: clock rate of the DPLL parent
*
* Using parent clock DPLL data, look up DPLL state. If locked, set our
* rate to the dpll_clk * 2; otherwise, just use dpll_clk.
@ -913,7 +915,7 @@ const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
* omap3_dpll4_set_rate - set rate for omap3 per-dpll
* @hw: clock to change
* @rate: target rate for clock
* @parent_rate: rate of the parent clock
* @parent_rate: clock rate of the DPLL parent
*
* Check if the current SoC supports the per-dpll reprogram operation
* or not, and then do the rate change if supported. Returns -EINVAL

6
drivers/clk/ti/dpll44xx.c
View File

@ -102,7 +102,8 @@ static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
/**
* omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
* @clk: struct clk * of the DPLL to compute the rate for
* @hw: pointer to the clock to compute the rate for
* @parent_rate: clock rate of the DPLL parent
*
* Compute the output rate for the OMAP4 DPLL represented by @clk.
* Takes the REGM4XEN bit into consideration, which is needed for the
@ -134,8 +135,9 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
/**
* omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
* @clk: struct clk * of the DPLL to round a rate for
* @hw: struct hw_clk containing the struct clk * of the DPLL to round a rate for
* @target_rate: the desired rate of the DPLL
* @parent_rate: clock rate of the DPLL parent
*
* Compute the rate that would be programmed into the DPLL hardware
* for @clk if set_rate() were to be provided with the rate

2
drivers/clk/ti/gate.c
View File

@ -55,7 +55,7 @@ static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
/**
* omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
* from HSDivider PWRDN problem Implements Errata ID: i556.
* @clk: DPLL output struct clk
* @hw: DPLL output struct clk_hw
*
* 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
* dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset

7
drivers/clk/versatile/clk-icst.c
View File

@ -36,8 +36,9 @@
/**
* struct clk_icst - ICST VCO clock wrapper
* @hw: corresponding clock hardware entry
* @vcoreg: VCO register address
* @lockreg: VCO lock register address
* @map: register map
* @vcoreg_off: VCO register address
* @lockreg_off: VCO lock register address
* @params: parameters for this ICST instance
* @rate: current rate
* @ctype: the type of control register for the ICST
@ -428,7 +429,7 @@ static const struct icst_params icst307_params = {
.idx2s = icst307_idx2s,
};
/**
/*
* The core modules on the Integrator/AP and Integrator/CP have
* especially crippled ICST525 control.
*/

73
drivers/clk/zynq/clkc.c
View File

@ -103,7 +103,6 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
const char *clk_name, void __iomem *fclk_ctrl_reg,
const char **parents, int enable)
{
struct clk *clk;
u32 enable_reg;
char *mux_name;
char *div0_name;
@ -131,15 +130,15 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
if (!div1_name)
goto err_div1_name;
clk = clk_register_mux(NULL, mux_name, parents, 4,
clk_register_mux(NULL, mux_name, parents, 4,
CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
fclk_lock);
clk = clk_register_divider(NULL, div0_name, mux_name,
clk_register_divider(NULL, div0_name, mux_name,
0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
clk = clk_register_divider(NULL, div1_name, div0_name,
clk_register_divider(NULL, div1_name, div0_name,
CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
fclk_lock);
@ -176,7 +175,6 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
const char *clk_name1, void __iomem *clk_ctrl,
const char **parents, unsigned int two_gates)
{
struct clk *clk;
char *mux_name;
char *div_name;
spinlock_t *lock;
@ -189,10 +187,10 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
clk = clk_register_mux(NULL, mux_name, parents, 4,
clk_register_mux(NULL, mux_name, parents, 4,
CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
@ -217,7 +215,6 @@ static void __init zynq_clk_setup(struct device_node *np)
int i;
u32 tmp;
int ret;
struct clk *clk;
char *clk_name;
unsigned int fclk_enable = 0;
const char *clk_output_name[clk_max];
@ -257,19 +254,19 @@ static void __init zynq_clk_setup(struct device_node *np)
ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp);
/* PLLs */
clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
SLCR_PLL_STATUS, 0, &armpll_lock);
clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
SLCR_PLL_STATUS, 1, &ddrpll_lock);
clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
SLCR_PLL_STATUS, 2, &iopll_lock);
clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
@ -277,10 +274,10 @@ static void __init zynq_clk_setup(struct device_node *np)
/* CPU clocks */
tmp = readl(SLCR_621_TRUE) & 1;
clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
&armclk_lock);
clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
@ -288,20 +285,20 @@ static void __init zynq_clk_setup(struct device_node *np)
"cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
1, 2);
clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
"cpu_3or2x_div", CLK_IGNORE_UNUSED,
SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
2 + tmp);
clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
"cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
26, 0, &armclk_lock);
clk_prepare_enable(clks[cpu_2x]);
clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
4 + 2 * tmp);
clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
"cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
@ -324,23 +321,23 @@ static void __init zynq_clk_setup(struct device_node *np)
&swdtclk_lock);
/* DDR clocks */
clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
"ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
clk_prepare_enable(clks[ddr2x]);
clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
"ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
clk_prepare_enable(clks[ddr3x]);
clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
clk_register_divider(NULL, "dci_div1", "dci_div0",
CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
&dciclk_lock);
@ -385,17 +382,17 @@ static void __init zynq_clk_setup(struct device_node *np)
gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
idx);
}
clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
&gem0clk_lock);
clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
clk_register_divider(NULL, "gem0_div1", "gem0_div0",
CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
&gem0clk_lock);
clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
SLCR_GEM0_CLK_CTRL, 6, 1, 0,
&gem0clk_lock);
@ -410,17 +407,17 @@ static void __init zynq_clk_setup(struct device_node *np)
gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
idx);
}
clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
&gem1clk_lock);
clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
clk_register_divider(NULL, "gem1_div1", "gem1_div0",
CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
&gem1clk_lock);
clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
SLCR_GEM1_CLK_CTRL, 6, 1, 0,
&gem1clk_lock);
@ -442,27 +439,27 @@ static void __init zynq_clk_setup(struct device_node *np)
can_mio_mux_parents[i] = dummy_nm;
}
kfree(clk_name);
clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
clk_register_mux(NULL, "can_mux", periph_parents, 4,
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
&canclk_lock);
clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
clk_register_divider(NULL, "can_div0", "can_mux", 0,
SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
clk = clk_register_divider(NULL, "can_div1", "can_div0",
clk_register_divider(NULL, "can_div1", "can_div0",
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
&canclk_lock);
clk = clk_register_gate(NULL, "can0_gate", "can_div1",
clk_register_gate(NULL, "can0_gate", "can_div1",
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
&canclk_lock);
clk = clk_register_gate(NULL, "can1_gate", "can_div1",
clk_register_gate(NULL, "can1_gate", "can_div1",
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
&canclk_lock);
clk = clk_register_mux(NULL, "can0_mio_mux",
clk_register_mux(NULL, "can0_mio_mux",
can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
&canmioclk_lock);
clk = clk_register_mux(NULL, "can1_mio_mux",
clk_register_mux(NULL, "can1_mio_mux",
can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
0, &canmioclk_lock);
@ -482,13 +479,13 @@ static void __init zynq_clk_setup(struct device_node *np)
dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
idx);
}
clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
&dbgclk_lock);
clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
&dbgclk_lock);
clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],

12
drivers/clk/zynq/pll.c
View File

@ -173,12 +173,12 @@ static const struct clk_ops zynq_pll_ops = {
/**
* clk_register_zynq_pll() - Register PLL with the clock framework
* @name PLL name
* @parent Parent clock name
* @pll_ctrl Pointer to PLL control register
* @pll_status Pointer to PLL status register
* @lock_index Bit index to this PLL's lock status bit in @pll_status
* @lock Register lock
* @name: PLL name
* @parent: Parent clock name
* @pll_ctrl: Pointer to PLL control register
* @pll_status: Pointer to PLL status register
* @lock_index: Bit index to this PLL's lock status bit in @pll_status
* @lock: Register lock
* Returns handle to the registered clock.
*/
struct clk *clk_register_zynq_pll(const char *name, const char *parent,

1
drivers/clk/zynqmp/divider.c
View File

@ -35,6 +35,7 @@
* @is_frac: The divider is a fractional divider
* @clk_id: Id of clock
* @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2)
* @max_div: maximum supported divisor (fetched from firmware)
*/
struct zynqmp_clk_divider {
struct clk_hw hw;

19
include/dt-bindings/clock/mstar-msc313-mpll.h Normal file
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@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Output definitions for the MStar/SigmaStar MPLL
*
* Copyright (C) 2020 Daniel Palmer <daniel@thingy.jp>
*/
#ifndef _DT_BINDINGS_CLOCK_MSTAR_MSC313_MPLL_H
#define _DT_BINDINGS_CLOCK_MSTAR_MSC313_MPLL_H
#define MSTAR_MSC313_MPLL_DIV2 1
#define MSTAR_MSC313_MPLL_DIV3 2
#define MSTAR_MSC313_MPLL_DIV4 3
#define MSTAR_MSC313_MPLL_DIV5 4
#define MSTAR_MSC313_MPLL_DIV6 5
#define MSTAR_MSC313_MPLL_DIV7 6
#define MSTAR_MSC313_MPLL_DIV10 7
#endif

2
include/dt-bindings/clock/qcom,gcc-msm8998.h
View File

@ -184,6 +184,8 @@
#define GCC_MSS_MNOC_BIMC_AXI_CLK 175
#define GCC_BIMC_GFX_CLK 176
#define UFS_UNIPRO_CORE_CLK_SRC 177
#define GCC_MMSS_GPLL0_CLK 178
#define HMSS_GPLL0_CLK_SRC 179
#define PCIE_0_GDSC 0
#define UFS_GDSC 1

226
include/dt-bindings/clock/qcom,gcc-sc7280.h Normal file
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@ -0,0 +1,226 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H
/* GCC clocks */
#define GCC_GPLL0 0
#define GCC_GPLL0_OUT_EVEN 1
#define GCC_GPLL0_OUT_ODD 2
#define GCC_GPLL1 3
#define GCC_GPLL10 4
#define GCC_GPLL4 5
#define GCC_GPLL9 6
#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 7
#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 8
#define GCC_AGGRE_UFS_PHY_AXI_CLK 9
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 10
#define GCC_CAMERA_AHB_CLK 11
#define GCC_CAMERA_HF_AXI_CLK 12
#define GCC_CAMERA_SF_AXI_CLK 13
#define GCC_CAMERA_XO_CLK 14
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 15
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 16
#define GCC_CPUSS_AHB_CLK 17
#define GCC_CPUSS_AHB_CLK_SRC 18
#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 19
#define GCC_DDRSS_GPU_AXI_CLK 20
#define GCC_DDRSS_PCIE_SF_CLK 21
#define GCC_DISP_AHB_CLK 22
#define GCC_DISP_GPLL0_CLK_SRC 23
#define GCC_DISP_HF_AXI_CLK 24
#define GCC_DISP_SF_AXI_CLK 25
#define GCC_DISP_XO_CLK 26
#define GCC_GP1_CLK 27
#define GCC_GP1_CLK_SRC 28
#define GCC_GP2_CLK 29
#define GCC_GP2_CLK_SRC 30
#define GCC_GP3_CLK 31
#define GCC_GP3_CLK_SRC 32
#define GCC_GPU_CFG_AHB_CLK 33
#define GCC_GPU_GPLL0_CLK_SRC 34
#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
#define GCC_GPU_IREF_EN 36
#define GCC_GPU_MEMNOC_GFX_CLK 37
#define GCC_GPU_SNOC_DVM_GFX_CLK 38
#define GCC_PCIE0_PHY_RCHNG_CLK 39
#define GCC_PCIE1_PHY_RCHNG_CLK 40
#define GCC_PCIE_0_AUX_CLK 41
#define GCC_PCIE_0_AUX_CLK_SRC 42
#define GCC_PCIE_0_CFG_AHB_CLK 43
#define GCC_PCIE_0_MSTR_AXI_CLK 44
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 45
#define GCC_PCIE_0_PIPE_CLK 46
#define GCC_PCIE_0_PIPE_CLK_SRC 47
#define GCC_PCIE_0_SLV_AXI_CLK 48
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49
#define GCC_PCIE_1_AUX_CLK 50
#define GCC_PCIE_1_AUX_CLK_SRC 51
#define GCC_PCIE_1_CFG_AHB_CLK 52
#define GCC_PCIE_1_MSTR_AXI_CLK 53
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 54
#define GCC_PCIE_1_PIPE_CLK 55
#define GCC_PCIE_1_PIPE_CLK_SRC 56
#define GCC_PCIE_1_SLV_AXI_CLK 57
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 58
#define GCC_PCIE_THROTTLE_CORE_CLK 59
#define GCC_PDM2_CLK 60
#define GCC_PDM2_CLK_SRC 61
#define GCC_PDM_AHB_CLK 62
#define GCC_PDM_XO4_CLK 63
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 64
#define GCC_QMIP_CAMERA_RT_AHB_CLK 65
#define GCC_QMIP_DISP_AHB_CLK 66
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 67
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 68
#define GCC_QUPV3_WRAP0_CORE_CLK 69
#define GCC_QUPV3_WRAP0_S0_CLK 70
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 71
#define GCC_QUPV3_WRAP0_S1_CLK 72
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 73
#define GCC_QUPV3_WRAP0_S2_CLK 74
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 75
#define GCC_QUPV3_WRAP0_S3_CLK 76
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 77
#define GCC_QUPV3_WRAP0_S4_CLK 78
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 79
#define GCC_QUPV3_WRAP0_S5_CLK 80
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 81
#define GCC_QUPV3_WRAP0_S6_CLK 82
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 83
#define GCC_QUPV3_WRAP0_S7_CLK 84
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 85
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 86
#define GCC_QUPV3_WRAP1_CORE_CLK 87
#define GCC_QUPV3_WRAP1_S0_CLK 88
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89
#define GCC_QUPV3_WRAP1_S1_CLK 90
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91
#define GCC_QUPV3_WRAP1_S2_CLK 92
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93
#define GCC_QUPV3_WRAP1_S3_CLK 94
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95
#define GCC_QUPV3_WRAP1_S4_CLK 96
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97
#define GCC_QUPV3_WRAP1_S5_CLK 98
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99
#define GCC_QUPV3_WRAP1_S6_CLK 100
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 101
#define GCC_QUPV3_WRAP1_S7_CLK 102
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 103
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 104
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 105
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 106
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 107
#define GCC_SDCC1_AHB_CLK 108
#define GCC_SDCC1_APPS_CLK 109
#define GCC_SDCC1_APPS_CLK_SRC 110
#define GCC_SDCC1_ICE_CORE_CLK 111
#define GCC_SDCC1_ICE_CORE_CLK_SRC 112
#define GCC_SDCC2_AHB_CLK 113
#define GCC_SDCC2_APPS_CLK 114
#define GCC_SDCC2_APPS_CLK_SRC 115
#define GCC_SDCC4_AHB_CLK 116
#define GCC_SDCC4_APPS_CLK 117
#define GCC_SDCC4_APPS_CLK_SRC 118
#define GCC_SYS_NOC_CPUSS_AHB_CLK 119
#define GCC_THROTTLE_PCIE_AHB_CLK 120
#define GCC_TITAN_NRT_THROTTLE_CORE_CLK 121
#define GCC_TITAN_RT_THROTTLE_CORE_CLK 122
#define GCC_UFS_1_CLKREF_EN 123
#define GCC_UFS_PHY_AHB_CLK 124
#define GCC_UFS_PHY_AXI_CLK 125
#define GCC_UFS_PHY_AXI_CLK_SRC 126
#define GCC_UFS_PHY_ICE_CORE_CLK 127
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 128
#define GCC_UFS_PHY_PHY_AUX_CLK 129
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 130
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 131
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 132
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 133
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 134
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 135
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 136
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 137
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 138
#define GCC_USB30_PRIM_MASTER_CLK 139
#define GCC_USB30_PRIM_MASTER_CLK_SRC 140
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 141
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 142
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 143
#define GCC_USB30_PRIM_SLEEP_CLK 144
#define GCC_USB30_SEC_MASTER_CLK 145
#define GCC_USB30_SEC_MASTER_CLK_SRC 146
#define GCC_USB30_SEC_MOCK_UTMI_CLK 147
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 148
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 149
#define GCC_USB30_SEC_SLEEP_CLK 150
#define GCC_USB3_PRIM_PHY_AUX_CLK 151
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 152
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 153
#define GCC_USB3_PRIM_PHY_PIPE_CLK 154
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 155
#define GCC_USB3_SEC_PHY_AUX_CLK 156
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 157
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 158
#define GCC_USB3_SEC_PHY_PIPE_CLK 159
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 160
#define GCC_VIDEO_AHB_CLK 161
#define GCC_VIDEO_AXI0_CLK 162
#define GCC_VIDEO_MVP_THROTTLE_CORE_CLK 163
#define GCC_VIDEO_XO_CLK 164
#define GCC_GPLL0_MAIN_DIV_CDIV 165
#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 166
#define GCC_QSPI_CORE_CLK 167
#define GCC_QSPI_CORE_CLK_SRC 168
#define GCC_CFG_NOC_LPASS_CLK 169
#define GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC 170
#define GCC_MSS_CFG_AHB_CLK 171
#define GCC_MSS_OFFLINE_AXI_CLK 172
#define GCC_MSS_SNOC_AXI_CLK 173
#define GCC_MSS_Q6_MEMNOC_AXI_CLK 174
#define GCC_MSS_Q6SS_BOOT_CLK_SRC 175
#define GCC_AGGRE_USB3_SEC_AXI_CLK 176
#define GCC_AGGRE_NOC_PCIE_TBU_CLK 177
#define GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK 178
#define GCC_PCIE_CLKREF_EN 179
#define GCC_WPSS_AHB_CLK 180
#define GCC_WPSS_AHB_BDG_MST_CLK 181
#define GCC_WPSS_RSCP_CLK 182
#define GCC_EDP_CLKREF_EN 183
#define GCC_SEC_CTRL_CLK_SRC 184
/* GCC power domains */
#define GCC_PCIE_0_GDSC 0
#define GCC_PCIE_1_GDSC 1
#define GCC_UFS_PHY_GDSC 2
#define GCC_USB30_PRIM_GDSC 3
#define GCC_USB30_SEC_GDSC 4
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 5
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 6
#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 7
#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 8
#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 9
/* GCC resets */
#define GCC_PCIE_0_BCR 0
#define GCC_PCIE_0_PHY_BCR 1
#define GCC_PCIE_1_BCR 2
#define GCC_PCIE_1_PHY_BCR 3
#define GCC_QUSB2PHY_PRIM_BCR 4
#define GCC_QUSB2PHY_SEC_BCR 5
#define GCC_SDCC1_BCR 6
#define GCC_SDCC2_BCR 7
#define GCC_SDCC4_BCR 8
#define GCC_UFS_PHY_BCR 9
#define GCC_USB30_PRIM_BCR 10
#define GCC_USB30_SEC_BCR 11
#define GCC_USB3_DP_PHY_PRIM_BCR 12
#define GCC_USB3_PHY_PRIM_BCR 13
#define GCC_USB3PHY_PHY_PRIM_BCR 14
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 15
#endif

309
include/dt-bindings/clock/qcom,gcc-sc8180x.h Normal file
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@ -0,0 +1,309 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Ltd.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H
#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2
#define GCC_AGGRE_UFS_PHY_AXI_CLK 3
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4
#define GCC_AGGRE_USB3_MP_AXI_CLK 5
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 6
#define GCC_AGGRE_USB3_SEC_AXI_CLK 7
#define GCC_BOOT_ROM_AHB_CLK 8
#define GCC_CAMERA_HF_AXI_CLK 9
#define GCC_CAMERA_SF_AXI_CLK 10
#define GCC_CFG_NOC_USB3_MP_AXI_CLK 11
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
#define GCC_CPUSS_AHB_CLK 14
#define GCC_CPUSS_AHB_CLK_SRC 15
#define GCC_CPUSS_RBCPR_CLK 16
#define GCC_DDRSS_GPU_AXI_CLK 17
#define GCC_DISP_HF_AXI_CLK 18
#define GCC_DISP_SF_AXI_CLK 19
#define GCC_EMAC_AXI_CLK 20
#define GCC_EMAC_PTP_CLK 21
#define GCC_EMAC_PTP_CLK_SRC 22
#define GCC_EMAC_RGMII_CLK 23
#define GCC_EMAC_RGMII_CLK_SRC 24
#define GCC_EMAC_SLV_AHB_CLK 25
#define GCC_GP1_CLK 26
#define GCC_GP1_CLK_SRC 27
#define GCC_GP2_CLK 28
#define GCC_GP2_CLK_SRC 29
#define GCC_GP3_CLK 30
#define GCC_GP3_CLK_SRC 31
#define GCC_GP4_CLK 32
#define GCC_GP4_CLK_SRC 33
#define GCC_GP5_CLK 34
#define GCC_GP5_CLK_SRC 35
#define GCC_GPU_GPLL0_CLK_SRC 36
#define GCC_GPU_GPLL0_DIV_CLK_SRC 37
#define GCC_GPU_MEMNOC_GFX_CLK 38
#define GCC_GPU_SNOC_DVM_GFX_CLK 39
#define GCC_NPU_AT_CLK 40
#define GCC_NPU_AXI_CLK 41
#define GCC_NPU_AXI_CLK_SRC 42
#define GCC_NPU_GPLL0_CLK_SRC 43
#define GCC_NPU_GPLL0_DIV_CLK_SRC 44
#define GCC_NPU_TRIG_CLK 45
#define GCC_PCIE0_PHY_REFGEN_CLK 46
#define GCC_PCIE1_PHY_REFGEN_CLK 47
#define GCC_PCIE2_PHY_REFGEN_CLK 48
#define GCC_PCIE3_PHY_REFGEN_CLK 49
#define GCC_PCIE_0_AUX_CLK 50
#define GCC_PCIE_0_AUX_CLK_SRC 51
#define GCC_PCIE_0_CFG_AHB_CLK 52
#define GCC_PCIE_0_MSTR_AXI_CLK 53
#define GCC_PCIE_0_PIPE_CLK 54
#define GCC_PCIE_0_SLV_AXI_CLK 55
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 56
#define GCC_PCIE_1_AUX_CLK 57
#define GCC_PCIE_1_AUX_CLK_SRC 58
#define GCC_PCIE_1_CFG_AHB_CLK 59
#define GCC_PCIE_1_MSTR_AXI_CLK 60
#define GCC_PCIE_1_PIPE_CLK 61
#define GCC_PCIE_1_SLV_AXI_CLK 62
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 63
#define GCC_PCIE_2_AUX_CLK 64
#define GCC_PCIE_2_AUX_CLK_SRC 65
#define GCC_PCIE_2_CFG_AHB_CLK 66
#define GCC_PCIE_2_MSTR_AXI_CLK 67
#define GCC_PCIE_2_PIPE_CLK 68
#define GCC_PCIE_2_SLV_AXI_CLK 69
#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 70
#define GCC_PCIE_3_AUX_CLK 71
#define GCC_PCIE_3_AUX_CLK_SRC 72
#define GCC_PCIE_3_CFG_AHB_CLK 73
#define GCC_PCIE_3_MSTR_AXI_CLK 74
#define GCC_PCIE_3_PIPE_CLK 75
#define GCC_PCIE_3_SLV_AXI_CLK 76
#define GCC_PCIE_3_SLV_Q2A_AXI_CLK 77
#define GCC_PCIE_PHY_AUX_CLK 78
#define GCC_PCIE_PHY_REFGEN_CLK_SRC 79
#define GCC_PDM2_CLK 80
#define GCC_PDM2_CLK_SRC 81
#define GCC_PDM_AHB_CLK 82
#define GCC_PDM_XO4_CLK 83
#define GCC_PRNG_AHB_CLK 84
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 85
#define GCC_QMIP_CAMERA_RT_AHB_CLK 86
#define GCC_QMIP_DISP_AHB_CLK 87
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 88
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 89
#define GCC_QSPI_1_CNOC_PERIPH_AHB_CLK 90
#define GCC_QSPI_1_CORE_CLK 91
#define GCC_QSPI_1_CORE_CLK_SRC 92
#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 93
#define GCC_QSPI_CORE_CLK 94
#define GCC_QSPI_CORE_CLK_SRC 95
#define GCC_QUPV3_WRAP0_S0_CLK 96
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 97
#define GCC_QUPV3_WRAP0_S1_CLK 98
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 99
#define GCC_QUPV3_WRAP0_S2_CLK 100
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 101
#define GCC_QUPV3_WRAP0_S3_CLK 102
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 103
#define GCC_QUPV3_WRAP0_S4_CLK 104
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 105
#define GCC_QUPV3_WRAP0_S5_CLK 106
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 107
#define GCC_QUPV3_WRAP0_S6_CLK 108
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 109
#define GCC_QUPV3_WRAP0_S7_CLK 110
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 111
#define GCC_QUPV3_WRAP1_S0_CLK 112
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 113
#define GCC_QUPV3_WRAP1_S1_CLK 114
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 115
#define GCC_QUPV3_WRAP1_S2_CLK 116
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 117
#define GCC_QUPV3_WRAP1_S3_CLK 118
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 119
#define GCC_QUPV3_WRAP1_S4_CLK 120
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 121
#define GCC_QUPV3_WRAP1_S5_CLK 122
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 123
#define GCC_QUPV3_WRAP2_S0_CLK 124
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 125
#define GCC_QUPV3_WRAP2_S1_CLK 126
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 127
#define GCC_QUPV3_WRAP2_S2_CLK 128
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 129
#define GCC_QUPV3_WRAP2_S3_CLK 130
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 131
#define GCC_QUPV3_WRAP2_S4_CLK 132
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 133
#define GCC_QUPV3_WRAP2_S5_CLK 134
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 135
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 136
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 137
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 138
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 139
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 140
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 141
#define GCC_SDCC2_AHB_CLK 142
#define GCC_SDCC2_APPS_CLK 143
#define GCC_SDCC2_APPS_CLK_SRC 144
#define GCC_SDCC4_AHB_CLK 145
#define GCC_SDCC4_APPS_CLK 146
#define GCC_SDCC4_APPS_CLK_SRC 147
#define GCC_SYS_NOC_CPUSS_AHB_CLK 148
#define GCC_TSIF_AHB_CLK 149
#define GCC_TSIF_INACTIVITY_TIMERS_CLK 150
#define GCC_TSIF_REF_CLK 151
#define GCC_TSIF_REF_CLK_SRC 152
#define GCC_UFS_CARD_2_AHB_CLK 153
#define GCC_UFS_CARD_2_AXI_CLK 154
#define GCC_UFS_CARD_2_AXI_CLK_SRC 155
#define GCC_UFS_CARD_2_ICE_CORE_CLK 156
#define GCC_UFS_CARD_2_ICE_CORE_CLK_SRC 157
#define GCC_UFS_CARD_2_PHY_AUX_CLK 158
#define GCC_UFS_CARD_2_PHY_AUX_CLK_SRC 159
#define GCC_UFS_CARD_2_RX_SYMBOL_0_CLK 160
#define GCC_UFS_CARD_2_RX_SYMBOL_1_CLK 161
#define GCC_UFS_CARD_2_TX_SYMBOL_0_CLK 162
#define GCC_UFS_CARD_2_UNIPRO_CORE_CLK 163
#define GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC 164
#define GCC_UFS_CARD_AHB_CLK 165
#define GCC_UFS_CARD_AXI_CLK 166
#define GCC_UFS_CARD_AXI_CLK_SRC 167
#define GCC_UFS_CARD_AXI_HW_CTL_CLK 168
#define GCC_UFS_CARD_ICE_CORE_CLK 169
#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 170
#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 171
#define GCC_UFS_CARD_PHY_AUX_CLK 172
#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 173
#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 174
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 175
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 176
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 177
#define GCC_UFS_CARD_UNIPRO_CORE_CLK 178
#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 179
#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 180
#define GCC_UFS_PHY_AHB_CLK 181
#define GCC_UFS_PHY_AXI_CLK 182
#define GCC_UFS_PHY_AXI_CLK_SRC 183
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 184
#define GCC_UFS_PHY_ICE_CORE_CLK 185
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 186
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 187
#define GCC_UFS_PHY_PHY_AUX_CLK 188
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 189
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 190
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 191
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 192
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 193
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 194
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 195
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 196
#define GCC_USB30_MP_MASTER_CLK 197
#define GCC_USB30_MP_MASTER_CLK_SRC 198
#define GCC_USB30_MP_MOCK_UTMI_CLK 199
#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 200
#define GCC_USB30_MP_SLEEP_CLK 201
#define GCC_USB30_PRIM_MASTER_CLK 202
#define GCC_USB30_PRIM_MASTER_CLK_SRC 203
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 204
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 205
#define GCC_USB30_PRIM_SLEEP_CLK 206
#define GCC_USB30_SEC_MASTER_CLK 207
#define GCC_USB30_SEC_MASTER_CLK_SRC 208
#define GCC_USB30_SEC_MOCK_UTMI_CLK 209
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 210
#define GCC_USB30_SEC_SLEEP_CLK 211
#define GCC_USB3_MP_PHY_AUX_CLK 212
#define GCC_USB3_MP_PHY_AUX_CLK_SRC 213
#define GCC_USB3_MP_PHY_COM_AUX_CLK 214
#define GCC_USB3_MP_PHY_PIPE_0_CLK 215
#define GCC_USB3_MP_PHY_PIPE_1_CLK 216
#define GCC_USB3_PRIM_PHY_AUX_CLK 217
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 218
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 219
#define GCC_USB3_PRIM_PHY_PIPE_CLK 220
#define GCC_USB3_SEC_PHY_AUX_CLK 221
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 222
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 223
#define GCC_USB3_SEC_PHY_PIPE_CLK 224
#define GCC_VIDEO_AXI0_CLK 225
#define GCC_VIDEO_AXI1_CLK 226
#define GCC_VIDEO_AXIC_CLK 227
#define GPLL0 228
#define GPLL0_OUT_EVEN 229
#define GPLL1 230
#define GPLL4 231
#define GPLL7 232
#define GCC_PCIE_0_CLKREF_CLK 233
#define GCC_PCIE_1_CLKREF_CLK 234
#define GCC_PCIE_2_CLKREF_CLK 235
#define GCC_PCIE_3_CLKREF_CLK 236
#define GCC_USB3_PRIM_CLKREF_CLK 237
#define GCC_USB3_SEC_CLKREF_CLK 238
#define GCC_EMAC_BCR 0
#define GCC_GPU_BCR 1
#define GCC_MMSS_BCR 2
#define GCC_NPU_BCR 3
#define GCC_PCIE_0_BCR 4
#define GCC_PCIE_0_PHY_BCR 5
#define GCC_PCIE_1_BCR 6
#define GCC_PCIE_1_PHY_BCR 7
#define GCC_PCIE_2_BCR 8
#define GCC_PCIE_2_PHY_BCR 9
#define GCC_PCIE_3_BCR 10
#define GCC_PCIE_3_PHY_BCR 11
#define GCC_PCIE_PHY_BCR 12
#define GCC_PDM_BCR 13
#define GCC_PRNG_BCR 14
#define GCC_QSPI_1_BCR 15
#define GCC_QSPI_BCR 16
#define GCC_QUPV3_WRAPPER_0_BCR 17
#define GCC_QUPV3_WRAPPER_1_BCR 18
#define GCC_QUPV3_WRAPPER_2_BCR 19
#define GCC_QUSB2PHY_5_BCR 20
#define GCC_QUSB2PHY_MP0_BCR 21
#define GCC_QUSB2PHY_MP1_BCR 22
#define GCC_QUSB2PHY_PRIM_BCR 23
#define GCC_QUSB2PHY_SEC_BCR 24
#define GCC_USB3_PHY_PRIM_SP0_BCR 25
#define GCC_USB3_PHY_PRIM_SP1_BCR 26
#define GCC_USB3_DP_PHY_PRIM_SP0_BCR 27
#define GCC_USB3_DP_PHY_PRIM_SP1_BCR 28
#define GCC_USB3_PHY_SEC_BCR 29
#define GCC_USB3PHY_PHY_SEC_BCR 30
#define GCC_SDCC2_BCR 31
#define GCC_SDCC4_BCR 32
#define GCC_TSIF_BCR 33
#define GCC_UFS_CARD_2_BCR 34
#define GCC_UFS_CARD_BCR 35
#define GCC_UFS_PHY_BCR 36
#define GCC_USB30_MP_BCR 37
#define GCC_USB30_PRIM_BCR 38
#define GCC_USB30_SEC_BCR 39
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 40
#define GCC_VIDEO_AXIC_CLK_BCR 41
#define GCC_VIDEO_AXI0_CLK_BCR 42
#define GCC_VIDEO_AXI1_CLK_BCR 43
#define GCC_USB3_DP_PHY_SEC_BCR 44
/* GCC GDSCRs */
#define EMAC_GDSC 0
#define PCIE_0_GDSC 1
#define PCIE_1_GDSC 2
#define PCIE_2_GDSC 3
#define PCIE_3_GDSC 4
#define UFS_CARD_2_GDSC 5
#define UFS_CARD_GDSC 6
#define UFS_PHY_GDSC 7
#define USB30_MP_GDSC 8
#define USB30_PRIM_GDSC 9
#define USB30_SEC_GDSC 10
#endif

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2020-2021, Linaro Limited
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H
/* GCC HW clocks */
#define CORE_BI_PLL_TEST_SE 0
#define PCIE_0_PIPE_CLK 1
#define PCIE_1_PIPE_CLK 2
#define UFS_CARD_RX_SYMBOL_0_CLK 3
#define UFS_CARD_RX_SYMBOL_1_CLK 4
#define UFS_CARD_TX_SYMBOL_0_CLK 5
#define UFS_PHY_RX_SYMBOL_0_CLK 6
#define UFS_PHY_RX_SYMBOL_1_CLK 7
#define UFS_PHY_TX_SYMBOL_0_CLK 8
#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 9
#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK 10
/* GCC clocks */
#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 11
#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 12
#define GCC_AGGRE_NOC_PCIE_TBU_CLK 13
#define GCC_AGGRE_UFS_CARD_AXI_CLK 14
#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 15
#define GCC_AGGRE_UFS_PHY_AXI_CLK 16
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 17
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 18
#define GCC_AGGRE_USB3_SEC_AXI_CLK 19
#define GCC_BOOT_ROM_AHB_CLK 20
#define GCC_CAMERA_HF_AXI_CLK 21
#define GCC_CAMERA_SF_AXI_CLK 22
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 24
#define GCC_DDRSS_GPU_AXI_CLK 25
#define GCC_DDRSS_PCIE_SF_TBU_CLK 26
#define GCC_DISP_HF_AXI_CLK 27
#define GCC_DISP_SF_AXI_CLK 28
#define GCC_GP1_CLK 29
#define GCC_GP1_CLK_SRC 30
#define GCC_GP2_CLK 31
#define GCC_GP2_CLK_SRC 32
#define GCC_GP3_CLK 33
#define GCC_GP3_CLK_SRC 34
#define GCC_GPLL0 35
#define GCC_GPLL0_OUT_EVEN 36
#define GCC_GPLL4 37
#define GCC_GPLL9 38
#define GCC_GPU_GPLL0_CLK_SRC 39
#define GCC_GPU_GPLL0_DIV_CLK_SRC 40
#define GCC_GPU_IREF_EN 41
#define GCC_GPU_MEMNOC_GFX_CLK 42
#define GCC_GPU_SNOC_DVM_GFX_CLK 43
#define GCC_PCIE0_PHY_RCHNG_CLK 44
#define GCC_PCIE1_PHY_RCHNG_CLK 45
#define GCC_PCIE_0_AUX_CLK 46
#define GCC_PCIE_0_AUX_CLK_SRC 47
#define GCC_PCIE_0_CFG_AHB_CLK 48
#define GCC_PCIE_0_CLKREF_EN 49
#define GCC_PCIE_0_MSTR_AXI_CLK 50
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 51
#define GCC_PCIE_0_PIPE_CLK 52
#define GCC_PCIE_0_PIPE_CLK_SRC 53
#define GCC_PCIE_0_SLV_AXI_CLK 54
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55
#define GCC_PCIE_1_AUX_CLK 56
#define GCC_PCIE_1_AUX_CLK_SRC 57
#define GCC_PCIE_1_CFG_AHB_CLK 58
#define GCC_PCIE_1_CLKREF_EN 59
#define GCC_PCIE_1_MSTR_AXI_CLK 60
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 61
#define GCC_PCIE_1_PIPE_CLK 62
#define GCC_PCIE_1_PIPE_CLK_SRC 63
#define GCC_PCIE_1_SLV_AXI_CLK 64
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 65
#define GCC_PDM2_CLK 66
#define GCC_PDM2_CLK_SRC 67
#define GCC_PDM_AHB_CLK 68
#define GCC_PDM_XO4_CLK 69
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 70
#define GCC_QMIP_CAMERA_RT_AHB_CLK 71
#define GCC_QMIP_DISP_AHB_CLK 72
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 73
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 74
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 75
#define GCC_QUPV3_WRAP0_CORE_CLK 76
#define GCC_QUPV3_WRAP0_S0_CLK 77
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 78
#define GCC_QUPV3_WRAP0_S1_CLK 79
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 80
#define GCC_QUPV3_WRAP0_S2_CLK 81
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 82
#define GCC_QUPV3_WRAP0_S3_CLK 83
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 84
#define GCC_QUPV3_WRAP0_S4_CLK 85
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 86
#define GCC_QUPV3_WRAP0_S5_CLK 87
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 88
#define GCC_QUPV3_WRAP0_S6_CLK 89
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 90
#define GCC_QUPV3_WRAP0_S7_CLK 91
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 92
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 93
#define GCC_QUPV3_WRAP1_CORE_CLK 94
#define GCC_QUPV3_WRAP1_S0_CLK 95
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 96
#define GCC_QUPV3_WRAP1_S1_CLK 97
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 98
#define GCC_QUPV3_WRAP1_S2_CLK 99
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 100
#define GCC_QUPV3_WRAP1_S3_CLK 101
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 102
#define GCC_QUPV3_WRAP1_S4_CLK 103
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 104
#define GCC_QUPV3_WRAP1_S5_CLK 105
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 106
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 107
#define GCC_QUPV3_WRAP2_CORE_CLK 108
#define GCC_QUPV3_WRAP2_S0_CLK 109
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110
#define GCC_QUPV3_WRAP2_S1_CLK 111
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112
#define GCC_QUPV3_WRAP2_S2_CLK 113
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114
#define GCC_QUPV3_WRAP2_S3_CLK 115
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116
#define GCC_QUPV3_WRAP2_S4_CLK 117
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118
#define GCC_QUPV3_WRAP2_S5_CLK 119
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 121
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 122
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 123
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 124
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 125
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 126
#define GCC_SDCC2_AHB_CLK 127
#define GCC_SDCC2_APPS_CLK 128
#define GCC_SDCC2_APPS_CLK_SRC 129
#define GCC_SDCC4_AHB_CLK 130
#define GCC_SDCC4_APPS_CLK 131
#define GCC_SDCC4_APPS_CLK_SRC 132
#define GCC_THROTTLE_PCIE_AHB_CLK 133
#define GCC_UFS_1_CLKREF_EN 134
#define GCC_UFS_CARD_AHB_CLK 135
#define GCC_UFS_CARD_AXI_CLK 136
#define GCC_UFS_CARD_AXI_CLK_SRC 137
#define GCC_UFS_CARD_AXI_HW_CTL_CLK 138
#define GCC_UFS_CARD_ICE_CORE_CLK 139
#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 140
#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 141
#define GCC_UFS_CARD_PHY_AUX_CLK 142
#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 143
#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 144
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 145
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 146
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 147
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 148
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 149
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 150
#define GCC_UFS_CARD_UNIPRO_CORE_CLK 151
#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 152
#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 153
#define GCC_UFS_PHY_AHB_CLK 154
#define GCC_UFS_PHY_AXI_CLK 155
#define GCC_UFS_PHY_AXI_CLK_SRC 156
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 157
#define GCC_UFS_PHY_ICE_CORE_CLK 158
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 159
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 160
#define GCC_UFS_PHY_PHY_AUX_CLK 161
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 162
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 163
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 165
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 166
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 167
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 169
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 170
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 171
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 172
#define GCC_USB30_PRIM_MASTER_CLK 173
#define GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON 174
#define GCC_USB30_PRIM_MASTER_CLK_SRC 175
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 176
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 177
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 178
#define GCC_USB30_PRIM_SLEEP_CLK 179
#define GCC_USB30_SEC_MASTER_CLK 180
#define GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON 181
#define GCC_USB30_SEC_MASTER_CLK_SRC 182
#define GCC_USB30_SEC_MOCK_UTMI_CLK 183
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 184
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 185
#define GCC_USB30_SEC_SLEEP_CLK 186
#define GCC_USB3_PRIM_PHY_AUX_CLK 187
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 188
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 189
#define GCC_USB3_PRIM_PHY_PIPE_CLK 190
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 191
#define GCC_USB3_SEC_CLKREF_EN 192
#define GCC_USB3_SEC_PHY_AUX_CLK 193
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 194
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 195
#define GCC_USB3_SEC_PHY_PIPE_CLK 196
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 197
#define GCC_VIDEO_AXI0_CLK 198
#define GCC_VIDEO_AXI1_CLK 199
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_DISPLAY_BCR 1
#define GCC_GPU_BCR 2
#define GCC_MMSS_BCR 3
#define GCC_PCIE_0_BCR 4
#define GCC_PCIE_0_LINK_DOWN_BCR 5
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
#define GCC_PCIE_0_PHY_BCR 7
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
#define GCC_PCIE_1_BCR 9
#define GCC_PCIE_1_LINK_DOWN_BCR 10
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
#define GCC_PCIE_1_PHY_BCR 12
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
#define GCC_PCIE_PHY_CFG_AHB_BCR 14
#define GCC_PCIE_PHY_COM_BCR 15
#define GCC_PDM_BCR 16
#define GCC_QUPV3_WRAPPER_0_BCR 17
#define GCC_QUPV3_WRAPPER_1_BCR 18
#define GCC_QUPV3_WRAPPER_2_BCR 19
#define GCC_QUSB2PHY_PRIM_BCR 20
#define GCC_QUSB2PHY_SEC_BCR 21
#define GCC_SDCC2_BCR 22
#define GCC_SDCC4_BCR 23
#define GCC_UFS_CARD_BCR 24
#define GCC_UFS_PHY_BCR 25
#define GCC_USB30_PRIM_BCR 26
#define GCC_USB30_SEC_BCR 27
#define GCC_USB3_DP_PHY_PRIM_BCR 28
#define GCC_USB3_DP_PHY_SEC_BCR 29
#define GCC_USB3_PHY_PRIM_BCR 30
#define GCC_USB3_PHY_SEC_BCR 31
#define GCC_USB3PHY_PHY_PRIM_BCR 32
#define GCC_USB3PHY_PHY_SEC_BCR 33
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 34
#define GCC_VIDEO_AXI0_CLK_ARES 35
#define GCC_VIDEO_AXI1_CLK_ARES 36
#define GCC_VIDEO_BCR 37
/* GCC power domains */
#define PCIE_0_GDSC 0
#define PCIE_1_GDSC 1
#define UFS_CARD_GDSC 2
#define UFS_PHY_GDSC 3
#define USB30_PRIM_GDSC 4
#define USB30_SEC_GDSC 5
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 6
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 7
#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 8
#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 9
#endif

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include/dt-bindings/clock/qcom,gpucc-sdm660.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2020, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
*/
#ifndef _DT_BINDINGS_CLK_SDM_GPUCC_660_H
#define _DT_BINDINGS_CLK_SDM_GPUCC_660_H
#define GPUCC_CXO_CLK 0
#define GPU_PLL0_PLL 1
#define GPU_PLL1_PLL 2
#define GFX3D_CLK_SRC 3
#define RBCPR_CLK_SRC 4
#define RBBMTIMER_CLK_SRC 5
#define GPUCC_RBCPR_CLK 6
#define GPUCC_GFX3D_CLK 7
#define GPUCC_RBBMTIMER_CLK 8
#define GPU_CX_GDSC 0
#define GPU_GX_GDSC 1
#define GPU_CX_BCR 0
#define GPU_GX_BCR 1
#define RBCPR_BCR 2
#define SPDM_BCR 3
#endif

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_MSM_MMCC_660_H
#define _DT_BINDINGS_CLK_MSM_MMCC_660_H
#define AHB_CLK_SRC 0
#define BYTE0_CLK_SRC 1
#define BYTE1_CLK_SRC 2
#define CAMSS_GP0_CLK_SRC 3
#define CAMSS_GP1_CLK_SRC 4
#define CCI_CLK_SRC 5
#define CPP_CLK_SRC 6
#define CSI0_CLK_SRC 7
#define CSI0PHYTIMER_CLK_SRC 8
#define CSI1_CLK_SRC 9
#define CSI1PHYTIMER_CLK_SRC 10
#define CSI2_CLK_SRC 11
#define CSI2PHYTIMER_CLK_SRC 12
#define CSI3_CLK_SRC 13
#define CSIPHY_CLK_SRC 14
#define DP_AUX_CLK_SRC 15
#define DP_CRYPTO_CLK_SRC 16
#define DP_GTC_CLK_SRC 17
#define DP_LINK_CLK_SRC 18
#define DP_PIXEL_CLK_SRC 19
#define ESC0_CLK_SRC 20
#define ESC1_CLK_SRC 21
#define JPEG0_CLK_SRC 22
#define MCLK0_CLK_SRC 23
#define MCLK1_CLK_SRC 24
#define MCLK2_CLK_SRC 25
#define MCLK3_CLK_SRC 26
#define MDP_CLK_SRC 27
#define MMPLL0_PLL 28
#define MMPLL10_PLL 29
#define MMPLL1_PLL 30
#define MMPLL3_PLL 31
#define MMPLL4_PLL 32
#define MMPLL5_PLL 33
#define MMPLL6_PLL 34
#define MMPLL7_PLL 35
#define MMPLL8_PLL 36
#define BIMC_SMMU_AHB_CLK 37
#define BIMC_SMMU_AXI_CLK 38
#define CAMSS_AHB_CLK 39
#define CAMSS_CCI_AHB_CLK 40
#define CAMSS_CCI_CLK 41
#define CAMSS_CPHY_CSID0_CLK 42
#define CAMSS_CPHY_CSID1_CLK 43
#define CAMSS_CPHY_CSID2_CLK 44
#define CAMSS_CPHY_CSID3_CLK 45
#define CAMSS_CPP_AHB_CLK 46
#define CAMSS_CPP_AXI_CLK 47
#define CAMSS_CPP_CLK 48
#define CAMSS_CPP_VBIF_AHB_CLK 49
#define CAMSS_CSI0_AHB_CLK 50
#define CAMSS_CSI0_CLK 51
#define CAMSS_CSI0PHYTIMER_CLK 52
#define CAMSS_CSI0PIX_CLK 53
#define CAMSS_CSI0RDI_CLK 54
#define CAMSS_CSI1_AHB_CLK 55
#define CAMSS_CSI1_CLK 56
#define CAMSS_CSI1PHYTIMER_CLK 57
#define CAMSS_CSI1PIX_CLK 58
#define CAMSS_CSI1RDI_CLK 59
#define CAMSS_CSI2_AHB_CLK 60
#define CAMSS_CSI2_CLK 61
#define CAMSS_CSI2PHYTIMER_CLK 62
#define CAMSS_CSI2PIX_CLK 63
#define CAMSS_CSI2RDI_CLK 64
#define CAMSS_CSI3_AHB_CLK 65
#define CAMSS_CSI3_CLK 66
#define CAMSS_CSI3PIX_CLK 67
#define CAMSS_CSI3RDI_CLK 68
#define CAMSS_CSI_VFE0_CLK 69
#define CAMSS_CSI_VFE1_CLK 70
#define CAMSS_CSIPHY0_CLK 71
#define CAMSS_CSIPHY1_CLK 72
#define CAMSS_CSIPHY2_CLK 73
#define CAMSS_GP0_CLK 74
#define CAMSS_GP1_CLK 75
#define CAMSS_ISPIF_AHB_CLK 76
#define CAMSS_JPEG0_CLK 77
#define CAMSS_JPEG_AHB_CLK 78
#define CAMSS_JPEG_AXI_CLK 79
#define CAMSS_MCLK0_CLK 80
#define CAMSS_MCLK1_CLK 81
#define CAMSS_MCLK2_CLK 82
#define CAMSS_MCLK3_CLK 83
#define CAMSS_MICRO_AHB_CLK 84
#define CAMSS_TOP_AHB_CLK 85
#define CAMSS_VFE0_AHB_CLK 86
#define CAMSS_VFE0_CLK 87
#define CAMSS_VFE0_STREAM_CLK 88
#define CAMSS_VFE1_AHB_CLK 89
#define CAMSS_VFE1_CLK 90
#define CAMSS_VFE1_STREAM_CLK 91
#define CAMSS_VFE_VBIF_AHB_CLK 92
#define CAMSS_VFE_VBIF_AXI_CLK 93
#define CSIPHY_AHB2CRIF_CLK 94
#define CXO_CLK 95
#define MDSS_AHB_CLK 96
#define MDSS_AXI_CLK 97
#define MDSS_BYTE0_CLK 98
#define MDSS_BYTE0_INTF_CLK 99
#define MDSS_BYTE0_INTF_DIV_CLK 100
#define MDSS_BYTE1_CLK 101
#define MDSS_BYTE1_INTF_CLK 102
#define MDSS_DP_AUX_CLK 103
#define MDSS_DP_CRYPTO_CLK 104
#define MDSS_DP_GTC_CLK 105
#define MDSS_DP_LINK_CLK 106
#define MDSS_DP_LINK_INTF_CLK 107
#define MDSS_DP_PIXEL_CLK 108
#define MDSS_ESC0_CLK 109
#define MDSS_ESC1_CLK 110
#define MDSS_HDMI_DP_AHB_CLK 111
#define MDSS_MDP_CLK 112
#define MDSS_PCLK0_CLK 113
#define MDSS_PCLK1_CLK 114
#define MDSS_ROT_CLK 115
#define MDSS_VSYNC_CLK 116
#define MISC_AHB_CLK 117
#define MISC_CXO_CLK 118
#define MNOC_AHB_CLK 119
#define SNOC_DVM_AXI_CLK 120
#define THROTTLE_CAMSS_AHB_CLK 121
#define THROTTLE_CAMSS_AXI_CLK 122
#define THROTTLE_MDSS_AHB_CLK 123
#define THROTTLE_MDSS_AXI_CLK 124
#define THROTTLE_VIDEO_AHB_CLK 125
#define THROTTLE_VIDEO_AXI_CLK 126
#define VIDEO_AHB_CLK 127
#define VIDEO_AXI_CLK 128
#define VIDEO_CORE_CLK 129
#define VIDEO_SUBCORE0_CLK 130
#define PCLK0_CLK_SRC 131
#define PCLK1_CLK_SRC 132
#define ROT_CLK_SRC 133
#define VFE0_CLK_SRC 134
#define VFE1_CLK_SRC 135
#define VIDEO_CORE_CLK_SRC 136
#define VSYNC_CLK_SRC 137
#define MDSS_BYTE1_INTF_DIV_CLK 138
#define AXI_CLK_SRC 139
#define VENUS_GDSC 0
#define VENUS_CORE0_GDSC 1
#define MDSS_GDSC 2
#define CAMSS_TOP_GDSC 3
#define CAMSS_VFE0_GDSC 4
#define CAMSS_VFE1_GDSC 5
#define CAMSS_CPP_GDSC 6
#define BIMC_SMMU_GDSC 7
#define CAMSS_MICRO_BCR 0
#endif

2
include/dt-bindings/clock/qcom,videocc-sm8250.h
View File

@ -16,6 +16,8 @@
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 6
#define VIDEO_CC_PLL0 7
#define VIDEO_CC_PLL1 8
#define VIDEO_CC_MVS0_DIV_CLK_SRC 9
#define VIDEO_CC_MVS0_CLK 10
/* VIDEO_CC resets */
#define VIDEO_CC_CVP_INTERFACE_BCR 0

4
include/linux/clk-provider.h
View File

@ -941,7 +941,9 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
/**
* struct clk_fractional_divider - adjustable fractional divider clock
*

23
include/linux/clk/spear.h Normal file
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@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2020 STMicroelectronics - All Rights Reserved
*
* Author: Lee Jones <lee.jones@linaro.org>
*/
#ifndef __LINUX_CLK_SPEAR_H
#define __LINUX_CLK_SPEAR_H
#ifdef CONFIG_MACH_SPEAR1310
void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base);
#else
static inline void spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) {}
#endif
#ifdef CONFIG_MACH_SPEAR1340
void __init spear1340_clk_init(void __iomem *misc_base);
#else
static inline void spear1340_clk_init(void __iomem *misc_base) {}
#endif
#endif