drm/i915: Consolidate legacy semaphore initialization
Replace per-engine initialization with a common half-programatic, half-data driven code for ease of maintenance and compactness. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -2932,6 +2932,54 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
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} else if (INTEL_GEN(dev_priv) >= 6) {
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engine->semaphore.sync_to = gen6_ring_sync;
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engine->semaphore.signal = gen6_signal;
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/*
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* The current semaphore is only applied on pre-gen8
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* platform. And there is no VCS2 ring on the pre-gen8
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* platform. So the semaphore between RCS and VCS2 is
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* initialized as INVALID. Gen8 will initialize the
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* sema between VCS2 and RCS later.
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*/
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for (i = 0; i < I915_NUM_ENGINES; i++) {
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static const struct {
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u32 wait_mbox;
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i915_reg_t mbox_reg;
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} sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = {
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[RCS] = {
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[VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC },
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[BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC },
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[VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
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},
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[VCS] = {
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[RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC },
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[BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC },
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[VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
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},
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[BCS] = {
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[RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC },
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[VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC },
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[VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
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},
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[VECS] = {
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[RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
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[VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
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[BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
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},
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};
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u32 wait_mbox;
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i915_reg_t mbox_reg;
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if (i == engine->id || i == VCS2) {
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wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
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mbox_reg = GEN6_NOSYNC;
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} else {
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wait_mbox = sem_data[engine->id][i].wait_mbox;
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mbox_reg = sem_data[engine->id][i].mbox_reg;
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}
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engine->semaphore.mbox.wait[i] = wait_mbox;
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engine->semaphore.mbox.signal[i] = mbox_reg;
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}
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}
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}
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@ -3004,25 +3052,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
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if (IS_GEN6(dev_priv))
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engine->flush = gen6_render_ring_flush;
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engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
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if (i915_semaphore_is_enabled(dev_priv)) {
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/*
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* The current semaphore is only applied on pre-gen8
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* platform. And there is no VCS2 ring on the pre-gen8
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* platform. So the semaphore between RCS and VCS2 is
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* initialized as INVALID. Gen8 will initialize the
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* sema between VCS2 and RCS later.
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*/
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engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
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engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
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engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
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engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
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engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
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engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
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engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
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engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
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engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
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engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
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}
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} else if (IS_GEN5(dev_priv)) {
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engine->add_request = pc_render_add_request;
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engine->flush = gen4_render_ring_flush;
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@ -3102,18 +3131,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
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GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
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} else {
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engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
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if (i915_semaphore_is_enabled(dev_priv)) {
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engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
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engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
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engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
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engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
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engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
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engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
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engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
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engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
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engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
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engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
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}
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}
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} else {
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engine->mmio_base = BSD_RING_BASE;
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@ -3170,25 +3187,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
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GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
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} else {
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engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
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if (i915_semaphore_is_enabled(dev_priv)) {
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/*
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* The current semaphore is only applied on pre-gen8
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* platform. And there is no VCS2 ring on the pre-gen8
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* platform. So the semaphore between BCS and VCS2 is
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* initialized as INVALID. Gen8 will initialize the
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* sema between BCS and VCS2 later.
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*/
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engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
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engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
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engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
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engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
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engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
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engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
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engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
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engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
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engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
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engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
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}
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}
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return intel_init_ring_buffer(dev, engine);
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@ -3216,18 +3214,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
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engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
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engine->irq_get = hsw_vebox_get_irq;
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engine->irq_put = hsw_vebox_put_irq;
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if (i915_semaphore_is_enabled(dev_priv)) {
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engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
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engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
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engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
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engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
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engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
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engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
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engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
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engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
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engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
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engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
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}
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}
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return intel_init_ring_buffer(dev, engine);
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