forked from Minki/linux
[ARM] 4109/2: Add support for the RealView/EB MPCore revC platform
The kernel originally supported revB only. This patch enables revC by default and adds a config option for building the kernel for the revB platform. Since the SCU base address was hard-coded in the proc-v6.S file (and only valid for RealView/EB revB), this patch also adds a more generic support for defining the SCU information. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -16,4 +16,14 @@ config REALVIEW_MPCORE
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kernel built with this option enabled is not compatible with
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other tiles.
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config REALVIEW_MPCORE_REVB
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bool "Support MPcore RevB tile"
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depends on REALVIEW_MPCORE
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default n
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help
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Enable support for the MPCore RevB tile on the Realview platform.
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Since there are device address differences, a
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kernel built with this option enabled is not compatible with
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other tiles.
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endmenu
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@ -152,9 +152,9 @@ static void __init gic_init_irq(void)
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#ifdef CONFIG_REALVIEW_MPCORE
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unsigned int pldctrl;
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writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
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pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + 0xd8);
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pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
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pldctrl |= 0x00800000; /* New irq mode */
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writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + 0xd8);
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writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
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writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
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#endif
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gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
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@ -14,10 +14,13 @@
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/elf.h>
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#include <asm/hardware/arm_scu.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#ifdef CONFIG_SMP
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#include <asm/hardware/arm_scu.h>
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#endif
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#include "proc-macros.S"
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#define D_CACHE_LINE_SIZE 32
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@ -183,8 +186,7 @@ __v6_setup:
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/* Set up the SCU on core 0 only */
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mrc p15, 0, r0, c0, c0, 5 @ CPU core number
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ands r0, r0, #15
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moveq r0, #0x10000000 @ SCU_BASE
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orreq r0, r0, #0x00100000
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ldreq r0, =SCU_BASE
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ldreq r5, [r0, #SCU_CTRL]
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orreq r5, r5, #1
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streq r5, [r0, #SCU_CTRL]
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@ -26,7 +26,7 @@
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#include <asm/arch/platform.h>
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/* macro to get at IO space when running virtually */
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#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
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#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
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#define __io_address(n) __io(IO_ADDRESS(n))
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#endif
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@ -207,11 +207,21 @@
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#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
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#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
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#else
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#ifdef CONFIG_REALVIEW_MPCORE_REVB
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#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
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#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_TWD_BASE 0x10100700
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#define REALVIEW_TWD_SIZE 0x00000100
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#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
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#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
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#else
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#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */
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#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_TWD_BASE 0x1F000700
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#define REALVIEW_TWD_SIZE 0x00000100
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#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
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#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
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#endif
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#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
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#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
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#endif
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8
include/asm-arm/arch-realview/scu.h
Normal file
8
include/asm-arm/arch-realview/scu.h
Normal file
@ -0,0 +1,8 @@
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#ifndef __ASMARM_ARCH_SCU_H
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#define __ASMARM_ARCH_SCU_H
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#include <asm/arch/platform.h>
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#define SCU_BASE REALVIEW_MPCORE_SCU_BASE
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#endif
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@ -1,6 +1,8 @@
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#ifndef ASMARM_HARDWARE_ARM_SCU_H
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#define ASMARM_HARDWARE_ARM_SCU_H
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#include <asm/arch/scu.h>
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/*
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* SCU registers
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*/
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