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MIPS: Make various locks static.

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2010-02-27 12:53:30 +01:00
parent 559e25a5e3
commit 4a8a738de6
9 changed files with 9 additions and 9 deletions
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3
arch/mips/cavium-octeon/octeon-irq.c
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@ -15,7 +15,6 @@
DEFINE_RWLOCK(octeon_irq_ciu0_rwlock); DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
DEFINE_SPINLOCK(octeon_irq_msi_lock);
static int octeon_coreid_for_cpu(int cpu) static int octeon_coreid_for_cpu(int cpu)
{ {
@ -545,6 +544,8 @@ static struct irq_chip octeon_irq_chip_ciu1 = {
#ifdef CONFIG_PCI_MSI #ifdef CONFIG_PCI_MSI
static DEFINE_SPINLOCK(octeon_irq_msi_lock);
static void octeon_irq_msi_ack(unsigned int irq) static void octeon_irq_msi_ack(unsigned int irq)
{ {
if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {

2
arch/mips/dec/kn01-berr.c
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@ -46,7 +46,7 @@
* There is no default value -- it has to be initialized. * There is no default value -- it has to be initialized.
*/ */
u16 cached_kn01_csr; u16 cached_kn01_csr;
DEFINE_SPINLOCK(kn01_lock); static DEFINE_SPINLOCK(kn01_lock);
static inline void dec_kn01_be_ack(void) static inline void dec_kn01_be_ack(void)

1
arch/mips/include/asm/dec/kn01.h
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@ -80,7 +80,6 @@
struct pt_regs; struct pt_regs;
extern u16 cached_kn01_csr; extern u16 cached_kn01_csr;
extern spinlock_t kn01_lock;
extern void dec_kn01_be_init(void); extern void dec_kn01_be_init(void);
extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup); extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);

2
arch/mips/oprofile/op_model_loongson2.c
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@ -47,7 +47,7 @@ static struct loongson2_register_config {
int cnt1_enabled, cnt2_enabled; int cnt1_enabled, cnt2_enabled;
} reg; } reg;
DEFINE_SPINLOCK(sample_lock); static DEFINE_SPINLOCK(sample_lock);
static char *oprofid = "LoongsonPerf"; static char *oprofid = "LoongsonPerf";
static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id); static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);

2
arch/mips/pci/ops-pmcmsp.c
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@ -206,7 +206,7 @@ static void pci_proc_init(void)
} }
#endif /* CONFIG_PROC_FS && PCI_COUNTERS */ #endif /* CONFIG_PROC_FS && PCI_COUNTERS */
DEFINE_SPINLOCK(bpci_lock); static DEFINE_SPINLOCK(bpci_lock);
/***************************************************************************** /*****************************************************************************
* *

2
arch/mips/sgi-ip27/ip27-nmi.c
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@ -21,7 +21,7 @@
typedef unsigned long machreg_t; typedef unsigned long machreg_t;
DEFINE_SPINLOCK(nmi_lock); static DEFINE_SPINLOCK(nmi_lock);
/* /*
* Lets see what else we need to do here. Set up sp, gp? * Lets see what else we need to do here. Set up sp, gp?

2
arch/mips/sibyte/bcm1480/irq.c
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@ -73,7 +73,7 @@ static struct irq_chip bcm1480_irq_type = {
/* Store the CPU id (not the logical number) */ /* Store the CPU id (not the logical number) */
int bcm1480_irq_owner[BCM1480_NR_IRQS]; int bcm1480_irq_owner[BCM1480_NR_IRQS];
DEFINE_SPINLOCK(bcm1480_imr_lock); static DEFINE_SPINLOCK(bcm1480_imr_lock);
void bcm1480_mask_irq(int cpu, int irq) void bcm1480_mask_irq(int cpu, int irq)
{ {

2
arch/mips/sibyte/sb1250/irq.c
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@ -72,7 +72,7 @@ static struct irq_chip sb1250_irq_type = {
/* Store the CPU id (not the logical number) */ /* Store the CPU id (not the logical number) */
int sb1250_irq_owner[SB1250_NR_IRQS]; int sb1250_irq_owner[SB1250_NR_IRQS];
DEFINE_SPINLOCK(sb1250_imr_lock); static DEFINE_SPINLOCK(sb1250_imr_lock);
void sb1250_mask_irq(int cpu, int irq) void sb1250_mask_irq(int cpu, int irq)
{ {

2
arch/mips/sni/rm200.c
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@ -132,7 +132,7 @@ device_initcall(snirm_setup_devinit);
* readb/writeb to access them * readb/writeb to access them
*/ */
DEFINE_SPINLOCK(sni_rm200_i8259A_lock); static DEFINE_SPINLOCK(sni_rm200_i8259A_lock);
#define PIC_CMD 0x00 #define PIC_CMD 0x00
#define PIC_IMR 0x01 #define PIC_IMR 0x01
#define PIC_ISR PIC_CMD #define PIC_ISR PIC_CMD