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drm/amdgpu: add reset_ras_error_count function for HDP

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HDP ras error counters are dirty ones after cold reboot
Read operation is needed to reset them to 0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang
2020-03-02 16:16:58 +08:00
committed by Alex Deucher
parent 279375c331
commit 4a89ad9b39
3 changed files with 15 additions and 1 deletions
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1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
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@@ -579,6 +579,7 @@ struct amdgpu_asic_funcs {
/* invalidate hdp read cache */ /* invalidate hdp read cache */
void (*invalidate_hdp)(struct amdgpu_device *adev, void (*invalidate_hdp)(struct amdgpu_device *adev,
struct amdgpu_ring *ring); struct amdgpu_ring *ring);
void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev);
/* check if the asic needs a full reset of if soft reset will work */ /* check if the asic needs a full reset of if soft reset will work */
bool (*need_full_reset)(struct amdgpu_device *adev); bool (*need_full_reset)(struct amdgpu_device *adev);
/* initialize doorbell layout for specific asic*/ /* initialize doorbell layout for specific asic*/

1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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@@ -4196,7 +4196,6 @@ static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = {
{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
{ SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
}; };
static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)

14
drivers/gpu/drm/amd/amdgpu/soc15.c
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@@ -831,6 +831,15 @@ static bool soc15_need_full_reset(struct amdgpu_device *adev)
/* change this when we implement soft reset */ /* change this when we implement soft reset */
return true; return true;
} }
static void vega20_reset_hdp_ras_error_count(struct amdgpu_device *adev)
{
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
return;
/*read back hdp ras counter to reset it to 0 */
RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
}
static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
uint64_t *count1) uint64_t *count1)
{ {
@@ -998,6 +1007,7 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
.get_config_memsize = &soc15_get_config_memsize, .get_config_memsize = &soc15_get_config_memsize,
.flush_hdp = &soc15_flush_hdp, .flush_hdp = &soc15_flush_hdp,
.invalidate_hdp = &soc15_invalidate_hdp, .invalidate_hdp = &soc15_invalidate_hdp,
.reset_hdp_ras_error_count = &vega20_reset_hdp_ras_error_count,
.need_full_reset = &soc15_need_full_reset, .need_full_reset = &soc15_need_full_reset,
.init_doorbell_index = &vega20_doorbell_index_init, .init_doorbell_index = &vega20_doorbell_index_init,
.get_pcie_usage = &vega20_get_pcie_usage, .get_pcie_usage = &vega20_get_pcie_usage,
@@ -1243,6 +1253,10 @@ static int soc15_common_late_init(void *handle)
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
xgpu_ai_mailbox_get_irq(adev); xgpu_ai_mailbox_get_irq(adev);
if (adev->asic_funcs &&
adev->asic_funcs->reset_hdp_ras_error_count)
adev->asic_funcs->reset_hdp_ras_error_count(adev);
if (adev->nbio.funcs->ras_late_init) if (adev->nbio.funcs->ras_late_init)
r = adev->nbio.funcs->ras_late_init(adev); r = adev->nbio.funcs->ras_late_init(adev);