habanalabs: Allow accessing host mapped addresses via debugfs
Allows using the addr/data32 debugfs nodes to access a device VA of a host mapped memory when the IOMMU is disabled. Due to the possible large amount of a user host mapped memory, the driver doesn't maintain a database with the host addresses per device VA. When the IOMMU is disabled, this missing info is being overcome by simply using phys_to_virt(). However, this is not useful when the IOMMU is enabled, and thus the enforced limitation. Signed-off-by: Tomer Tayar <ttayar@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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@ -3,7 +3,10 @@ Date: Jan 2019
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KernelVersion: 5.1
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KernelVersion: 5.1
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Contact: oded.gabbay@gmail.com
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Contact: oded.gabbay@gmail.com
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Description: Sets the device address to be used for read or write through
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Description: Sets the device address to be used for read or write through
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PCI bar. The acceptable value is a string that starts with "0x"
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PCI bar, or the device VA of a host mapped memory to be read or
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written directly from the host. The latter option is allowed
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only when the IOMMU is disabled.
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The acceptable value is a string that starts with "0x"
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What: /sys/kernel/debug/habanalabs/hl<n>/command_buffers
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What: /sys/kernel/debug/habanalabs/hl<n>/command_buffers
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Date: Jan 2019
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Date: Jan 2019
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@ -33,10 +36,12 @@ Contact: oded.gabbay@gmail.com
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Description: Allows the root user to read or write directly through the
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Description: Allows the root user to read or write directly through the
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device's PCI bar. Writing to this file generates a write
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device's PCI bar. Writing to this file generates a write
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transaction while reading from the file generates a read
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transaction while reading from the file generates a read
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transcation. This custom interface is needed (instead of using
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transaction. This custom interface is needed (instead of using
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the generic Linux user-space PCI mapping) because the DDR bar
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the generic Linux user-space PCI mapping) because the DDR bar
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is very small compared to the DDR memory and only the driver can
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is very small compared to the DDR memory and only the driver can
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move the bar before and after the transaction
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move the bar before and after the transaction.
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If the IOMMU is disabled, it also allows the root user to read
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or write from the host a device VA of a host mapped memory
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What: /sys/kernel/debug/habanalabs/hl<n>/device
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What: /sys/kernel/debug/habanalabs/hl<n>/device
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Date: Jan 2019
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Date: Jan 2019
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@ -500,6 +500,25 @@ err:
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return -EINVAL;
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return -EINVAL;
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}
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}
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static bool hl_is_device_va(struct hl_device *hdev, u64 addr)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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if (!hdev->mmu_enable)
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goto out;
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if (hdev->dram_supports_virtual_memory &&
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addr >= prop->va_space_dram_start_address &&
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addr < prop->va_space_dram_end_address)
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return true;
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if (addr >= prop->va_space_host_start_address &&
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addr < prop->va_space_host_end_address)
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return true;
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out:
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return false;
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}
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static int device_va_to_pa(struct hl_device *hdev, u64 virt_addr,
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static int device_va_to_pa(struct hl_device *hdev, u64 virt_addr,
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u64 *phys_addr)
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u64 *phys_addr)
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{
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{
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@ -573,7 +592,6 @@ static ssize_t hl_data_read32(struct file *f, char __user *buf,
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{
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{
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struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
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struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
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struct hl_device *hdev = entry->hdev;
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struct hl_device *hdev = entry->hdev;
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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char tmp_buf[32];
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char tmp_buf[32];
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u64 addr = entry->addr;
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u64 addr = entry->addr;
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u32 val;
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u32 val;
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@ -582,11 +600,8 @@ static ssize_t hl_data_read32(struct file *f, char __user *buf,
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if (*ppos)
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if (*ppos)
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return 0;
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return 0;
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if (addr >= prop->va_space_dram_start_address &&
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if (hl_is_device_va(hdev, addr)) {
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addr < prop->va_space_dram_end_address &&
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rc = device_va_to_pa(hdev, addr, &addr);
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hdev->mmu_enable &&
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hdev->dram_supports_virtual_memory) {
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rc = device_va_to_pa(hdev, entry->addr, &addr);
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if (rc)
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if (rc)
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return rc;
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return rc;
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}
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}
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@ -607,7 +622,6 @@ static ssize_t hl_data_write32(struct file *f, const char __user *buf,
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{
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{
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struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
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struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
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struct hl_device *hdev = entry->hdev;
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struct hl_device *hdev = entry->hdev;
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 addr = entry->addr;
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u64 addr = entry->addr;
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u32 value;
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u32 value;
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ssize_t rc;
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ssize_t rc;
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@ -616,11 +630,8 @@ static ssize_t hl_data_write32(struct file *f, const char __user *buf,
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if (rc)
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if (rc)
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return rc;
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return rc;
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if (addr >= prop->va_space_dram_start_address &&
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if (hl_is_device_va(hdev, addr)) {
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addr < prop->va_space_dram_end_address &&
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rc = device_va_to_pa(hdev, addr, &addr);
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hdev->mmu_enable &&
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hdev->dram_supports_virtual_memory) {
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rc = device_va_to_pa(hdev, entry->addr, &addr);
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if (rc)
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if (rc)
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return rc;
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return rc;
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}
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}
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@ -14,6 +14,7 @@
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#include <linux/genalloc.h>
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#include <linux/genalloc.h>
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#include <linux/hwmon.h>
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#include <linux/hwmon.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/iommu.h>
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/*
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/*
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* GOYA security scheme:
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* GOYA security scheme:
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@ -3941,10 +3942,11 @@ static void goya_clear_sm_regs(struct hl_device *hdev)
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}
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}
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/*
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/*
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* goya_debugfs_read32 - read a 32bit value from a given device address
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* goya_debugfs_read32 - read a 32bit value from a given device or a host mapped
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* address.
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*
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*
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* @hdev: pointer to hl_device structure
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* @hdev: pointer to hl_device structure
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* @addr: address in device
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* @addr: device or host mapped address
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* @val: returned value
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* @val: returned value
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*
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*
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* In case of DDR address that is not mapped into the default aperture that
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* In case of DDR address that is not mapped into the default aperture that
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@ -3985,6 +3987,10 @@ static int goya_debugfs_read32(struct hl_device *hdev, u64 addr, u32 *val)
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}
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}
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if (ddr_bar_addr == U64_MAX)
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if (ddr_bar_addr == U64_MAX)
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rc = -EIO;
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rc = -EIO;
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} else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
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*val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);
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} else {
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} else {
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rc = -EFAULT;
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rc = -EFAULT;
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}
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}
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@ -3993,10 +3999,11 @@ static int goya_debugfs_read32(struct hl_device *hdev, u64 addr, u32 *val)
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}
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}
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/*
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/*
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* goya_debugfs_write32 - write a 32bit value to a given device address
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* goya_debugfs_write32 - write a 32bit value to a given device or a host mapped
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* address.
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*
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*
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* @hdev: pointer to hl_device structure
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* @hdev: pointer to hl_device structure
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* @addr: address in device
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* @addr: device or host mapped address
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* @val: returned value
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* @val: returned value
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*
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*
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* In case of DDR address that is not mapped into the default aperture that
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* In case of DDR address that is not mapped into the default aperture that
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@ -4037,6 +4044,10 @@ static int goya_debugfs_write32(struct hl_device *hdev, u64 addr, u32 val)
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}
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}
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if (ddr_bar_addr == U64_MAX)
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if (ddr_bar_addr == U64_MAX)
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rc = -EIO;
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rc = -EIO;
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} else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
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*(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
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} else {
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} else {
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rc = -EFAULT;
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rc = -EFAULT;
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}
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}
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