xtensa: Use generic show_interrupts()
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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610e1756ea
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@ -8,6 +8,7 @@ config XTENSA
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def_bool y
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def_bool y
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select HAVE_IDE
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select HAVE_IDE
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select HAVE_GENERIC_HARDIRQS
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_IRQ_SHOW
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_HARDIRQS_NO_DEPRECATED
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help
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help
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Xtensa processors are 32-bit RISC machines designed by Tensilica
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Xtensa processors are 32-bit RISC machines designed by Tensilica
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@ -62,51 +62,16 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
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set_irq_regs(old_regs);
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set_irq_regs(old_regs);
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}
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}
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/*
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int arch_show_interrupts(struct seq_file *p, int prec)
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* Generic, controller-independent functions:
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*/
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int show_interrupts(struct seq_file *p, void *v)
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{
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{
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int i = *(loff_t *) v, j;
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int j;
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struct irqaction * action;
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unsigned long flags;
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if (i == 0) {
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seq_printf(p, "%*s: ", prec, "NMI");
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seq_printf(p, " ");
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for_each_online_cpu(j)
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", nmi_count(j));
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seq_printf(p, "CPU%d ",j);
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seq_putc(p, '\n');
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seq_putc(p, '\n');
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seq_printf(p, "%*s: ", prec, "ERR");
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}
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seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
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if (i < NR_IRQS) {
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raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
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action = irq_desc[i].action;
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if (!action)
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goto skip;
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seq_printf(p, "%3d: ",i);
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#ifndef CONFIG_SMP
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seq_printf(p, "%10u ", kstat_irqs(i));
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#else
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
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#endif
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seq_printf(p, " %14s", irq_desc[i].chip->name);
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seq_printf(p, " %s", action->name);
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for (action=action->next; action; action = action->next)
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seq_printf(p, ", %s", action->name);
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seq_putc(p, '\n');
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skip:
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raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
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} else if (i == NR_IRQS) {
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seq_printf(p, "NMI: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", nmi_count(j));
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seq_putc(p, '\n');
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seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
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}
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return 0;
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return 0;
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}
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}
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