usb: ehci-omap: Add OMAP4 support
Update the ehci-omap glue layer to support the controller in the OMAP4. Major differences from OMAP3 is that the OMAP4 has per-port clocking, and supports ULPI output clocking mode. The old input clocking mode is not supported. Also, there are only 2 externally available ports as against 3 in the OMAP3. The third port is internally tied off and should not be used. Signed-off-by: Keshava Munegowda <keshava_mgowda@ti.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
This commit is contained in:
Anand Gadiyar
parent
1ed85659a2
commit
4792a15bf0
@ -1,11 +1,12 @@
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/*
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* ehci-omap.c - driver for USBHOST on OMAP 34xx processor
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* ehci-omap.c - driver for USBHOST on OMAP3/4 processors
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*
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* Bus Glue for OMAP34xx USBHOST 3 port EHCI controller
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* Tested on OMAP3430 ES2.0 SDP
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* Bus Glue for the EHCI controllers in OMAP3/4
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* Tested on several OMAP3 boards, and OMAP4 Pandaboard
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Texas Instruments, Inc.
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* Author: Vikram Pandita <vikram.pandita@ti.com>
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* Author: Anand Gadiyar <gadiyar@ti.com>
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*
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* Copyright (C) 2009 Nokia Corporation
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* Contact: Felipe Balbi <felipe.balbi@nokia.com>
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@ -26,11 +27,14 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* TODO (last updated Feb 12, 2010):
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* TODO (last updated Nov 21, 2010):
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* - add kernel-doc
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* - enable AUTOIDLE
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* - add suspend/resume
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* - move workarounds to board-files
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* - factor out code common to OHCI
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* - add HSIC and TLL support
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* - convert to use hwmod and runtime PM
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*/
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#include <linux/platform_device.h>
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@ -114,6 +118,23 @@
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#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
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#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
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/* OMAP4-specific defines */
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#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
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#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
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#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
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#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
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#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
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#define OMAP4_P1_MODE_CLEAR (3 << 16)
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#define OMAP4_P1_MODE_TLL (1 << 16)
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#define OMAP4_P1_MODE_HSIC (3 << 16)
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#define OMAP4_P2_MODE_CLEAR (3 << 18)
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#define OMAP4_P2_MODE_TLL (1 << 18)
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#define OMAP4_P2_MODE_HSIC (3 << 18)
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#define OMAP_REV2_TLL_CHANNEL_COUNT 2
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#define OMAP_UHH_DEBUG_CSR (0x44)
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/* EHCI Register Set */
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@ -127,8 +148,16 @@
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#define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8
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#define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0
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/* Values of UHH_REVISION - Note: these are not given in the TRM */
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#define OMAP_EHCI_REV1 0x00000010 /* OMAP3 */
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#define OMAP_EHCI_REV2 0x50700100 /* OMAP4 */
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#define is_omap_ehci_rev1(x) (x->omap_ehci_rev == OMAP_EHCI_REV1)
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#define is_omap_ehci_rev2(x) (x->omap_ehci_rev == OMAP_EHCI_REV2)
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#define is_ehci_phy_mode(x) (x == EHCI_HCD_OMAP_MODE_PHY)
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#define is_ehci_tll_mode(x) (x == EHCI_HCD_OMAP_MODE_TLL)
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#define is_ehci_hsic_mode(x) (x == EHCI_HCD_OMAP_MODE_HSIC)
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/*-------------------------------------------------------------------------*/
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@ -163,6 +192,10 @@ struct ehci_hcd_omap {
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struct clk *usbhost_fs_fck;
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struct clk *usbtll_fck;
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struct clk *usbtll_ick;
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struct clk *xclk60mhsp1_ck;
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struct clk *xclk60mhsp2_ck;
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struct clk *utmi_p1_fck;
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struct clk *utmi_p2_fck;
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/* FIXME the following two workarounds are
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* board specific not silicon-specific so these
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@ -179,6 +212,9 @@ struct ehci_hcd_omap {
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/* phy reset workaround */
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int phy_reset;
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/* IP revision */
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u32 omap_ehci_rev;
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/* desired phy_mode: TLL, PHY */
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enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
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@ -337,6 +373,80 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
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}
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clk_enable(omap->usbtll_ick);
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omap->omap_ehci_rev = ehci_omap_readl(omap->uhh_base,
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OMAP_UHH_REVISION);
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dev_dbg(omap->dev, "OMAP UHH_REVISION 0x%x\n",
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omap->omap_ehci_rev);
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/*
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* Enable per-port clocks as needed (newer controllers only).
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* - External ULPI clock for PHY mode
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* - Internal clocks for TLL and HSIC modes (TODO)
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*/
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if (is_omap_ehci_rev2(omap)) {
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switch (omap->port_mode[0]) {
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case EHCI_HCD_OMAP_MODE_PHY:
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omap->xclk60mhsp1_ck = clk_get(omap->dev,
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"xclk60mhsp1_ck");
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if (IS_ERR(omap->xclk60mhsp1_ck)) {
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ret = PTR_ERR(omap->xclk60mhsp1_ck);
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dev_err(omap->dev,
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"Unable to get Port1 ULPI clock\n");
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}
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omap->utmi_p1_fck = clk_get(omap->dev,
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"utmi_p1_gfclk");
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if (IS_ERR(omap->utmi_p1_fck)) {
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ret = PTR_ERR(omap->utmi_p1_fck);
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dev_err(omap->dev,
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"Unable to get utmi_p1_fck\n");
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}
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ret = clk_set_parent(omap->utmi_p1_fck,
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omap->xclk60mhsp1_ck);
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if (ret != 0) {
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dev_err(omap->dev,
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"Unable to set P1 f-clock\n");
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}
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break;
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case EHCI_HCD_OMAP_MODE_TLL:
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/* TODO */
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default:
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break;
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}
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switch (omap->port_mode[1]) {
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case EHCI_HCD_OMAP_MODE_PHY:
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omap->xclk60mhsp2_ck = clk_get(omap->dev,
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"xclk60mhsp2_ck");
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if (IS_ERR(omap->xclk60mhsp2_ck)) {
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ret = PTR_ERR(omap->xclk60mhsp2_ck);
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dev_err(omap->dev,
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"Unable to get Port2 ULPI clock\n");
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}
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omap->utmi_p2_fck = clk_get(omap->dev,
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"utmi_p2_gfclk");
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if (IS_ERR(omap->utmi_p2_fck)) {
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ret = PTR_ERR(omap->utmi_p2_fck);
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dev_err(omap->dev,
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"Unable to get utmi_p2_fck\n");
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}
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ret = clk_set_parent(omap->utmi_p2_fck,
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omap->xclk60mhsp2_ck);
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if (ret != 0) {
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dev_err(omap->dev,
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"Unable to set P2 f-clock\n");
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}
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break;
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case EHCI_HCD_OMAP_MODE_TLL:
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/* TODO */
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default:
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break;
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}
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}
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/* perform TLL soft reset, and wait until reset is complete */
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ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
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OMAP_USBTLL_SYSCONFIG_SOFTRESET);
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@ -364,12 +474,20 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
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/* Put UHH in NoIdle/NoStandby mode */
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reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
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reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
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| OMAP_UHH_SYSCONFIG_SIDLEMODE
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| OMAP_UHH_SYSCONFIG_CACTIVITY
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| OMAP_UHH_SYSCONFIG_MIDLEMODE);
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reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
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if (is_omap_ehci_rev1(omap)) {
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reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
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| OMAP_UHH_SYSCONFIG_SIDLEMODE
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| OMAP_UHH_SYSCONFIG_CACTIVITY
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| OMAP_UHH_SYSCONFIG_MIDLEMODE);
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reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
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} else if (is_omap_ehci_rev2(omap)) {
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reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR;
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reg |= OMAP4_UHH_SYSCONFIG_NOIDLE;
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reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR;
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reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY;
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}
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ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
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reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
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@ -380,40 +498,56 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
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| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
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reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
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if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
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reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
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if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
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reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
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if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
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reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
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if (is_omap_ehci_rev1(omap)) {
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if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
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reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
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if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
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reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
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if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
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reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
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/* Bypass the TLL module for PHY mode operation */
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if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
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dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1\n");
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if (is_ehci_phy_mode(omap->port_mode[0]) ||
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is_ehci_phy_mode(omap->port_mode[1]) ||
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is_ehci_phy_mode(omap->port_mode[2]))
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reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
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else
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reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
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} else {
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dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
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if (is_ehci_phy_mode(omap->port_mode[0]))
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reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
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else if (is_ehci_tll_mode(omap->port_mode[0]))
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reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
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/* Bypass the TLL module for PHY mode operation */
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if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
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dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1\n");
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if (is_ehci_phy_mode(omap->port_mode[0]) ||
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is_ehci_phy_mode(omap->port_mode[1]) ||
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is_ehci_phy_mode(omap->port_mode[2]))
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reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
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else
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reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
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} else {
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dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
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if (is_ehci_phy_mode(omap->port_mode[0]))
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reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
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else if (is_ehci_tll_mode(omap->port_mode[0]))
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reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
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if (is_ehci_phy_mode(omap->port_mode[1]))
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reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
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else if (is_ehci_tll_mode(omap->port_mode[1]))
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reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
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if (is_ehci_phy_mode(omap->port_mode[1]))
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reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
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else if (is_ehci_tll_mode(omap->port_mode[1]))
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reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
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if (is_ehci_phy_mode(omap->port_mode[2]))
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reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
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else if (is_ehci_tll_mode(omap->port_mode[2]))
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reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
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if (is_ehci_phy_mode(omap->port_mode[2]))
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reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
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else if (is_ehci_tll_mode(omap->port_mode[2]))
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reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
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}
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} else if (is_omap_ehci_rev2(omap)) {
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/* Clear port mode fields for PHY mode*/
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reg &= ~OMAP4_P1_MODE_CLEAR;
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reg &= ~OMAP4_P2_MODE_CLEAR;
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if (is_ehci_tll_mode(omap->port_mode[0]))
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reg |= OMAP4_P1_MODE_TLL;
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else if (is_ehci_hsic_mode(omap->port_mode[0]))
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reg |= OMAP4_P1_MODE_HSIC;
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if (is_ehci_tll_mode(omap->port_mode[1]))
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reg |= OMAP4_P2_MODE_TLL;
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else if (is_ehci_hsic_mode(omap->port_mode[1]))
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reg |= OMAP4_P2_MODE_HSIC;
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}
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ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
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dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
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@ -468,6 +602,14 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
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return 0;
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err_sys_status:
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clk_disable(omap->utmi_p2_fck);
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clk_put(omap->utmi_p2_fck);
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clk_disable(omap->xclk60mhsp2_ck);
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clk_put(omap->xclk60mhsp2_ck);
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clk_disable(omap->utmi_p1_fck);
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clk_put(omap->utmi_p1_fck);
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clk_disable(omap->xclk60mhsp1_ck);
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clk_put(omap->xclk60mhsp1_ck);
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clk_disable(omap->usbtll_ick);
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clk_put(omap->usbtll_ick);
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@ -507,6 +649,8 @@ static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
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/* Reset OMAP modules for insmod/rmmod to work */
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ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG,
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is_omap_ehci_rev2(omap) ?
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OMAP4_UHH_SYSCONFIG_SOFTRESET :
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OMAP_UHH_SYSCONFIG_SOFTRESET);
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while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
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& (1 << 0))) {
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@ -572,6 +716,32 @@ static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
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omap->usbtll_ick = NULL;
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}
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if (is_omap_ehci_rev2(omap)) {
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if (omap->xclk60mhsp1_ck != NULL) {
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clk_disable(omap->xclk60mhsp1_ck);
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clk_put(omap->xclk60mhsp1_ck);
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omap->xclk60mhsp1_ck = NULL;
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}
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if (omap->utmi_p1_fck != NULL) {
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clk_disable(omap->utmi_p1_fck);
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clk_put(omap->utmi_p1_fck);
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omap->utmi_p1_fck = NULL;
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}
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if (omap->xclk60mhsp2_ck != NULL) {
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clk_disable(omap->xclk60mhsp2_ck);
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clk_put(omap->xclk60mhsp2_ck);
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omap->xclk60mhsp2_ck = NULL;
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}
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if (omap->utmi_p2_fck != NULL) {
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clk_disable(omap->utmi_p2_fck);
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clk_put(omap->utmi_p2_fck);
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omap->utmi_p2_fck = NULL;
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}
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}
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if (omap->phy_reset) {
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if (gpio_is_valid(omap->reset_gpio_port[0]))
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gpio_free(omap->reset_gpio_port[0]);
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