forked from Minki/linux
GPIO bug fixes on top of v3.4-rc2
Miscellaneous bug fixes to GPIO drivers and for a corner case in the gpio device tree parsing code. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPiG4HAAoJEEFnBt12D9kBekwQALuM73zU18cvoLgd+wg34RFy 4xJ23sm3QtSixXFBcQuLPwcPT5hMUMjQBP+LQ3mf8oshrr3zV5EdjuvVXA8xP78H nBWqBoJ+HNEV01b1a1rqvXGgzHofCVYHS7dAZ6Ob0RPfTfIzzM7x9et9pWsq1Q/5 ribPBqaonhs0hnJkEoXB8SVl4R6brhubwzk38C9gzAG2/faVr6Wv5o43C1PlLiLg WT+0bvSJmQwiV2U9fkq9HUkjoZLw2VS8BUYL8OjzeVZ0mdGJrP1KQiQuhuYOg6Rx iBPJK7SyCRsIvGsqb9IkdLpZ3hdvM1g5OEmXIHXowNlwjiyX8hZgs0XF4cIZ+VCn GOIrYG8GE3uy5WRnkROzCPyMvFYYidTp4ZcZoh1bRJWzt/6m7craAgSkcwk4/xTw edbLTqW1szmI/pkwb3EjbUkA+ee6lMSlwKoKmvVz/LL+/UOdRWvm48vu1rdkQ1+1 +Ylgm9KpG1ywFyPsWG7owLWH2j4Us/4lBdWWVwtJaCORc2KGdxD7BVxhAcrZTIIt RB8ODBvpYgs/jH/+tvfnvdNuXHQiPyd/UQwbGXs0RM/rHBTtDaUfxt8zXQpXkgRa JBl+pvpnmJHsNBJ7i4by/ii62kF3rXjTMA8ZGo8zNGOBcto5jMBkIGn+zlx17c8V xx880JZh7+8sZu3kTqRs =fdGO -----END PGP SIGNATURE----- Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6 Pull GPIO bug fixes from Grant Likely: "Miscellaneous bug fixes to GPIO drivers and for a corner case in the gpio device tree parsing code." * tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6: gpio/exynos: Fix compiler warning in gpio-samsung.c file gpio: Fix range check in of_gpio_simple_xlate() gpio: Fix uninitialized variable bit in adp5588_irq_handler gpio/sodaville: Convert sodaville driver to new irqdomain API
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commit
461c14917e
@ -430,7 +430,7 @@ config GPIO_ML_IOH
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config GPIO_SODAVILLE
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bool "Intel Sodaville GPIO support"
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depends on X86 && PCI && OF && BROKEN
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depends on X86 && PCI && OF
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select GPIO_GENERIC
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select GENERIC_IRQ_CHIP
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help
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@ -252,7 +252,7 @@ static irqreturn_t adp5588_irq_handler(int irq, void *devid)
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if (ret < 0)
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memset(dev->irq_stat, 0, ARRAY_SIZE(dev->irq_stat));
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for (bank = 0; bank <= ADP5588_BANK(ADP5588_MAXGPIO);
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for (bank = 0, bit = 0; bank <= ADP5588_BANK(ADP5588_MAXGPIO);
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bank++, bit = 0) {
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pending = dev->irq_stat[bank] & dev->irq_mask[bank];
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@ -2382,8 +2382,8 @@ static struct samsung_gpio_chip exynos4_gpios_3[] = {
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#endif
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};
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static struct samsung_gpio_chip exynos5_gpios_1[] = {
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#ifdef CONFIG_ARCH_EXYNOS5
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static struct samsung_gpio_chip exynos5_gpios_1[] = {
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{
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.chip = {
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.base = EXYNOS5_GPA0(0),
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@ -2541,11 +2541,11 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
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.to_irq = samsung_gpiolib_to_irq,
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},
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},
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#endif
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};
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#endif
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static struct samsung_gpio_chip exynos5_gpios_2[] = {
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#ifdef CONFIG_ARCH_EXYNOS5
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static struct samsung_gpio_chip exynos5_gpios_2[] = {
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{
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.chip = {
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.base = EXYNOS5_GPE0(0),
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@ -2602,11 +2602,11 @@ static struct samsung_gpio_chip exynos5_gpios_2[] = {
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},
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},
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#endif
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};
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#endif
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static struct samsung_gpio_chip exynos5_gpios_3[] = {
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#ifdef CONFIG_ARCH_EXYNOS5
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static struct samsung_gpio_chip exynos5_gpios_3[] = {
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{
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.chip = {
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.base = EXYNOS5_GPV0(0),
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@ -2638,11 +2638,11 @@ static struct samsung_gpio_chip exynos5_gpios_3[] = {
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.label = "GPV4",
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},
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},
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#endif
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};
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#endif
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static struct samsung_gpio_chip exynos5_gpios_4[] = {
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#ifdef CONFIG_ARCH_EXYNOS5
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static struct samsung_gpio_chip exynos5_gpios_4[] = {
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{
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.chip = {
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.base = EXYNOS5_GPZ(0),
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@ -2650,8 +2650,8 @@ static struct samsung_gpio_chip exynos5_gpios_4[] = {
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.label = "GPZ",
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},
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},
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#endif
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};
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#endif
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#if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
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@ -41,7 +41,7 @@
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struct sdv_gpio_chip_data {
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int irq_base;
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void __iomem *gpio_pub_base;
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struct irq_domain id;
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struct irq_domain *id;
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struct irq_chip_generic *gc;
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struct bgpio_chip bgpio;
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};
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@ -51,10 +51,9 @@ static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct sdv_gpio_chip_data *sd = gc->private;
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void __iomem *type_reg;
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u32 irq_offs = d->irq - sd->irq_base;
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u32 reg;
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if (irq_offs < 8)
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if (d->hwirq < 8)
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type_reg = sd->gpio_pub_base + GPIT1R0;
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else
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type_reg = sd->gpio_pub_base + GPIT1R1;
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@ -63,11 +62,11 @@ static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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reg &= ~BIT(4 * (irq_offs % 8));
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reg &= ~BIT(4 * (d->hwirq % 8));
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break;
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case IRQ_TYPE_LEVEL_LOW:
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reg |= BIT(4 * (irq_offs % 8));
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reg |= BIT(4 * (d->hwirq % 8));
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break;
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default:
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@ -91,7 +90,7 @@ static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
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u32 irq_bit = __fls(irq_stat);
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irq_stat &= ~BIT(irq_bit);
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generic_handle_irq(sd->irq_base + irq_bit);
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generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
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}
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return IRQ_HANDLED;
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@ -127,7 +126,7 @@ static int sdv_xlate(struct irq_domain *h, struct device_node *node,
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}
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static struct irq_domain_ops irq_domain_sdv_ops = {
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.dt_translate = sdv_xlate,
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.xlate = sdv_xlate,
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};
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static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
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@ -149,10 +148,6 @@ static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
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if (ret)
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goto out_free_desc;
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sd->id.irq_base = sd->irq_base;
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sd->id.of_node = of_node_get(pdev->dev.of_node);
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sd->id.ops = &irq_domain_sdv_ops;
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/*
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* This gpio irq controller latches level irqs. Testing shows that if
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* we unmask & ACK the IRQ before the source of the interrupt is gone
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@ -179,7 +174,10 @@ static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
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IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
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IRQ_LEVEL | IRQ_NOPROBE);
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irq_domain_add(&sd->id);
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sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
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sd->irq_base, 0, &irq_domain_sdv_ops, sd);
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if (!sd->id)
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goto out_free_irq;
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return 0;
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out_free_irq:
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free_irq(pdev->irq, sd);
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@ -260,7 +258,6 @@ static void sdv_gpio_remove(struct pci_dev *pdev)
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{
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struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev);
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irq_domain_del(&sd->id);
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free_irq(pdev->irq, sd);
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irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
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@ -140,7 +140,7 @@ int of_gpio_simple_xlate(struct gpio_chip *gc,
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if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
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return -EINVAL;
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if (gpiospec->args[0] > gc->ngpio)
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if (gpiospec->args[0] >= gc->ngpio)
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return -EINVAL;
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if (flags)
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