ARM: dts: uniphier: Add USB3 controller nodes
Add USB3 controller nodes including usb-core, resets, regulator, ss-phy and hs-phy. This supports for Pro4, PXs2 and the boards. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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84a9c4d559
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@ -80,6 +80,14 @@
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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&nand {
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status = "okay";
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};
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@ -90,3 +90,11 @@
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reg = <1>;
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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@ -88,6 +88,14 @@
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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&nand {
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status = "okay";
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};
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@ -85,3 +85,11 @@
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reg = <1>;
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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@ -445,6 +445,100 @@
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};
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};
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usb0: usb@65a00000 {
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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65a00000 0xcd00>;
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interrupt-names = "host", "peripheral";
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interrupts = <0 134 4>, <0 135 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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clock-names = "ref", "bus_early", "suspend";
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clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
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resets = <&usb0_rst 4>;
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phys = <&usb0_ssphy>;
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dr_mode = "host";
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};
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-pro4-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x100>;
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usb0_vbus: regulator@0 {
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compatible = "socionext,uniphier-pro4-usb3-regulator";
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reg = <0 0x10>;
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clock-names = "gio", "link";
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clocks = <&sys_clk 12>, <&sys_clk 14>;
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reset-names = "gio", "link";
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resets = <&sys_rst 12>, <&sys_rst 14>;
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};
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usb0_ssphy: ss-phy@10 {
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compatible = "socionext,uniphier-pro4-usb3-ssphy";
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reg = <0x10 0x10>;
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#phy-cells = <0>;
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clock-names = "gio", "link";
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clocks = <&sys_clk 12>, <&sys_clk 14>;
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reset-names = "gio", "link";
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resets = <&sys_rst 12>, <&sys_rst 14>;
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vbus-supply = <&usb0_vbus>;
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};
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usb0_rst: reset@40 {
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compatible = "socionext,uniphier-pro4-usb3-reset";
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reg = <0x40 0x4>;
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#reset-cells = <1>;
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clock-names = "gio", "link";
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clocks = <&sys_clk 12>, <&sys_clk 14>;
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reset-names = "gio", "link";
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resets = <&sys_rst 12>, <&sys_rst 14>;
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};
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};
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usb1: usb@65c00000 {
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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65c00000 0xcd00>;
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interrupt-names = "host", "peripheral";
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interrupts = <0 137 4>, <0 138 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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clock-names = "ref", "bus_early", "suspend";
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clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
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resets = <&usb1_rst 4>;
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dr_mode = "host";
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};
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usb-glue@65d00000 {
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compatible = "socionext,uniphier-pro4-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65d00000 0x100>;
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usb1_vbus: regulator@0 {
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compatible = "socionext,uniphier-pro4-usb3-regulator";
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reg = <0 0x10>;
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clock-names = "gio", "link";
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clocks = <&sys_clk 12>, <&sys_clk 15>;
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reset-names = "gio", "link";
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resets = <&sys_rst 12>, <&sys_rst 15>;
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};
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usb1_rst: reset@40 {
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compatible = "socionext,uniphier-pro4-usb3-reset";
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reg = <0x40 0x4>;
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#reset-cells = <1>;
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clock-names = "gio", "link";
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clocks = <&sys_clk 12>, <&sys_clk 15>;
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reset-names = "gio", "link";
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resets = <&sys_rst 12>, <&sys_rst 15>;
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};
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};
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nand: nand@68000000 {
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compatible = "socionext,uniphier-denali-nand-v5a";
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status = "disabled";
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@ -90,3 +90,11 @@
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reg = <1>;
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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@ -91,3 +91,7 @@
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reg = <1>;
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};
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};
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&usb0 {
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status = "okay";
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};
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@ -579,6 +579,186 @@
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};
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};
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usb0: usb@65a00000 {
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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65a00000 0xcd00>;
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interrupt-names = "host", "peripheral";
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interrupts = <0 134 4>, <0 135 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
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clock-names = "ref", "bus_early", "suspend";
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clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
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resets = <&usb0_rst 15>;
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phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
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<&usb0_ssphy0>, <&usb0_ssphy1>;
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dr_mode = "host";
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};
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-pxs2-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb0_rst: reset@0 {
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compatible = "socionext,uniphier-pxs2-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb0_vbus0: regulator@100 {
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compatible = "socionext,uniphier-pxs2-usb3-regulator";
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reg = <0x100 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb0_vbus1: regulator@110 {
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compatible = "socionext,uniphier-pxs2-usb3-regulator";
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reg = <0x110 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb0_hsphy0: hs-phy@200 {
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compatible = "socionext,uniphier-pxs2-usb3-hsphy";
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reg = <0x200 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 16>;
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vbus-supply = <&usb0_vbus0>;
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};
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usb0_hsphy1: hs-phy@210 {
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compatible = "socionext,uniphier-pxs2-usb3-hsphy";
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reg = <0x210 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 16>;
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vbus-supply = <&usb0_vbus1>;
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};
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usb0_ssphy0: ss-phy@300 {
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compatible = "socionext,uniphier-pxs2-usb3-ssphy";
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reg = <0x300 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 17>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 17>;
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vbus-supply = <&usb0_vbus0>;
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};
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usb0_ssphy1: ss-phy@310 {
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compatible = "socionext,uniphier-pxs2-usb3-ssphy";
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reg = <0x310 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 18>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 18>;
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vbus-supply = <&usb0_vbus1>;
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};
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};
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usb1: usb@65c00000 {
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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65c00000 0xcd00>;
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interrupt-names = "host", "peripheral";
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interrupts = <0 137 4>, <0 138 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
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clock-names = "ref", "bus_early", "suspend";
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clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
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resets = <&usb1_rst 15>;
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phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
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dr_mode = "host";
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};
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usb-glue@65d00000 {
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compatible = "socionext,uniphier-pxs2-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65d00000 0x400>;
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usb1_rst: reset@0 {
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compatible = "socionext,uniphier-pxs2-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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clock-names = "link";
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clocks = <&sys_clk 15>;
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reset-names = "link";
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resets = <&sys_rst 15>;
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};
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usb1_vbus0: regulator@100 {
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compatible = "socionext,uniphier-pxs2-usb3-regulator";
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reg = <0x100 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 15>;
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reset-names = "link";
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resets = <&sys_rst 15>;
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};
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usb1_vbus1: regulator@110 {
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compatible = "socionext,uniphier-pxs2-usb3-regulator";
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reg = <0x110 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 15>;
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reset-names = "link";
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resets = <&sys_rst 15>;
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};
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usb1_hsphy0: hs-phy@200 {
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compatible = "socionext,uniphier-pxs2-usb3-hsphy";
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reg = <0x200 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 15>, <&sys_clk 20>;
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reset-names = "link", "phy";
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resets = <&sys_rst 15>, <&sys_rst 20>;
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vbus-supply = <&usb1_vbus0>;
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};
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usb1_hsphy1: hs-phy@210 {
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compatible = "socionext,uniphier-pxs2-usb3-hsphy";
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reg = <0x210 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 15>, <&sys_clk 20>;
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reset-names = "link", "phy";
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resets = <&sys_rst 15>, <&sys_rst 20>;
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vbus-supply = <&usb1_vbus1>;
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};
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usb1_ssphy0: ss-phy@300 {
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compatible = "socionext,uniphier-pxs2-usb3-ssphy";
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reg = <0x300 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 15>, <&sys_clk 21>;
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reset-names = "link", "phy";
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resets = <&sys_rst 15>, <&sys_rst 21>;
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vbus-supply = <&usb1_vbus0>;
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};
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};
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nand: nand@68000000 {
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compatible = "socionext,uniphier-denali-nand-v5b";
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status = "disabled";
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