gpio: clarify open drain/source docs
Make the text clearer, remove reference to confusing "positive" and "negative" and elaborate a bit. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -100,6 +100,10 @@ Both usecases require that the line be equipped with a pull-up resistor. This
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resistor will make the line tend to high level unless one of the transistors on
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resistor will make the line tend to high level unless one of the transistors on
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the rail actively pulls it down.
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the rail actively pulls it down.
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The level on the line will go as high as the VDD on the pull-up resistor, which
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may be higher than the level supported by the transistor, achieveing a
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level-shift to the higher VDD.
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Integrated electronics often have an output driver stage in the form of a CMOS
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Integrated electronics often have an output driver stage in the form of a CMOS
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"totem-pole" with one N-MOS and one P-MOS transistor where one of them drives
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"totem-pole" with one N-MOS and one P-MOS transistor where one of them drives
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the line high and one of them drives the line low. This is called a push-pull
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the line high and one of them drives the line low. This is called a push-pull
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@ -110,14 +114,18 @@ output. The "totem-pole" looks like so:
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OD ||--+
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OD ||--+
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+--/ ---o|| P-MOS-FET
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+--/ ---o|| P-MOS-FET
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in --+ +----- out
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IN --+ +----- out
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+--/ ----|| N-MOS-FET
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+--/ ----|| N-MOS-FET
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OS ||--+
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OS ||--+
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GND
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GND
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You see the little "switches" named "OD" and "OS" that enable/disable the
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The desired output signal (e.g. coming directly from some GPIO output register)
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arrives at IN. The switches named "OD" and "OS" are normally closed, creating
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a push-pull circuit.
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Consider the little "switches" named "OD" and "OS" that enable/disable the
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P-MOS or N-MOS transistor right after the split of the input. As you can see,
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P-MOS or N-MOS transistor right after the split of the input. As you can see,
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either transistor will go totally numb if this switch is open. The totem-pole
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either transistor will go totally numb if this switch is open. The totem-pole
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is then halved and give high impedance instead of actively driving the line
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is then halved and give high impedance instead of actively driving the line
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@ -128,8 +136,8 @@ Some GPIO hardware come in open drain / open source configuration. Some are
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hard-wired lines that will only support open drain or open source no matter
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hard-wired lines that will only support open drain or open source no matter
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what: there is only one transistor there. Some are software-configurable:
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what: there is only one transistor there. Some are software-configurable:
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by flipping a bit in a register the output can be configured as open drain
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by flipping a bit in a register the output can be configured as open drain
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or open source, by flicking open the switches labeled "OD" and "OS" in the
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or open source, in practice by flicking open the switches labeled "OD" and "OS"
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drawing above.
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in the drawing above.
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By disabling the P-MOS transistor, the output can be driven between GND and
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By disabling the P-MOS transistor, the output can be driven between GND and
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high impedance (open drain), and by disabling the N-MOS transistor, the output
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high impedance (open drain), and by disabling the N-MOS transistor, the output
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@ -146,8 +154,8 @@ set in the machine file, or coming from other hardware descriptions.
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If this state can not be configured in hardware, i.e. if the GPIO hardware does
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If this state can not be configured in hardware, i.e. if the GPIO hardware does
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not support open drain/open source in hardware, the GPIO library will instead
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not support open drain/open source in hardware, the GPIO library will instead
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use a trick: when a line is set as output, if the line is flagged as open
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use a trick: when a line is set as output, if the line is flagged as open
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drain, and the output value is negative, it will be driven low as usual. But
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drain, and the IN output value is low, it will be driven low as usual. But
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if the output value is set to positive, it will instead *NOT* be driven high,
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if the IN output value is set to high, it will instead *NOT* be driven high,
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instead it will be switched to input, as input mode is high impedance, thus
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instead it will be switched to input, as input mode is high impedance, thus
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achieveing an "open drain emulation" of sorts: electrically the behaviour will
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achieveing an "open drain emulation" of sorts: electrically the behaviour will
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be identical, with the exception of possible hardware glitches when switching
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be identical, with the exception of possible hardware glitches when switching
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