mtd: denali: fix the format of comment blocks
We should use
/*
* Blah Blah ...
* ...
*/
for multi-line comment blocks.
In addition, refactor some comments where it seems reasonable and
remove some comments where the code is clear enough such as:
/* clear interrupts */
clear_interrupts(denali);
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Masahiro Yamada
Brian Norris
parent
7622d4905a
commit
43914a2dcc
@ -29,7 +29,8 @@
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MODULE_LICENSE("GPL");
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/* We define a module parameter that allows the user to override
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/*
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* We define a module parameter that allows the user to override
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* the hardware and decide what timing mode should be used.
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*/
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#define NAND_DEFAULT_TIMINGS -1
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@ -41,8 +42,10 @@ MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
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#define DENALI_NAND_NAME "denali-nand"
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/* We define a macro here that combines all interrupts this driver uses into
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* a single constant value, for convenience. */
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/*
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* We define a macro here that combines all interrupts this driver uses into
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* a single constant value, for convenience.
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*/
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#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
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INTR_STATUS__ECC_TRANSACTION_DONE | \
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INTR_STATUS__ECC_ERR | \
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@ -54,23 +57,30 @@ MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
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INTR_STATUS__RST_COMP | \
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INTR_STATUS__ERASE_COMP)
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/* indicates whether or not the internal value for the flash bank is
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* valid or not */
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/*
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* indicates whether or not the internal value for the flash bank is
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* valid or not
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*/
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#define CHIP_SELECT_INVALID -1
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#define SUPPORT_8BITECC 1
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/* This macro divides two integers and rounds fractional values up
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* to the nearest integer value. */
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/*
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* This macro divides two integers and rounds fractional values up
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* to the nearest integer value.
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*/
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#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
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/* this macro allows us to convert from an MTD structure to our own
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/*
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* this macro allows us to convert from an MTD structure to our own
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* device context (denali) structure.
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*/
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#define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
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/* These constants are defined by the driver to enable common driver
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* configuration options. */
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/*
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* These constants are defined by the driver to enable common driver
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* configuration options.
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*/
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#define SPARE_ACCESS 0x41
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#define MAIN_ACCESS 0x42
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#define MAIN_SPARE_ACCESS 0x43
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@ -84,8 +94,10 @@ MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
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#define ADDR_CYCLE 1
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#define STATUS_CYCLE 2
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/* this is a helper macro that allows us to
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* format the bank into the proper bits for the controller */
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/*
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* this is a helper macro that allows us to
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* format the bank into the proper bits for the controller
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*/
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#define BANK(x) ((x) << 24)
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/* forward declarations */
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@ -96,12 +108,12 @@ static void denali_irq_enable(struct denali_nand_info *denali,
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uint32_t int_mask);
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static uint32_t read_interrupt_status(struct denali_nand_info *denali);
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/* Certain operations for the denali NAND controller use
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* an indexed mode to read/write data. The operation is
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* performed by writing the address value of the command
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* to the device memory followed by the data. This function
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/*
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* Certain operations for the denali NAND controller use an indexed mode to
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* read/write data. The operation is performed by writing the address value
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* of the command to the device memory followed by the data. This function
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* abstracts this common operation.
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*/
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*/
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static void index_addr(struct denali_nand_info *denali,
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uint32_t address, uint32_t data)
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{
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@ -117,8 +129,10 @@ static void index_addr_read_data(struct denali_nand_info *denali,
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*pdata = ioread32(denali->flash_mem + 0x10);
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}
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/* We need to buffer some data for some of the NAND core routines.
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* The operations manage buffering that data. */
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/*
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* We need to buffer some data for some of the NAND core routines.
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* The operations manage buffering that data.
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*/
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static void reset_buf(struct denali_nand_info *denali)
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{
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denali->buf.head = denali->buf.tail = 0;
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@ -192,7 +206,8 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali)
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return PASS;
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}
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/* this routine calculates the ONFI timing values for a given mode and
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/*
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* this routine calculates the ONFI timing values for a given mode and
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* programs the clocking register accordingly. The mode is determined by
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* the get_onfi_nand_para routine.
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*/
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@ -298,9 +313,11 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali,
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static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
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{
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int i;
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/* we needn't to do a reset here because driver has already
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/*
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* we needn't to do a reset here because driver has already
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* reset all the banks before
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* */
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*/
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if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
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ONFI_TIMING_MODE__VALUE))
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return FAIL;
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@ -313,8 +330,10 @@ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
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nand_onfi_timing_set(denali, i);
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/* By now, all the ONFI devices we know support the page cache */
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/* rw feature. So here we enable the pipeline_rw_ahead feature */
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/*
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* By now, all the ONFI devices we know support the page cache
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* rw feature. So here we enable the pipeline_rw_ahead feature
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*/
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/* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
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/* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
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@ -340,8 +359,10 @@ static void get_toshiba_nand_para(struct denali_nand_info *denali)
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{
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uint32_t tmp;
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/* Workaround to fix a controller bug which reports a wrong */
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/* spare area size for some kind of Toshiba NAND device */
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/*
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* Workaround to fix a controller bug which reports a wrong
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* spare area size for some kind of Toshiba NAND device
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*/
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if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
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(ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
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iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
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@ -391,7 +412,8 @@ static void get_hynix_nand_para(struct denali_nand_info *denali,
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}
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}
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/* determines how many NAND chips are connected to the controller. Note for
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/*
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* determines how many NAND chips are connected to the controller. Note for
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* Intel CE4100 devices we don't support more than one device.
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*/
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static void find_valid_banks(struct denali_nand_info *denali)
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@ -421,7 +443,8 @@ static void find_valid_banks(struct denali_nand_info *denali)
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}
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if (denali->platform == INTEL_CE4100) {
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/* Platform limitations of the CE4100 device limit
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/*
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* Platform limitations of the CE4100 device limit
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* users to a single chip solution for NAND.
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* Multichip support is not enabled.
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*/
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@ -449,12 +472,13 @@ static void detect_max_banks(struct denali_nand_info *denali)
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static void detect_partition_feature(struct denali_nand_info *denali)
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{
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/* For MRST platform, denali->fwblks represent the
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/*
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* For MRST platform, denali->fwblks represent the
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* number of blocks firmware is taken,
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* FW is in protect partition and MTD driver has no
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* permission to access it. So let driver know how many
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* blocks it can't touch.
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* */
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*/
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if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
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if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) &
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PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
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@ -481,11 +505,11 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
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"%s, Line %d, Function: %s\n",
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__FILE__, __LINE__, __func__);
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/* Use read id method to get device ID and other
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* params. For some NAND chips, controller can't
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* report the correct device ID by reading from
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* DEVICE_ID register
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* */
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/*
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* Use read id method to get device ID and other params.
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* For some NAND chips, controller can't report the correct
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* device ID by reading from DEVICE_ID register
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*/
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addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
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index_addr(denali, (uint32_t)addr | 0, 0x90);
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index_addr(denali, (uint32_t)addr | 1, 0);
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@ -524,7 +548,8 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
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detect_partition_feature(denali);
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/* If the user specified to override the default timings
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/*
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* If the user specified to override the default timings
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* with a specific ONFI mode, we apply those changes here.
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*/
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if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
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@ -545,7 +570,8 @@ static void denali_set_intr_modes(struct denali_nand_info *denali,
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iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
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}
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/* validation function to verify that the controlling software is making
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/*
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* validation function to verify that the controlling software is making
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* a valid request
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*/
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static inline bool is_flash_bank_valid(int flash_bank)
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@ -585,7 +611,8 @@ static void denali_irq_enable(struct denali_nand_info *denali,
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iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
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}
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/* This function only returns when an interrupt that this driver cares about
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/*
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* This function only returns when an interrupt that this driver cares about
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* occurs. This is to reduce the overhead of servicing interrupts
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*/
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static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
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@ -625,9 +652,9 @@ static uint32_t read_interrupt_status(struct denali_nand_info *denali)
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return ioread32(denali->flash_reg + intr_status_reg);
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}
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/* This is the interrupt service routine. It handles all interrupts
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* sent to this device. Note that on CE4100, this is a shared
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* interrupt.
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/*
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* This is the interrupt service routine. It handles all interrupts
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* sent to this device. Note that on CE4100, this is a shared interrupt.
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*/
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static irqreturn_t denali_isr(int irq, void *dev_id)
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{
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@ -637,19 +664,21 @@ static irqreturn_t denali_isr(int irq, void *dev_id)
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spin_lock(&denali->irq_lock);
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/* check to see if a valid NAND chip has
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* been selected.
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*/
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/* check to see if a valid NAND chip has been selected. */
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if (is_flash_bank_valid(denali->flash_bank)) {
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/* check to see if controller generated
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* the interrupt, since this is a shared interrupt */
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/*
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* check to see if controller generated the interrupt,
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* since this is a shared interrupt
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*/
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irq_status = denali_irq_detected(denali);
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if (irq_status != 0) {
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/* handle interrupt */
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/* first acknowledge it */
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clear_interrupt(denali, irq_status);
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/* store the status in the device context for someone
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to read */
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/*
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* store the status in the device context for someone
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* to read
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*/
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denali->irq_status |= irq_status;
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/* notify anyone who cares that it happened */
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complete(&denali->complete);
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@ -681,8 +710,10 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
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/* our interrupt was detected */
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break;
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} else {
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/* these are not the interrupts you are looking for -
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* need to wait again */
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/*
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* these are not the interrupts you are looking for -
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* need to wait again
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*/
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spin_unlock_irq(&denali->irq_lock);
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retry = true;
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}
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@ -698,8 +729,10 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
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return intr_status;
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}
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/* This helper function setups the registers for ECC and whether or not
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* the spare area will be transferred. */
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/*
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* This helper function setups the registers for ECC and whether or not
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* the spare area will be transferred.
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*/
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static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
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bool transfer_spare)
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{
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@ -715,7 +748,8 @@ static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
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denali->flash_reg + TRANSFER_SPARE_REG);
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}
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/* sends a pipeline command operation to the controller. See the Denali NAND
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/*
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* sends a pipeline command operation to the controller. See the Denali NAND
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* controller's user guide for more information (section 4.2.3.6).
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*/
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static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
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@ -737,7 +771,6 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
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setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
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/* clear interrupts */
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clear_interrupts(denali);
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addr = BANK(denali->flash_bank) | denali->page;
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@ -757,9 +790,10 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
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cmd = MODE_10 | addr;
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index_addr(denali, (uint32_t)cmd, access_type);
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/* page 33 of the NAND controller spec indicates we should not
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use the pipeline commands in Spare area only mode. So we
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don't.
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/*
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* page 33 of the NAND controller spec indicates we should not
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* use the pipeline commands in Spare area only mode.
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* So we don't.
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*/
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if (access_type == SPARE_ACCESS) {
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cmd = MODE_01 | addr;
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@ -768,10 +802,11 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
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index_addr(denali, (uint32_t)cmd,
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PIPELINE_ACCESS | op | page_count);
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/* wait for command to be accepted
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/*
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* wait for command to be accepted
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* can always use status0 bit as the
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* mask is identical for each
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* bank. */
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* mask is identical for each bank.
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*/
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status == 0) {
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@ -796,8 +831,10 @@ static int write_data_to_flash_mem(struct denali_nand_info *denali,
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{
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uint32_t i = 0, *buf32;
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/* verify that the len is a multiple of 4. see comment in
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* read_data_from_flash_mem() */
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/*
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* verify that the len is a multiple of 4.
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* see comment in read_data_from_flash_mem()
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*/
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BUG_ON((len % 4) != 0);
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/* write the data to the flash memory */
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@ -814,14 +851,12 @@ static int read_data_from_flash_mem(struct denali_nand_info *denali,
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{
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uint32_t i = 0, *buf32;
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/* we assume that len will be a multiple of 4, if not
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* it would be nice to know about it ASAP rather than
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* have random failures...
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* This assumption is based on the fact that this
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* function is designed to be used to read flash pages,
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* which are typically multiples of 4...
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/*
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* we assume that len will be a multiple of 4, if not it would be nice
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* to know about it ASAP rather than have random failures...
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* This assumption is based on the fact that this function is designed
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* to be used to read flash pages, which are typically multiples of 4.
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*/
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BUG_ON((len % 4) != 0);
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/* transfer the data from the flash */
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@ -873,16 +908,19 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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DENALI_READ) == PASS) {
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read_data_from_flash_mem(denali, buf, mtd->oobsize);
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/* wait for command to be accepted
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* can always use status0 bit as the mask is identical for each
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* bank. */
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/*
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* wait for command to be accepted
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* can always use status0 bit as the
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* mask is identical for each bank.
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*/
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status == 0)
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dev_err(denali->dev, "page on OOB timeout %d\n",
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denali->page);
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/* We set the device back to MAIN_ACCESS here as I observed
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/*
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* We set the device back to MAIN_ACCESS here as I observed
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* instability with the controller if you do a block erase
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* and the last transaction was a SPARE_ACCESS. Block erase
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* is reliable (according to the MTD test infrastructure)
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@ -894,7 +932,8 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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}
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}
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/* this function examines buffers to see if they contain data that
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/*
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* this function examines buffers to see if they contain data that
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* indicate that the buffer is part of an erased region of flash.
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*/
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static bool is_erased(uint8_t *buf, int len)
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@ -940,13 +979,14 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
|
||||
err_device = ECC_ERR_DEVICE(err_correction_info);
|
||||
|
||||
if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
|
||||
/* If err_byte is larger than ECC_SECTOR_SIZE,
|
||||
/*
|
||||
* If err_byte is larger than ECC_SECTOR_SIZE,
|
||||
* means error happened in OOB, so we ignore
|
||||
* it. It's no need for us to correct it
|
||||
* err_device is represented the NAND error
|
||||
* bits are happened in if there are more
|
||||
* than one NAND connected.
|
||||
* */
|
||||
*/
|
||||
if (err_byte < ECC_SECTOR_SIZE) {
|
||||
int offset;
|
||||
offset = (err_sector *
|
||||
@ -960,17 +1000,19 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
|
||||
bitflips++;
|
||||
}
|
||||
} else {
|
||||
/* if the error is not correctable, need to
|
||||
/*
|
||||
* if the error is not correctable, need to
|
||||
* look at the page to see if it is an erased
|
||||
* page. if so, then it's not a real ECC error
|
||||
* */
|
||||
*/
|
||||
check_erased_page = true;
|
||||
}
|
||||
} while (!ECC_LAST_ERR(err_correction_info));
|
||||
/* Once handle all ecc errors, controller will triger
|
||||
/*
|
||||
* Once handle all ecc errors, controller will triger
|
||||
* a ECC_TRANSACTION_DONE interrupt, so here just wait
|
||||
* for a while for this interrupt
|
||||
* */
|
||||
*/
|
||||
while (!(read_interrupt_status(denali) &
|
||||
INTR_STATUS__ECC_TRANSACTION_DONE))
|
||||
cpu_relax();
|
||||
@ -1013,12 +1055,14 @@ static void denali_setup_dma(struct denali_nand_info *denali, int op)
|
||||
/* 3. set memory low address bits 23:8 */
|
||||
index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300);
|
||||
|
||||
/* 4. interrupt when complete, burst len = 64 bytes*/
|
||||
/* 4. interrupt when complete, burst len = 64 bytes */
|
||||
index_addr(denali, mode | 0x14000, 0x2400);
|
||||
}
|
||||
|
||||
/* writes a page. user specifies type, and this function handles the
|
||||
* configuration details. */
|
||||
/*
|
||||
* writes a page. user specifies type, and this function handles the
|
||||
* configuration details.
|
||||
*/
|
||||
static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf, bool raw_xfer)
|
||||
{
|
||||
@ -1031,8 +1075,8 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
|
||||
INTR_STATUS__PROGRAM_FAIL;
|
||||
|
||||
/* if it is a raw xfer, we want to disable ecc, and send
|
||||
* the spare area.
|
||||
/*
|
||||
* if it is a raw xfer, we want to disable ecc and send the spare area.
|
||||
* !raw_xfer - enable ecc
|
||||
* raw_xfer - transfer spare
|
||||
*/
|
||||
@ -1073,27 +1117,33 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
|
||||
/* NAND core entry points */
|
||||
|
||||
/* this is the callback that the NAND core calls to write a page. Since
|
||||
/*
|
||||
* this is the callback that the NAND core calls to write a page. Since
|
||||
* writing a page with ECC or without is similar, all the work is done
|
||||
* by write_page above.
|
||||
* */
|
||||
*/
|
||||
static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf, int oob_required)
|
||||
{
|
||||
/* for regular page writes, we let HW handle all the ECC
|
||||
* data written to the device. */
|
||||
/*
|
||||
* for regular page writes, we let HW handle all the ECC
|
||||
* data written to the device.
|
||||
*/
|
||||
return write_page(mtd, chip, buf, false);
|
||||
}
|
||||
|
||||
/* This is the callback that the NAND core calls to write a page without ECC.
|
||||
/*
|
||||
* This is the callback that the NAND core calls to write a page without ECC.
|
||||
* raw access is similar to ECC page writes, so all the work is done in the
|
||||
* write_page() function above.
|
||||
*/
|
||||
static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf, int oob_required)
|
||||
{
|
||||
/* for raw page writes, we want to disable ECC and simply write
|
||||
whatever data is in the buffer. */
|
||||
/*
|
||||
* for raw page writes, we want to disable ECC and simply write
|
||||
* whatever data is in the buffer.
|
||||
*/
|
||||
return write_page(mtd, chip, buf, true);
|
||||
}
|
||||
|
||||
@ -1238,7 +1288,6 @@ static int denali_erase(struct mtd_info *mtd, int page)
|
||||
|
||||
uint32_t cmd = 0x0, irq_status = 0;
|
||||
|
||||
/* clear interrupts */
|
||||
clear_interrupts(denali);
|
||||
|
||||
/* setup page read request for access type */
|
||||
@ -1268,10 +1317,11 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
|
||||
case NAND_CMD_READID:
|
||||
case NAND_CMD_PARAM:
|
||||
reset_buf(denali);
|
||||
/*sometimes ManufactureId read from register is not right
|
||||
/*
|
||||
* sometimes ManufactureId read from register is not right
|
||||
* e.g. some of Micron MT29F32G08QAA MLC NAND chips
|
||||
* So here we send READID cmd to NAND insteand
|
||||
* */
|
||||
*/
|
||||
addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
|
||||
index_addr(denali, (uint32_t)addr | 0, 0x90);
|
||||
index_addr(denali, (uint32_t)addr | 1, 0);
|
||||
@ -1331,11 +1381,12 @@ static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
|
||||
/* Initialization code to bring the device up to a known good state */
|
||||
static void denali_hw_init(struct denali_nand_info *denali)
|
||||
{
|
||||
/* tell driver how many bit controller will skip before
|
||||
/*
|
||||
* tell driver how many bit controller will skip before
|
||||
* writing ECC code in OOB, this register may be already
|
||||
* set by firmware. So we read this value out.
|
||||
* if this value is 0, just let it be.
|
||||
* */
|
||||
*/
|
||||
denali->bbtskipbytes = ioread32(denali->flash_reg +
|
||||
SPARE_AREA_SKIP_BYTES);
|
||||
detect_max_banks(denali);
|
||||
@ -1353,10 +1404,11 @@ static void denali_hw_init(struct denali_nand_info *denali)
|
||||
denali_irq_init(denali);
|
||||
}
|
||||
|
||||
/* Althogh controller spec said SLC ECC is forceb to be 4bit,
|
||||
/*
|
||||
* Althogh controller spec said SLC ECC is forceb to be 4bit,
|
||||
* but denali controller in MRST only support 15bit and 8bit ECC
|
||||
* correction
|
||||
* */
|
||||
*/
|
||||
#define ECC_8BITS 14
|
||||
static struct nand_ecclayout nand_8bit_oob = {
|
||||
.eccbytes = 14,
|
||||
@ -1396,13 +1448,16 @@ static void denali_drv_init(struct denali_nand_info *denali)
|
||||
denali->idx = 0;
|
||||
|
||||
/* setup interrupt handler */
|
||||
/* the completion object will be used to notify
|
||||
* the callee that the interrupt is done */
|
||||
/*
|
||||
* the completion object will be used to notify
|
||||
* the callee that the interrupt is done
|
||||
*/
|
||||
init_completion(&denali->complete);
|
||||
|
||||
/* the spinlock will be used to synchronize the ISR
|
||||
* with any element that might be access shared
|
||||
* data (interrupt status) */
|
||||
/*
|
||||
* the spinlock will be used to synchronize the ISR with any
|
||||
* element that might be access shared data (interrupt status)
|
||||
*/
|
||||
spin_lock_init(&denali->irq_lock);
|
||||
|
||||
/* indicate that MTD has not selected a valid bank yet */
|
||||
@ -1417,7 +1472,8 @@ int denali_init(struct denali_nand_info *denali)
|
||||
int ret;
|
||||
|
||||
if (denali->platform == INTEL_CE4100) {
|
||||
/* Due to a silicon limitation, we can only support
|
||||
/*
|
||||
* Due to a silicon limitation, we can only support
|
||||
* ONFI timing mode 1 and below.
|
||||
*/
|
||||
if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
|
||||
@ -1436,8 +1492,10 @@ int denali_init(struct denali_nand_info *denali)
|
||||
denali_hw_init(denali);
|
||||
denali_drv_init(denali);
|
||||
|
||||
/* denali_isr register is done after all the hardware
|
||||
* initilization is finished*/
|
||||
/*
|
||||
* denali_isr register is done after all the hardware
|
||||
* initilization is finished
|
||||
*/
|
||||
if (request_irq(denali->irq, denali_isr, IRQF_SHARED,
|
||||
DENALI_NAND_NAME, denali)) {
|
||||
pr_err("Spectra: Unable to allocate IRQ\n");
|
||||
@ -1456,9 +1514,11 @@ int denali_init(struct denali_nand_info *denali)
|
||||
denali->nand.read_byte = denali_read_byte;
|
||||
denali->nand.waitfunc = denali_waitfunc;
|
||||
|
||||
/* scan for NAND devices attached to the controller
|
||||
/*
|
||||
* scan for NAND devices attached to the controller
|
||||
* this is the first stage in a two step process to register
|
||||
* with the nand subsystem */
|
||||
* with the nand subsystem
|
||||
*/
|
||||
if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
|
||||
ret = -ENXIO;
|
||||
goto failed_req_irq;
|
||||
@ -1490,10 +1550,10 @@ int denali_init(struct denali_nand_info *denali)
|
||||
goto failed_req_irq;
|
||||
}
|
||||
|
||||
/* support for multi nand
|
||||
* MTD known nothing about multi nand,
|
||||
* so we should tell it the real pagesize
|
||||
* and anything necessery
|
||||
/*
|
||||
* support for multi nand
|
||||
* MTD known nothing about multi nand, so we should tell it
|
||||
* the real pagesize and anything necessery
|
||||
*/
|
||||
denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
|
||||
denali->nand.chipsize <<= (denali->devnum - 1);
|
||||
@ -1509,9 +1569,11 @@ int denali_init(struct denali_nand_info *denali)
|
||||
denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
|
||||
denali->bbtskipbytes *= denali->devnum;
|
||||
|
||||
/* second stage of the NAND scan
|
||||
/*
|
||||
* second stage of the NAND scan
|
||||
* this stage requires information regarding ECC and
|
||||
* bad block management. */
|
||||
* bad block management.
|
||||
*/
|
||||
|
||||
/* Bad block management */
|
||||
denali->nand.bbt_td = &bbt_main_descr;
|
||||
@ -1522,7 +1584,8 @@ int denali_init(struct denali_nand_info *denali)
|
||||
denali->nand.options |= NAND_SKIP_BBTSCAN;
|
||||
denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
|
||||
|
||||
/* Denali Controller only support 15bit and 8bit ECC in MRST,
|
||||
/*
|
||||
* Denali Controller only support 15bit and 8bit ECC in MRST,
|
||||
* so just let controller do 15bit ECC for MLC and 8bit ECC for
|
||||
* SLC if possible.
|
||||
* */
|
||||
@ -1558,18 +1621,20 @@ int denali_init(struct denali_nand_info *denali)
|
||||
denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
|
||||
denali->bbtskipbytes;
|
||||
|
||||
/* Let driver know the total blocks number and
|
||||
* how many blocks contained by each nand chip.
|
||||
* blksperchip will help driver to know how many
|
||||
* blocks is taken by FW.
|
||||
* */
|
||||
/*
|
||||
* Let driver know the total blocks number and how many blocks
|
||||
* contained by each nand chip. blksperchip will help driver to
|
||||
* know how many blocks is taken by FW.
|
||||
*/
|
||||
denali->totalblks = denali->mtd.size >>
|
||||
denali->nand.phys_erase_shift;
|
||||
denali->blksperchip = denali->totalblks / denali->nand.numchips;
|
||||
|
||||
/* These functions are required by the NAND core framework, otherwise,
|
||||
/*
|
||||
* These functions are required by the NAND core framework, otherwise,
|
||||
* the NAND core will assert. However, we don't need them, so we'll stub
|
||||
* them out. */
|
||||
* them out.
|
||||
*/
|
||||
denali->nand.ecc.calculate = denali_ecc_calculate;
|
||||
denali->nand.ecc.correct = denali_ecc_correct;
|
||||
denali->nand.ecc.hwctl = denali_ecc_hwctl;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user