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drm/amd/powerplay: avoid double check feature enabled

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the unforce_dpm_levels doesn't need to check feature enablement.
because the smu_get_dpm_freq_range function has check feature logic.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Kevin Wang 2019-07-16 13:07:23 -05:00 committed by Alex Deucher
parent 75728f512e
commit 42b3aa9a5b
1 changed files with 8 additions and 15 deletions
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23
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
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@ -833,27 +833,20 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
return ret; return ret;
} }
static int navi10_unforce_dpm_levels(struct smu_context *smu) { static int navi10_unforce_dpm_levels(struct smu_context *smu)
{
int ret = 0, i = 0; int ret = 0, i = 0;
uint32_t min_freq, max_freq; uint32_t min_freq, max_freq;
enum smu_clk_type clk_type; enum smu_clk_type clk_type;
struct clk_feature_map { enum smu_clk_type clks[] = {
enum smu_clk_type clk_type; SMU_GFXCLK,
uint32_t feature; SMU_MCLK,
} clk_feature_map[] = { SMU_SOCCLK,
{SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
{SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT},
{SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
}; };
for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { for (i = 0; i < ARRAY_SIZE(clks); i++) {
if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature)) clk_type = clks[i];
continue;
clk_type = clk_feature_map[i].clk_type;
ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq); ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
if (ret) if (ret)
return ret; return ret;