forked from Minki/linux
imx6q cpuidle support for 3.9
- It's based on imx-cleanup-3.9 to avoid conflicts. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJRCRzjAAoJEFBXWFqHsHzOOTYH/2YiAhCXDoovJ++leTTBKoFO kRx2gvV0oxQYAjvRX4IiiwcuWjbCQI8ugiKxeH9Vn+jwHD8jKqzTINEUVQfKUud6 s8AI1/EqKwKnEFYFs/Fg6WxZHuHpoL/clpRB/5wZw1KoChmte2OnVU7d9vOt67iN l0P4nPR18iwU5LFoDCnqMX50Dp9C56KEF2JhzBCQKW9TtRclwpcBNy6AsHb/TNOe /nHN+Ku6/3xQEz2MPQ9QdmgFxnp9Pr8R6leJNg1Vg6UGRYrKxy0zVo+oFEXAZuUw v6gnhdlvO6Ki/IKHcWkw7Q7pUDTuB6SttirQE9mBlPdc0V3kTU82SVtX9WAQhSs= =rVol -----END PGP SIGNATURE----- Merge tag 'imx6q-cpudile-3.9' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc From Shawn Guo: imx6q cpuidle support for 3.9 - It's based on imx-cleanup-3.9 to avoid conflicts. * tag 'imx6q-cpudile-3.9' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: imx6q: support WAIT mode using cpuidle ARM: imx: move imx6q_cpuidle_driver into a separate file ARM: imx: mask gpc interrupts initially ARM: imx: return zero in case next event gets a large increment ARM: imx: Remove mx508 support ARM: imx: Remove mach-mx51_3ds board ARM: imx: use debug_ll_io_init() for imx6q ARM: imx: remove unused imx6q_clock_map_io() ARM: mach-imx: Kconfig: Do not select Babbage for MACH_IMX51_DT Signed-off-by: Olof Johansson <olof@lixom.net> Still, two delete/change conflicts caused by imx/cleanup: arch/arm/mach-imx/mach-mx50_rdp.c arch/arm/mach-imx/mach-mx51_3ds.c
This commit is contained in:
Olof Johansson
commit
4227961650
@ -219,12 +219,12 @@ choice
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Say Y here if you want kernel low-level debugging support
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on i.MX51.
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config DEBUG_IMX50_IMX53_UART
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bool "i.MX50 and i.MX53 Debug UART"
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depends on SOC_IMX50 || SOC_IMX53
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config DEBUG_IMX53_UART
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bool "i.MX53 Debug UART"
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depends on SOC_IMX53
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help
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Say Y here if you want kernel low-level debugging support
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on i.MX50 or i.MX53.
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on i.MX53.
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config DEBUG_IMX6Q_UART
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bool "i.MX6Q Debug UART"
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@ -518,7 +518,7 @@ config DEBUG_LL_INCLUDE
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DEBUG_IMX21_IMX27_UART || \
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DEBUG_IMX31_IMX35_UART || \
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DEBUG_IMX51_UART || \
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DEBUG_IMX50_IMX53_UART ||\
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DEBUG_IMX53_UART ||\
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DEBUG_IMX6Q_UART
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default "debug/highbank.S" if DEBUG_HIGHBANK_UART
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default "debug/mvebu.S" if DEBUG_MVEBU_UART
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@ -33,7 +33,6 @@ CONFIG_MACH_PCM043=y
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CONFIG_MACH_MX35_3DS=y
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CONFIG_MACH_VPR200=y
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CONFIG_MACH_IMX51_DT=y
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CONFIG_MACH_MX51_3DS=y
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CONFIG_MACH_EUKREA_CPUIMX51SD=y
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CONFIG_SOC_IMX53=y
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CONFIG_SOC_IMX6Q=y
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@ -34,7 +34,7 @@
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#define UART_PADDR 0x43f90000
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#elif defined (CONFIG_DEBUG_IMX51_UART)
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#define UART_PADDR 0x73fbc000
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#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
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#elif defined (CONFIG_DEBUG_IMX53_UART)
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#define UART_PADDR 0x53fbc000
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#elif defined (CONFIG_DEBUG_IMX6Q_UART)
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#define UART_PADDR IMX6Q_DEBUG_UART_BASE
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@ -95,9 +95,6 @@ config MACH_MX27
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config ARCH_MX5
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bool
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config ARCH_MX50
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bool
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config ARCH_MX51
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bool
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@ -164,11 +161,6 @@ config SOC_IMX5
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select CPU_V7
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select MXC_TZIC
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config SOC_IMX50
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bool
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select ARCH_MX50
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select SOC_IMX5
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config SOC_IMX51
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bool
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select ARCH_MX5
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@ -738,25 +730,10 @@ endif
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if ARCH_MULTI_V7
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comment "i.MX5 platforms:"
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config MACH_MX50_RDP
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bool "Support MX50 reference design platform"
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depends on BROKEN
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select IMX_HAVE_PLATFORM_IMX_I2C
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
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select IMX_HAVE_PLATFORM_SPI_IMX
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select SOC_IMX50
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help
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Include support for MX50 reference design platform (RDP) board. This
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includes specific configurations for the board and its peripherals.
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comment "i.MX51 machines:"
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config MACH_IMX51_DT
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bool "Support i.MX51 platforms from device tree"
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select MACH_MX51_BABBAGE
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select SOC_IMX51
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help
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Include support for Freescale i.MX51 based platforms
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@ -777,19 +754,6 @@ config MACH_MX51_BABBAGE
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u-boot. This includes specific configurations for the board and its
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peripherals.
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config MACH_MX51_3DS
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bool "Support MX51PDK (3DS)"
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select IMX_HAVE_PLATFORM_IMX2_WDT
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select IMX_HAVE_PLATFORM_IMX_KEYPAD
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
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select IMX_HAVE_PLATFORM_SPI_IMX
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select MXC_DEBUG_BOARD
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select SOC_IMX51
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help
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Include support for MX51PDK (3DS) platform. This includes specific
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configurations for the board and its peripherals.
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config MACH_EUKREA_CPUIMX51SD
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bool "Support Eukrea CPUIMX51SD module"
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select IMX_HAVE_PLATFORM_FSL_USB2_UDC
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@ -28,7 +28,11 @@ obj-$(CONFIG_MXC_ULPI) += ulpi.o
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obj-$(CONFIG_MXC_USE_EPIT) += epit.o
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obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
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obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
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obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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ifeq ($(CONFIG_CPU_IDLE),y)
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obj-y += cpuidle.o
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obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
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endif
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ifdef CONFIG_SND_IMX_SOC
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obj-y += ssi-fiq.o
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@ -88,7 +92,6 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
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obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
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obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
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obj-$(CONFIG_DEBUG_LL) += lluart.o
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obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
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obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
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obj-$(CONFIG_HAVE_IMX_SRC) += src.o
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@ -103,10 +106,8 @@ endif
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# i.MX5 based machines
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obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
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obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
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obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
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obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
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obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
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obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
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obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
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@ -22,10 +22,6 @@ zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000
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params_phys-$(CONFIG_SOC_IMX35) := 0x80000100
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initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
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zreladdr-$(CONFIG_SOC_IMX50) += 0x70008000
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params_phys-$(CONFIG_SOC_IMX50) := 0x70000100
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initrd_phys-$(CONFIG_SOC_IMX50) := 0x70800000
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zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000
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params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
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initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
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@ -54,9 +54,18 @@
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#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
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#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
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#define CGPR 0x64
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#define BM_CGPR_CHICKEN_BIT (0x1 << 17)
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static void __iomem *ccm_base;
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void __init imx6q_clock_map_io(void) { }
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void imx6q_set_chicken_bit(void)
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{
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u32 val = readl_relaxed(ccm_base + CGPR);
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val |= BM_CGPR_CHICKEN_BIT;
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writel_relaxed(val, ccm_base + CGPR);
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}
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int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
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{
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@ -68,6 +77,7 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
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break;
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case WAIT_UNCLOCKED:
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val |= 0x1 << BP_CLPCR_LPM;
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val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
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break;
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case STOP_POWER_ON:
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val |= 0x2 << BP_CLPCR_LPM;
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@ -21,7 +21,6 @@ extern void mx25_map_io(void);
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extern void mx27_map_io(void);
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extern void mx31_map_io(void);
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extern void mx35_map_io(void);
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extern void mx50_map_io(void);
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extern void mx51_map_io(void);
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extern void mx53_map_io(void);
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extern void imx1_init_early(void);
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@ -30,7 +29,6 @@ extern void imx25_init_early(void);
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extern void imx27_init_early(void);
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extern void imx31_init_early(void);
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extern void imx35_init_early(void);
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extern void imx50_init_early(void);
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extern void imx51_init_early(void);
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extern void imx53_init_early(void);
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extern void mxc_init_irq(void __iomem *);
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@ -41,7 +39,6 @@ extern void mx25_init_irq(void);
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extern void mx27_init_irq(void);
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extern void mx31_init_irq(void);
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extern void mx35_init_irq(void);
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extern void mx50_init_irq(void);
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extern void mx51_init_irq(void);
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extern void mx53_init_irq(void);
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extern void imx1_soc_init(void);
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@ -50,7 +47,6 @@ extern void imx25_soc_init(void);
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extern void imx27_soc_init(void);
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extern void imx31_soc_init(void);
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extern void imx35_soc_init(void);
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extern void imx50_soc_init(void);
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extern void imx51_soc_init(void);
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extern void imx51_init_late(void);
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extern void imx53_init_late(void);
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@ -109,26 +105,22 @@ void tzic_handle_irq(struct pt_regs *);
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#define imx27_handle_irq avic_handle_irq
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#define imx31_handle_irq avic_handle_irq
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#define imx35_handle_irq avic_handle_irq
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#define imx50_handle_irq tzic_handle_irq
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#define imx51_handle_irq tzic_handle_irq
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#define imx53_handle_irq tzic_handle_irq
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extern void imx_enable_cpu(int cpu, bool enable);
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extern void imx_set_cpu_jump(int cpu, void *jump_addr);
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#ifdef CONFIG_DEBUG_LL
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extern void imx_lluart_map_io(void);
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#else
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static inline void imx_lluart_map_io(void) {}
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#endif
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extern void v7_cpu_resume(void);
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extern u32 *pl310_get_save_ptr(void);
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#ifdef CONFIG_SMP
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extern void v7_secondary_startup(void);
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extern void imx_scu_map_io(void);
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extern void imx_smp_prepare(void);
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extern void imx_scu_standby_enable(void);
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#else
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static inline void imx_scu_map_io(void) {}
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static inline void imx_smp_prepare(void) {}
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static inline void imx_scu_standby_enable(void) {}
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#endif
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extern void imx_enable_cpu(int cpu, bool enable);
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extern void imx_set_cpu_jump(int cpu, void *jump_addr);
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@ -138,7 +130,7 @@ extern void imx_gpc_init(void);
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extern void imx_gpc_pre_suspend(void);
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extern void imx_gpc_post_resume(void);
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extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
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extern void imx6q_clock_map_io(void);
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extern void imx6q_set_chicken_bit(void);
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extern void imx_cpu_die(unsigned int cpu);
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@ -22,7 +22,6 @@
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static int mx5_cpu_rev = -1;
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#define IIM_SREV 0x24
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#define MX50_HW_ADADIG_DIGPROG 0xB0
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static int get_mx51_srev(void)
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{
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@ -108,41 +107,3 @@ int mx53_revision(void)
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return mx5_cpu_rev;
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}
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EXPORT_SYMBOL(mx53_revision);
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|
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static int get_mx50_srev(void)
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{
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void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
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u32 rev;
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|
||||
if (!anatop) {
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mx5_cpu_rev = -EINVAL;
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return 0;
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||||
}
|
||||
|
||||
rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
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||||
rev &= 0xff;
|
||||
|
||||
iounmap(anatop);
|
||||
if (rev == 0x0)
|
||||
return IMX_CHIP_REVISION_1_0;
|
||||
else if (rev == 0x1)
|
||||
return IMX_CHIP_REVISION_1_1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Returns:
|
||||
* the silicon revision of the cpu
|
||||
* -EINVAL - not a mx50
|
||||
*/
|
||||
int mx50_revision(void)
|
||||
{
|
||||
if (!cpu_is_mx50())
|
||||
return -EINVAL;
|
||||
|
||||
if (mx5_cpu_rev == -1)
|
||||
mx5_cpu_rev = get_mx50_srev();
|
||||
|
||||
return mx5_cpu_rev;
|
||||
}
|
||||
EXPORT_SYMBOL(mx50_revision);
|
||||
|
||||
95
arch/arm/mach-imx/cpuidle-imx6q.c
Normal file
95
arch/arm/mach-imx/cpuidle-imx6q.c
Normal file
@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/cpuidle.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/cpuidle.h>
|
||||
#include <asm/proc-fns.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "cpuidle.h"
|
||||
|
||||
static atomic_t master = ATOMIC_INIT(0);
|
||||
static DEFINE_SPINLOCK(master_lock);
|
||||
|
||||
static int imx6q_enter_wait(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv, int index)
|
||||
{
|
||||
int cpu = dev->cpu;
|
||||
|
||||
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
|
||||
|
||||
if (atomic_inc_return(&master) == num_online_cpus()) {
|
||||
/*
|
||||
* With this lock, we prevent other cpu to exit and enter
|
||||
* this function again and become the master.
|
||||
*/
|
||||
if (!spin_trylock(&master_lock))
|
||||
goto idle;
|
||||
imx6q_set_lpm(WAIT_UNCLOCKED);
|
||||
cpu_do_idle();
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
spin_unlock(&master_lock);
|
||||
goto done;
|
||||
}
|
||||
|
||||
idle:
|
||||
cpu_do_idle();
|
||||
done:
|
||||
atomic_dec(&master);
|
||||
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
|
||||
|
||||
return index;
|
||||
}
|
||||
|
||||
/*
|
||||
* For each cpu, setup the broadcast timer because local timer
|
||||
* stops for the states other than WFI.
|
||||
*/
|
||||
static void imx6q_setup_broadcast_timer(void *arg)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
|
||||
}
|
||||
|
||||
static struct cpuidle_driver imx6q_cpuidle_driver = {
|
||||
.name = "imx6q_cpuidle",
|
||||
.owner = THIS_MODULE,
|
||||
.en_core_tk_irqen = 1,
|
||||
.states = {
|
||||
/* WFI */
|
||||
ARM_CPUIDLE_WFI_STATE,
|
||||
/* WAIT */
|
||||
{
|
||||
.exit_latency = 50,
|
||||
.target_residency = 75,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.enter = imx6q_enter_wait,
|
||||
.name = "WAIT",
|
||||
.desc = "Clock off",
|
||||
},
|
||||
},
|
||||
.state_count = 2,
|
||||
.safe_state_index = 0,
|
||||
};
|
||||
|
||||
int __init imx6q_cpuidle_init(void)
|
||||
{
|
||||
/* Need to enable SCU standby for entering WAIT modes */
|
||||
imx_scu_standby_enable();
|
||||
|
||||
/* Set chicken bit to get a reliable WAIT mode support */
|
||||
imx6q_set_chicken_bit();
|
||||
|
||||
/* Configure the broadcast timer on each cpu */
|
||||
on_each_cpu(imx6q_setup_broadcast_timer, NULL, 1);
|
||||
|
||||
return imx_cpuidle_init(&imx6q_cpuidle_driver);
|
||||
}
|
||||
@ -14,9 +14,14 @@
|
||||
|
||||
#ifdef CONFIG_CPU_IDLE
|
||||
extern int imx_cpuidle_init(struct cpuidle_driver *drv);
|
||||
extern int imx6q_cpuidle_init(void);
|
||||
#else
|
||||
static inline int imx_cpuidle_init(struct cpuidle_driver *drv)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int imx6q_cpuidle_init(void)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,33 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include "devices/devices-common.h"
|
||||
|
||||
extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
|
||||
#define imx50_add_imx_uart(id, pdata) \
|
||||
imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
|
||||
|
||||
extern const struct imx_fec_data imx50_fec_data;
|
||||
#define imx50_add_fec(pdata) \
|
||||
imx_add_fec(&imx50_fec_data, pdata)
|
||||
|
||||
extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
|
||||
#define imx50_add_imx_i2c(id, pdata) \
|
||||
imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
|
||||
@ -1,6 +1,6 @@
|
||||
config IMX_HAVE_PLATFORM_FEC
|
||||
bool
|
||||
default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53
|
||||
default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
|
||||
|
||||
config IMX_HAVE_PLATFORM_FLEXCAN
|
||||
bool
|
||||
|
||||
@ -35,12 +35,6 @@ const struct imx_fec_data imx35_fec_data __initconst =
|
||||
imx_fec_data_entry_single(MX35, "imx27-fec");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX50
|
||||
/* i.mx50 has the i.mx25 type fec */
|
||||
const struct imx_fec_data imx50_fec_data __initconst =
|
||||
imx_fec_data_entry_single(MX50, "imx25-fec");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
/* i.mx51 has the i.mx27 type fec */
|
||||
const struct imx_fec_data imx51_fec_data __initconst =
|
||||
|
||||
@ -70,16 +70,6 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX35 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX50
|
||||
const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = {
|
||||
#define imx50_imx_i2c_data_entry(_id, _hwid) \
|
||||
imx_imx_i2c_data_entry(MX50, "imx21-i2c", _id, _hwid, SZ_4K)
|
||||
imx50_imx_i2c_data_entry(0, 1),
|
||||
imx50_imx_i2c_data_entry(1, 2),
|
||||
imx50_imx_i2c_data_entry(2, 3),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX51 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
|
||||
#define imx51_imx_i2c_data_entry(_id, _hwid) \
|
||||
|
||||
@ -94,18 +94,6 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX35 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX50
|
||||
const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = {
|
||||
#define imx50_imx_uart_data_entry(_id, _hwid) \
|
||||
imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K)
|
||||
imx50_imx_uart_data_entry(0, 1),
|
||||
imx50_imx_uart_data_entry(1, 2),
|
||||
imx50_imx_uart_data_entry(2, 3),
|
||||
imx50_imx_uart_data_entry(3, 4),
|
||||
imx50_imx_uart_data_entry(4, 5),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX50 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
|
||||
#define imx51_imx_uart_data_entry(_id, _hwid) \
|
||||
|
||||
@ -101,11 +101,16 @@ static void imx_gpc_irq_mask(struct irq_data *d)
|
||||
void __init imx_gpc_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
int i;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
|
||||
gpc_base = of_iomap(np, 0);
|
||||
WARN_ON(!gpc_base);
|
||||
|
||||
/* Initially mask all interrupts */
|
||||
for (i = 0; i < IMR_NUM; i++)
|
||||
writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
|
||||
|
||||
/* Register GPC as the secondary interrupt controller behind GIC */
|
||||
gic_arch_extn.irq_mask = imx_gpc_irq_mask;
|
||||
gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
|
||||
|
||||
@ -72,11 +72,6 @@
|
||||
* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
|
||||
* X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
|
||||
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
|
||||
* mx50:
|
||||
* TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
|
||||
* AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
|
||||
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
|
||||
* AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
|
||||
* mx51:
|
||||
* TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
|
||||
* IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
|
||||
@ -108,7 +103,6 @@
|
||||
#include "mxc.h"
|
||||
|
||||
#include "mx6q.h"
|
||||
#include "mx50.h"
|
||||
#include "mx51.h"
|
||||
#include "mx53.h"
|
||||
#include "mx3x.h"
|
||||
|
||||
@ -1,977 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_IOMUX_MX50_H__
|
||||
#define __MACH_IOMUX_MX50_H__
|
||||
|
||||
#include "iomux-v3.h"
|
||||
|
||||
#define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE)
|
||||
|
||||
#define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
|
||||
|
||||
#define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
|
||||
|
||||
#define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \
|
||||
PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define MX50_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_CSPI_SS_PAD (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_KEY_COL0__NANDF_CLE IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL)
|
||||
#define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_KEY_ROW0__NANDF_ALE IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_KEY_COL1__NANDF_CE0 IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
|
||||
#define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_KEY_ROW1__NANDF_CE1 IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL)
|
||||
#define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_KEY_COL2__NANDF_CE2 IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL)
|
||||
#define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_KEY_ROW2__NANDF_CE3 IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_KEY_COL3__NANDF_READY IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \
|
||||
PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
||||
#define MX50_PAD_KEY_COL3__SDMA_EXT0 IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
|
||||
#define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_KEY_ROW3__NANDF_DQS IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_KEY_ROW3__SDMA_EXT1 IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \
|
||||
MX50_I2C_PAD_CTRL)
|
||||
#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \
|
||||
MX50_I2C_PAD_CTRL)
|
||||
#define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_I2C1_SDA__UART2_RXD IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \
|
||||
MX50_I2C_PAD_CTRL)
|
||||
#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \
|
||||
MX50_I2C_PAD_CTRL)
|
||||
#define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_I2C2_SDA__UART2_RTS IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_I2C2_SDA__PWRSTABLE IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \
|
||||
MX50_I2C_PAD_CTRL)
|
||||
#define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_I2C3_SCL__FEC_MDC IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_I2C3_SCL__PMIC_RDY IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \
|
||||
MX50_I2C_PAD_CTRL)
|
||||
#define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_I2C3_SDA__FEC_MDIO IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL)
|
||||
#define MX50_PAD_I2C3_SDA__PWRFAIL_INT IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_I2C3_SDA__ALARM_DEB IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_I2C3_SDA__GPT_CAPIN1 IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_I2C3_SDA__USBOTG_PWR IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL)
|
||||
#define MX50_PAD_PWM1__GPT_CMPOUT1 IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PWM2__PWM2_PWMO IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_PWM2__DCDC_PWM IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_PWM2__GPT_CMPOUT2 IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_PWM2__ANY_PU_RST IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL)
|
||||
#define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL)
|
||||
#define MX50_PAD_OWIRE__SSI_EXT1_CLK IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_OWIRE__EPDC_PWRIRQ IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_OWIRE__GPT_CMPOUT3 IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPITO__EPITO IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_EPITO__SSI_EXT2_CLK IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPITO__TOG_EN IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPITO__GPT_CLKIN IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_WDOG__WDOG IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_WDOG__WDOG_RST IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_WDOG__XTAL32K IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_TXD__CSPI_RDY IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_RXD__CSPI_SS3 IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD)
|
||||
|
||||
#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_SSI_RXC__AUD3_RXC IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_RXC__UART5_RXD IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_RXC__WEIM_D7 IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_RXC__CSPI_SS1 IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x764, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x748, 0, MX50_SD_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART3_TXD__SD2_WP IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART3_TXD__WEIM_D12 IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_UART3_RXD__SD1_D5 IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART3_RXD__SD4_D1 IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART4_TXD__WEIM_D14 IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_UART4_RXD__UART4_RXD IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_UART4_RXD__UART3_RTS IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_UART4_RXD__SD1_D7 IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART4_RXD__SD4_D3 IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART4_RXD__SD1_LCTL IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_UART4_RXD__WEIM_D15 IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_CSPI_SCLK__CSPI_SCLK IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_SCLK__UART3_RTS IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6 IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_SCLK__WEIM_D8 IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_ECSPI1_MISO__UART4_RTS IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8 IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_MISO__WEIM_D10 IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
|
||||
#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_SCLK__UART5_RTS IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4 IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_SCLK__WEIM_D8 IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
|
||||
#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x0, 0, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x73c, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3 IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
|
||||
#define MX50_PAD_ECSPI2_SS0__UART5_RXD IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_SS0__NANDF_CEN7 IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_ECSPI2_SS0__WEIM_D11 IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD1_CLK__CLKO IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD1_CMD__CLKO2 IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD1_D0__PLL1_BYP IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD1_D1__PLL2_BYP IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD1_D2__PLL3_BYP IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_CLK__MSHC_SCLK IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_CMD__MSHC_BS IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D0__MSHC_D0 IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D0__KEY_COL4 IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D1__MSHC_D1 IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D1__KEY_ROW4 IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D2__MSHC_D2 IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D2__KEY_COL5 IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D3__MSHC_D3 IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D3__KEY_ROW5 IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D4__AUD4_RXFS IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D4__KEY_COL6 IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D4__WEIM_D0 IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D4__CCM_OUT0 IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D5__AUD4_RXC IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D5__KEY_ROW6 IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D5__WEIM_D1 IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D5__CCM_OUT1 IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D6__AUD4_RXD IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D6__KEY_COL7 IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D6__WEIM_D2 IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D6__CCM_OUT2 IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D7__AUD4_TXFS IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D7__KEY_ROW7 IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D7__WEIM_D3 IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_D7__CCM_STOP IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD2_WP__SD2_WP IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_WP__AUD4_TXD IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_WP__WEIM_D4 IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_WP__CCM_WAIT IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD2_CD__SD2_CD IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_CD__AUD4_TXC IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_CD__WEIM_D5 IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD2_CD__CCM_REF_EN IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE)
|
||||
|
||||
#define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE)
|
||||
#define MX50_PAD_DISP_D1__WEIM_A17 IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE)
|
||||
#define MX50_PAD_DISP_D2__WEIM_A18 IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE)
|
||||
#define MX50_PAD_DISP_D3__WEIM_A19 IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D3__FEC_COL IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE)
|
||||
#define MX50_PAD_DISP_D4__WEIM_A20 IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_DISP_D5__WEIM_A21 IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_DISP_D6__WEIM_A22 IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D6__FEC_RX_CLK IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_DISP_D7__WEIM_A23 IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
|
||||
#define MX50_PAD_DISP_WR__ELCDIF_WR IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_WR__WEIM_A24 IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_RD__ELCDIF_RD IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_CS__ELCDIF_CS IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_CS__WEIM_A27 IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_CS__WEIM_CS3 IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_BUSY__WEIM_CS3 IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_RESET__WEIM_CS3 IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_SD3_CMD__SSP_CMD IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_SD3_CLK__SSP_CLK IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_SD3_D0__SSP_D0 IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_D0__PLL1_BYP IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_SD3_D1__PLL2_BYP IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_SD3_D2__SSP_D2 IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_D2__PLL3_BYP IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_SD3_D3__SSP_D3 IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_SD3_D4__SSP_D4 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_SD3_D5__SSP_D5 IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_SD3_D6__SSP_D6 IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_SD3_D7__SSP_D7 IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_SD3_WP__SD3_WP IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_SD3_WP__SSP_CD IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_WP__SD4_LCTL IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_SD3_WP__WEIM_CS3 IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D8__NANDF_CLE IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D8__SD1_LCTL IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D8__SD4_CMD IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D8__KEY_COL4 IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D8__FEC_TX_CLK IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D9__NANDF_ALE IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D9__SD2_LCTL IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D9__SD4_CLK IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D9__KEY_ROW4 IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D9__FEC_RX_ER IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D10__NANDF_CEN0 IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D10__SD3_LCTL IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D10__SD4_D0 IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D10__KEY_COL5 IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D10__FEC_RX_DV IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D11__NANDF_CEN1 IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D11__SD4_D1 IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D11__KEY_ROW5 IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D11__FEC_RDAT1 IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D12__NANDF_CEN2 IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D12__SD1_CD IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D12__SD4_D2 IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D12__KEY_COL6 IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D12__FEC_RDAT0 IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D13__NANDF_CEN3 IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D13__SD3_CD IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D13__SD4_D3 IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D13__KEY_ROW6 IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D13__FEC_TX_EN IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D14__NANDF_RDY0 IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D14__SD1_WP IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D14__SD4_WP IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D14__KEY_COL7 IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D14__FEC_TDAT1 IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D15__NANDF_DQS IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D15__SD3_RST IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D15__SD4_CD IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D15__KEY_ROW7 IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_DISP_D15__FEC_TDAT0 IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D0__WEIM_D0 IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D0__ELCDIF_RS IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D1__WEIM_D1 IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D1__ELCDIF_CS IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D1__ELCDIF_EN IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D2__WEIM_D2 IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D2__ELCDIF_WR IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D3__WEIM_D3 IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D3__ELCDIF_RD IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D4__WEIM_D4 IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D5__WEIM_D5 IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D6__WEIM_D6 IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D7__WEIM_D7 IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D8__EPDC_D8 IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D8__WEIM_D8 IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D8__ELCDIF_D24 IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D10__WEIM_D10 IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D10__ELCDIF_D26 IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D11__EPDC_D11 IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D11__WEIM_D11 IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D11__ELCDIF_D27 IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D12__EPDC_D12 IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D12__WEIM_D12 IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D12__ELCDIF_D28 IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D13__EPDC_D13 IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D13__WEIM_D13 IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D13__ELCDIF_D29 IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D14__EPDC_D14 IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D14__WEIM_D14 IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D14__ELCDIF_D30 IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D14__AUD6_TXD IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_D15__EPDC_D15 IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D15__WEIM_D15 IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D15__ELCDIF_D31 IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_D15__AUD6_TXC IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDCLK__WEIM_D16 IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDCLK__AUD6_TXFS IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDSP__WEIM_D17 IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDSP__ELCDIF_D17 IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDSP__AUD6_RXD IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDOE__WEIM_D18 IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDOE__ELCDIF_D18 IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDOE__AUD6_RXC IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDRL__WEIM_D19 IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDRL__ELCDIF_D19 IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_GDRL__AUD6_RXFS IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCLK__WEIM_D20 IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCLK__AUD5_TXD IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDOEZ__WEIM_D21 IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDOEZ__AUD5_TXC IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDOED__WEIM_D22 IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDOED__AUD5_TXFS IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDOE__WEIM_D23 IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDOE__ELCDIF_D23 IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDOE__AUD5_RXD IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDLE__WEIM_D24 IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDLE__ELCDIF_D8 IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDLE__AUD5_RXC IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCLKN__WEIM_D25 IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9 IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDSHR__WEIM_D26 IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDSHR__AUD4_TXD IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCOM__WEIM_D27 IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11 IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCOM__AUD4_TXC IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRSTAT__WEIM_D28 IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12 IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0 IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29 IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13 IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1 IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30 IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14 IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2 IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31 IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15 IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0 IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3 IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2 IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1 IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_VCOM0__WEIM_EB3 IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_VCOM1__WEIM_CS3 IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_BDR0__ELCDIF_D7 IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_BDR1__EPDC_BDR1 IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_BDR1__ELCDIF_D6 IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCE0__ELCDIF_D5 IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCE1__ELCDIF_D4 IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3 IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCE3__ELCDIF_D2 IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCE4__ELCDIF_D1 IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EPDC_SDCE5__ELCDIF_D0 IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_DA0__WEIM_A0 IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA0__KEY_COL4 IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_DA1__WEIM_A1 IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA1__KEY_ROW4 IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_DA2__WEIM_A2 IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA2__KEY_COL5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_DA3__WEIM_A3 IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA3__KEY_ROW5 IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_DA4__WEIM_A4 IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA4__KEY_COL6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_DA5__WEIM_A5 IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA5__KEY_ROW6 IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_DA6__WEIM_A6 IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA6__KEY_COL7 IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_DA7__WEIM_A7 IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA7__KEY_ROW7 IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_DA8__WEIM_A8 IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_EIM_DA9__WEIM_A9 IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_EIM_DA10__WEIM_A10 IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_EIM_DA11__WEIM_A11 IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
|
||||
#define MX50_PAD_EIM_DA12__WEIM_A12 IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_EIM_DA12__EPDC_SDCE6 IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_DA13__WEIM_A13 IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PIN_EIM_DA13__EPDC_SDCE7 IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_DA14__WEIM_A14 IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \
|
||||
PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
||||
#define MX50_PAD_EIM_DA14__EPDC_SDCE8 IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_DA15__WEIM_A15 IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH)
|
||||
#define MX50_PAD_EIM_DA15__EPDC_SDCE9 IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_CS2__WEIM_CS2 IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_CS2__WEIM_A27 IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_CS1__WEIM_CS1 IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_CS0__WEIM_CS0 IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_EB0__WEIM_EB0 IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_EB1__WEIM_EB1 IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_WAIT__WEIM_WAIT IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_BCLK__WEIM_BCLK IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_RDY__WEIM_RDY IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_OE__WEIM_OE IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_RW__WEIM_RW IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_LBA__WEIM_LBA IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#define MX50_PAD_EIM_CRE__WEIM_CRE IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL)
|
||||
#define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL)
|
||||
|
||||
#endif /* __MACH_IOMUX_MX50_H__ */
|
||||
@ -1,47 +0,0 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "hardware.h"
|
||||
|
||||
#define IMX6Q_UART1_BASE_ADDR 0x02020000
|
||||
#define IMX6Q_UART2_BASE_ADDR 0x021e8000
|
||||
#define IMX6Q_UART3_BASE_ADDR 0x021ec000
|
||||
#define IMX6Q_UART4_BASE_ADDR 0x021f0000
|
||||
#define IMX6Q_UART5_BASE_ADDR 0x021f4000
|
||||
|
||||
/*
|
||||
* IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
|
||||
* of IMX6Q_UART##n##_BASE_ADDR.
|
||||
*/
|
||||
#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
|
||||
#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
|
||||
#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
|
||||
|
||||
static struct map_desc imx_lluart_desc = {
|
||||
#ifdef CONFIG_DEBUG_IMX6Q_UART
|
||||
.virtual = IMX_IO_P2V(IMX6Q_DEBUG_UART_BASE),
|
||||
.pfn = __phys_to_pfn(IMX6Q_DEBUG_UART_BASE),
|
||||
.length = 0x4000,
|
||||
.type = MT_DEVICE,
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init imx_lluart_map_io(void)
|
||||
{
|
||||
if (imx_lluart_desc.virtual)
|
||||
iotable_init(&imx_lluart_desc, 1);
|
||||
}
|
||||
@ -12,7 +12,6 @@
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/cpuidle.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/init.h>
|
||||
@ -27,10 +26,10 @@
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/micrel_phy.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <asm/cpuidle.h>
|
||||
#include <asm/smp_twd.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
@ -201,24 +200,20 @@ static void __init imx6q_init_machine(void)
|
||||
imx6q_1588_init();
|
||||
}
|
||||
|
||||
static struct cpuidle_driver imx6q_cpuidle_driver = {
|
||||
.name = "imx6q_cpuidle",
|
||||
.owner = THIS_MODULE,
|
||||
.en_core_tk_irqen = 1,
|
||||
.states[0] = ARM_CPUIDLE_WFI_STATE,
|
||||
.state_count = 1,
|
||||
};
|
||||
|
||||
static void __init imx6q_init_late(void)
|
||||
{
|
||||
imx_cpuidle_init(&imx6q_cpuidle_driver);
|
||||
/*
|
||||
* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
|
||||
* to run cpuidle on them.
|
||||
*/
|
||||
if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
|
||||
imx6q_cpuidle_init();
|
||||
}
|
||||
|
||||
static void __init imx6q_map_io(void)
|
||||
{
|
||||
imx_lluart_map_io();
|
||||
debug_ll_io_init();
|
||||
imx_scu_map_io();
|
||||
imx6q_clock_map_io();
|
||||
}
|
||||
|
||||
static void __init imx6q_init_irq(void)
|
||||
|
||||
@ -1,221 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx50.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx50.h"
|
||||
|
||||
#define FEC_EN IMX_GPIO_NR(6, 23)
|
||||
#define FEC_RESET_B IMX_GPIO_NR(4, 12)
|
||||
|
||||
static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
|
||||
/* SD1 */
|
||||
MX50_PAD_ECSPI2_SS0__GPIO_4_19,
|
||||
MX50_PAD_EIM_CRE__GPIO_1_27,
|
||||
MX50_PAD_SD1_CMD__SD1_CMD,
|
||||
|
||||
MX50_PAD_SD1_CLK__SD1_CLK,
|
||||
MX50_PAD_SD1_D0__SD1_D0,
|
||||
MX50_PAD_SD1_D1__SD1_D1,
|
||||
MX50_PAD_SD1_D2__SD1_D2,
|
||||
MX50_PAD_SD1_D3__SD1_D3,
|
||||
|
||||
/* SD2 */
|
||||
MX50_PAD_SD2_CD__GPIO_5_17,
|
||||
MX50_PAD_SD2_WP__GPIO_5_16,
|
||||
MX50_PAD_SD2_CMD__SD2_CMD,
|
||||
MX50_PAD_SD2_CLK__SD2_CLK,
|
||||
MX50_PAD_SD2_D0__SD2_D0,
|
||||
MX50_PAD_SD2_D1__SD2_D1,
|
||||
MX50_PAD_SD2_D2__SD2_D2,
|
||||
MX50_PAD_SD2_D3__SD2_D3,
|
||||
MX50_PAD_SD2_D4__SD2_D4,
|
||||
MX50_PAD_SD2_D5__SD2_D5,
|
||||
MX50_PAD_SD2_D6__SD2_D6,
|
||||
MX50_PAD_SD2_D7__SD2_D7,
|
||||
|
||||
/* SD3 */
|
||||
MX50_PAD_SD3_CMD__SD3_CMD,
|
||||
MX50_PAD_SD3_CLK__SD3_CLK,
|
||||
MX50_PAD_SD3_D0__SD3_D0,
|
||||
MX50_PAD_SD3_D1__SD3_D1,
|
||||
MX50_PAD_SD3_D2__SD3_D2,
|
||||
MX50_PAD_SD3_D3__SD3_D3,
|
||||
MX50_PAD_SD3_D4__SD3_D4,
|
||||
MX50_PAD_SD3_D5__SD3_D5,
|
||||
MX50_PAD_SD3_D6__SD3_D6,
|
||||
MX50_PAD_SD3_D7__SD3_D7,
|
||||
|
||||
/* PWR_INT */
|
||||
MX50_PAD_ECSPI2_MISO__GPIO_4_18,
|
||||
|
||||
/* UART pad setting */
|
||||
MX50_PAD_UART1_TXD__UART1_TXD,
|
||||
MX50_PAD_UART1_RXD__UART1_RXD,
|
||||
MX50_PAD_UART1_RTS__UART1_RTS,
|
||||
MX50_PAD_UART2_TXD__UART2_TXD,
|
||||
MX50_PAD_UART2_RXD__UART2_RXD,
|
||||
MX50_PAD_UART2_CTS__UART2_CTS,
|
||||
MX50_PAD_UART2_RTS__UART2_RTS,
|
||||
|
||||
MX50_PAD_I2C1_SCL__I2C1_SCL,
|
||||
MX50_PAD_I2C1_SDA__I2C1_SDA,
|
||||
MX50_PAD_I2C2_SCL__I2C2_SCL,
|
||||
MX50_PAD_I2C2_SDA__I2C2_SDA,
|
||||
|
||||
MX50_PAD_EPITO__USBH1_PWR,
|
||||
/* Need to comment below line if
|
||||
* one needs to debug owire.
|
||||
*/
|
||||
MX50_PAD_OWIRE__USBH1_OC,
|
||||
/* using gpio to control otg pwr */
|
||||
MX50_PAD_PWM2__GPIO_6_25,
|
||||
MX50_PAD_I2C3_SCL__USBOTG_OC,
|
||||
|
||||
MX50_PAD_SSI_RXC__FEC_MDIO,
|
||||
MX50_PAD_SSI_RXFS__FEC_MDC,
|
||||
MX50_PAD_DISP_D0__FEC_TXCLK,
|
||||
MX50_PAD_DISP_D1__FEC_RX_ER,
|
||||
MX50_PAD_DISP_D2__FEC_RX_DV,
|
||||
MX50_PAD_DISP_D3__FEC_RXD1,
|
||||
MX50_PAD_DISP_D4__FEC_RXD0,
|
||||
MX50_PAD_DISP_D5__FEC_TX_EN,
|
||||
MX50_PAD_DISP_D6__FEC_TXD1,
|
||||
MX50_PAD_DISP_D7__FEC_TXD0,
|
||||
MX50_PAD_I2C3_SDA__GPIO_6_23,
|
||||
MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
|
||||
|
||||
MX50_PAD_CSPI_SS0__CSPI_SS0,
|
||||
MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
|
||||
MX50_PAD_CSPI_MOSI__CSPI_MOSI,
|
||||
MX50_PAD_CSPI_MISO__CSPI_MISO,
|
||||
|
||||
/* SGTL500_OSC_EN */
|
||||
MX50_PAD_UART1_CTS__GPIO_6_8,
|
||||
|
||||
/* SGTL_AMP_SHDN */
|
||||
MX50_PAD_UART3_RXD__GPIO_6_15,
|
||||
|
||||
/* Keypad */
|
||||
MX50_PAD_KEY_COL0__KEY_COL0,
|
||||
MX50_PAD_KEY_ROW0__KEY_ROW0,
|
||||
MX50_PAD_KEY_COL1__KEY_COL1,
|
||||
MX50_PAD_KEY_ROW1__KEY_ROW1,
|
||||
MX50_PAD_KEY_COL2__KEY_COL2,
|
||||
MX50_PAD_KEY_ROW2__KEY_ROW2,
|
||||
MX50_PAD_KEY_COL3__KEY_COL3,
|
||||
MX50_PAD_KEY_ROW3__KEY_ROW3,
|
||||
MX50_PAD_EIM_DA0__KEY_COL4,
|
||||
MX50_PAD_EIM_DA1__KEY_ROW4,
|
||||
MX50_PAD_EIM_DA2__KEY_COL5,
|
||||
MX50_PAD_EIM_DA3__KEY_ROW5,
|
||||
MX50_PAD_EIM_DA4__KEY_COL6,
|
||||
MX50_PAD_EIM_DA5__KEY_ROW6,
|
||||
MX50_PAD_EIM_DA6__KEY_COL7,
|
||||
MX50_PAD_EIM_DA7__KEY_ROW7,
|
||||
/*EIM pads */
|
||||
MX50_PAD_EIM_DA8__GPIO_1_8,
|
||||
MX50_PAD_EIM_DA9__GPIO_1_9,
|
||||
MX50_PAD_EIM_DA10__GPIO_1_10,
|
||||
MX50_PAD_EIM_DA11__GPIO_1_11,
|
||||
MX50_PAD_EIM_DA12__GPIO_1_12,
|
||||
MX50_PAD_EIM_DA13__GPIO_1_13,
|
||||
MX50_PAD_EIM_DA14__GPIO_1_14,
|
||||
MX50_PAD_EIM_DA15__GPIO_1_15,
|
||||
MX50_PAD_EIM_CS2__GPIO_1_16,
|
||||
MX50_PAD_EIM_CS1__GPIO_1_17,
|
||||
MX50_PAD_EIM_CS0__GPIO_1_18,
|
||||
MX50_PAD_EIM_EB0__GPIO_1_19,
|
||||
MX50_PAD_EIM_EB1__GPIO_1_20,
|
||||
MX50_PAD_EIM_WAIT__GPIO_1_21,
|
||||
MX50_PAD_EIM_BCLK__GPIO_1_22,
|
||||
MX50_PAD_EIM_RDY__GPIO_1_23,
|
||||
MX50_PAD_EIM_OE__GPIO_1_24,
|
||||
};
|
||||
|
||||
/* Serial ports */
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
|
||||
static const struct fec_platform_data fec_data __initconst = {
|
||||
.phy = PHY_INTERFACE_MODE_RMII,
|
||||
};
|
||||
|
||||
static inline void mx50_rdp_fec_reset(void)
|
||||
{
|
||||
gpio_request(FEC_EN, "fec-en");
|
||||
gpio_direction_output(FEC_EN, 0);
|
||||
gpio_request(FEC_RESET_B, "fec-reset_b");
|
||||
gpio_direction_output(FEC_RESET_B, 0);
|
||||
msleep(1);
|
||||
gpio_set_value(FEC_RESET_B, 1);
|
||||
}
|
||||
|
||||
static const struct imxi2c_platform_data i2c_data __initconst = {
|
||||
.bitrate = 100000,
|
||||
};
|
||||
|
||||
/*
|
||||
* Board specific initialization.
|
||||
*/
|
||||
static void __init mx50_rdp_board_init(void)
|
||||
{
|
||||
imx50_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
|
||||
ARRAY_SIZE(mx50_rdp_pads));
|
||||
|
||||
imx50_add_imx_uart(0, &uart_pdata);
|
||||
imx50_add_imx_uart(1, &uart_pdata);
|
||||
mx50_rdp_fec_reset();
|
||||
imx50_add_fec(&fec_data);
|
||||
imx50_add_imx_i2c(0, &i2c_data);
|
||||
imx50_add_imx_i2c(1, &i2c_data);
|
||||
imx50_add_imx_i2c(2, &i2c_data);
|
||||
}
|
||||
|
||||
static void __init mx50_rdp_timer_init(void)
|
||||
{
|
||||
mx50_clocks_init(32768, 24000000, 22579200);
|
||||
}
|
||||
|
||||
MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
|
||||
.map_io = mx50_map_io,
|
||||
.init_early = imx50_init_early,
|
||||
.init_irq = mx50_init_irq,
|
||||
.handle_irq = imx50_handle_irq,
|
||||
.init_time = mx50_rdp_timer_init,
|
||||
.init_machine = mx50_rdp_board_init,
|
||||
.restart = mxc_restart,
|
||||
MACHINE_END
|
||||
@ -1,174 +0,0 @@
|
||||
/*
|
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include "3ds_debugboard.h"
|
||||
#include "common.h"
|
||||
#include "devices-imx51.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx51.h"
|
||||
|
||||
#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
|
||||
|
||||
static iomux_v3_cfg_t mx51_3ds_pads[] = {
|
||||
/* UART1 */
|
||||
MX51_PAD_UART1_RXD__UART1_RXD,
|
||||
MX51_PAD_UART1_TXD__UART1_TXD,
|
||||
MX51_PAD_UART1_RTS__UART1_RTS,
|
||||
MX51_PAD_UART1_CTS__UART1_CTS,
|
||||
|
||||
/* UART2 */
|
||||
MX51_PAD_UART2_RXD__UART2_RXD,
|
||||
MX51_PAD_UART2_TXD__UART2_TXD,
|
||||
MX51_PAD_EIM_D25__UART2_CTS,
|
||||
MX51_PAD_EIM_D26__UART2_RTS,
|
||||
|
||||
/* UART3 */
|
||||
MX51_PAD_UART3_RXD__UART3_RXD,
|
||||
MX51_PAD_UART3_TXD__UART3_TXD,
|
||||
MX51_PAD_EIM_D24__UART3_CTS,
|
||||
MX51_PAD_EIM_D27__UART3_RTS,
|
||||
|
||||
/* CPLD PARENT IRQ PIN */
|
||||
MX51_PAD_GPIO1_6__GPIO1_6,
|
||||
|
||||
/* KPP */
|
||||
MX51_PAD_KEY_ROW0__KEY_ROW0,
|
||||
MX51_PAD_KEY_ROW1__KEY_ROW1,
|
||||
MX51_PAD_KEY_ROW2__KEY_ROW2,
|
||||
MX51_PAD_KEY_ROW3__KEY_ROW3,
|
||||
MX51_PAD_KEY_COL0__KEY_COL0,
|
||||
MX51_PAD_KEY_COL1__KEY_COL1,
|
||||
MX51_PAD_KEY_COL2__KEY_COL2,
|
||||
MX51_PAD_KEY_COL3__KEY_COL3,
|
||||
MX51_PAD_KEY_COL4__KEY_COL4,
|
||||
MX51_PAD_KEY_COL5__KEY_COL5,
|
||||
|
||||
/* eCSPI2 */
|
||||
MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
|
||||
MX51_PAD_NANDF_RB3__ECSPI2_MISO,
|
||||
MX51_PAD_NANDF_D15__ECSPI2_MOSI,
|
||||
MX51_PAD_NANDF_D12__GPIO3_28,
|
||||
};
|
||||
|
||||
/* Serial ports */
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
|
||||
static int mx51_3ds_board_keymap[] = {
|
||||
KEY(0, 0, KEY_1),
|
||||
KEY(0, 1, KEY_2),
|
||||
KEY(0, 2, KEY_3),
|
||||
KEY(0, 3, KEY_F1),
|
||||
KEY(0, 4, KEY_UP),
|
||||
KEY(0, 5, KEY_F2),
|
||||
|
||||
KEY(1, 0, KEY_4),
|
||||
KEY(1, 1, KEY_5),
|
||||
KEY(1, 2, KEY_6),
|
||||
KEY(1, 3, KEY_LEFT),
|
||||
KEY(1, 4, KEY_SELECT),
|
||||
KEY(1, 5, KEY_RIGHT),
|
||||
|
||||
KEY(2, 0, KEY_7),
|
||||
KEY(2, 1, KEY_8),
|
||||
KEY(2, 2, KEY_9),
|
||||
KEY(2, 3, KEY_F3),
|
||||
KEY(2, 4, KEY_DOWN),
|
||||
KEY(2, 5, KEY_F4),
|
||||
|
||||
KEY(3, 0, KEY_0),
|
||||
KEY(3, 1, KEY_OK),
|
||||
KEY(3, 2, KEY_ESC),
|
||||
KEY(3, 3, KEY_ENTER),
|
||||
KEY(3, 4, KEY_MENU),
|
||||
KEY(3, 5, KEY_BACK)
|
||||
};
|
||||
|
||||
static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
|
||||
.keymap = mx51_3ds_board_keymap,
|
||||
.keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap),
|
||||
};
|
||||
|
||||
static int mx51_3ds_spi2_cs[] = {
|
||||
MXC_SPI_CS(0),
|
||||
MX51_3DS_ECSPI2_CS,
|
||||
};
|
||||
|
||||
static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
|
||||
.chipselect = mx51_3ds_spi2_cs,
|
||||
.num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
|
||||
};
|
||||
|
||||
static struct spi_board_info mx51_3ds_spi_nor_device[] = {
|
||||
{
|
||||
.modalias = "m25p80",
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 1,
|
||||
.chip_select = 1,
|
||||
.mode = SPI_MODE_0,
|
||||
.platform_data = NULL,},
|
||||
};
|
||||
|
||||
/*
|
||||
* Board specific initialization.
|
||||
*/
|
||||
static void __init mx51_3ds_init(void)
|
||||
{
|
||||
imx51_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
|
||||
ARRAY_SIZE(mx51_3ds_pads));
|
||||
|
||||
imx51_add_imx_uart(0, &uart_pdata);
|
||||
imx51_add_imx_uart(1, &uart_pdata);
|
||||
imx51_add_imx_uart(2, &uart_pdata);
|
||||
|
||||
imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
|
||||
spi_register_board_info(mx51_3ds_spi_nor_device,
|
||||
ARRAY_SIZE(mx51_3ds_spi_nor_device));
|
||||
|
||||
if (mxc_expio_init(MX51_CS5_BASE_ADDR, IMX_GPIO_NR(1, 6)))
|
||||
printk(KERN_WARNING "Init of the debugboard failed, all "
|
||||
"devices on the board are unusable.\n");
|
||||
|
||||
imx51_add_sdhci_esdhc_imx(0, NULL);
|
||||
imx51_add_imx_keypad(&mx51_3ds_map_data);
|
||||
imx51_add_imx2_wdt(0);
|
||||
}
|
||||
|
||||
static void __init mx51_3ds_timer_init(void)
|
||||
{
|
||||
mx51_clocks_init(32768, 24000000, 22579200, 0);
|
||||
}
|
||||
|
||||
MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
|
||||
/* Maintainer: Freescale Semiconductor, Inc. */
|
||||
.atag_offset = 0x100,
|
||||
.map_io = mx51_map_io,
|
||||
.init_early = imx51_init_early,
|
||||
.init_irq = mx51_init_irq,
|
||||
.handle_irq = imx51_handle_irq,
|
||||
.init_time = mx51_3ds_timer_init,
|
||||
.init_machine = mx51_3ds_init,
|
||||
.init_late = imx51_init_late,
|
||||
.restart = mxc_restart,
|
||||
MACHINE_END
|
||||
@ -23,16 +23,6 @@
|
||||
#include "hardware.h"
|
||||
#include "iomux-v3.h"
|
||||
|
||||
/*
|
||||
* Define the MX50 memory map.
|
||||
*/
|
||||
static struct map_desc mx50_io_desc[] __initdata = {
|
||||
imx_map_entry(MX50, TZIC, MT_DEVICE),
|
||||
imx_map_entry(MX50, SPBA0, MT_DEVICE),
|
||||
imx_map_entry(MX50, AIPS1, MT_DEVICE),
|
||||
imx_map_entry(MX50, AIPS2, MT_DEVICE),
|
||||
};
|
||||
|
||||
/*
|
||||
* Define the MX51 memory map.
|
||||
*/
|
||||
@ -59,11 +49,6 @@ static struct map_desc mx53_io_desc[] __initdata = {
|
||||
* system startup to create static physical to virtual memory mappings
|
||||
* for the IO modules.
|
||||
*/
|
||||
void __init mx50_map_io(void)
|
||||
{
|
||||
iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
|
||||
}
|
||||
|
||||
void __init mx51_map_io(void)
|
||||
{
|
||||
iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
|
||||
@ -74,13 +59,6 @@ void __init mx53_map_io(void)
|
||||
iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
|
||||
}
|
||||
|
||||
void __init imx50_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX50);
|
||||
mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
|
||||
mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
|
||||
}
|
||||
|
||||
/*
|
||||
* The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
|
||||
* the Freescale marketing division. However this did not remove the
|
||||
@ -115,11 +93,6 @@ void __init imx53_init_early(void)
|
||||
mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init mx50_init_irq(void)
|
||||
{
|
||||
tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init mx51_init_irq(void)
|
||||
{
|
||||
tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
|
||||
@ -148,31 +121,10 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = {
|
||||
.script_addrs = &imx51_sdma_script,
|
||||
};
|
||||
|
||||
static const struct resource imx50_audmux_res[] __initconst = {
|
||||
DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
|
||||
};
|
||||
|
||||
static const struct resource imx51_audmux_res[] __initconst = {
|
||||
DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
|
||||
};
|
||||
|
||||
void __init imx50_soc_init(void)
|
||||
{
|
||||
mxc_device_init();
|
||||
|
||||
/* i.mx50 has the i.mx35 type gpio */
|
||||
mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
|
||||
mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
|
||||
mxc_register_gpio("imx35-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
|
||||
mxc_register_gpio("imx35-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
|
||||
mxc_register_gpio("imx35-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
|
||||
mxc_register_gpio("imx35-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
|
||||
|
||||
/* i.mx50 has the i.mx31 type audmux */
|
||||
platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
|
||||
ARRAY_SIZE(imx50_audmux_res));
|
||||
}
|
||||
|
||||
void __init imx51_soc_init(void)
|
||||
{
|
||||
mxc_device_init();
|
||||
|
||||
@ -1,290 +0,0 @@
|
||||
#ifndef __MACH_MX50_H__
|
||||
#define __MACH_MX50_H__
|
||||
|
||||
/*
|
||||
* IROM
|
||||
*/
|
||||
#define MX50_IROM_BASE_ADDR 0x0
|
||||
#define MX50_IROM_SIZE SZ_64K
|
||||
|
||||
/* TZIC */
|
||||
#define MX50_TZIC_BASE_ADDR 0x0fffc000
|
||||
#define MX50_TZIC_SIZE SZ_16K
|
||||
|
||||
/*
|
||||
* IRAM
|
||||
*/
|
||||
#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */
|
||||
#define MX50_IRAM_PARTITIONS 16
|
||||
#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */
|
||||
|
||||
/*
|
||||
* Databahn
|
||||
*/
|
||||
#define MX50_DATABAHN_BASE_ADDR 0x14000000
|
||||
|
||||
/*
|
||||
* Graphics Memory of GPU
|
||||
*/
|
||||
#define MX50_GPU2D_BASE_ADDR 0x20000000
|
||||
|
||||
#define MX50_DEBUG_BASE_ADDR 0x40000000
|
||||
#define MX50_DEBUG_SIZE SZ_1M
|
||||
#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000)
|
||||
#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000)
|
||||
#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000)
|
||||
#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000)
|
||||
#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000)
|
||||
#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000)
|
||||
#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000)
|
||||
#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000)
|
||||
|
||||
#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000)
|
||||
#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000)
|
||||
#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000)
|
||||
#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000)
|
||||
#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000)
|
||||
#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000)
|
||||
#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000)
|
||||
#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000)
|
||||
#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000)
|
||||
#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000)
|
||||
#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000)
|
||||
#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000)
|
||||
#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000)
|
||||
#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000)
|
||||
|
||||
/*
|
||||
* SPBA global module enabled #0
|
||||
*/
|
||||
#define MX50_SPBA0_BASE_ADDR 0x50000000
|
||||
#define MX50_SPBA0_SIZE SZ_1M
|
||||
|
||||
#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000)
|
||||
#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000)
|
||||
#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000)
|
||||
#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000)
|
||||
#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000)
|
||||
#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000)
|
||||
#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000)
|
||||
|
||||
/*
|
||||
* AIPS 1
|
||||
*/
|
||||
#define MX50_AIPS1_BASE_ADDR 0x53f00000
|
||||
#define MX50_AIPS1_SIZE SZ_1M
|
||||
|
||||
#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000)
|
||||
#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000)
|
||||
#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000)
|
||||
#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000)
|
||||
#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000)
|
||||
#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000)
|
||||
#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000)
|
||||
#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000)
|
||||
#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000)
|
||||
#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000)
|
||||
#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000)
|
||||
#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000)
|
||||
#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000)
|
||||
#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000)
|
||||
#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000)
|
||||
#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000)
|
||||
#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000)
|
||||
#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000)
|
||||
#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000)
|
||||
#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000)
|
||||
#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000)
|
||||
#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000)
|
||||
|
||||
#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000)
|
||||
#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000)
|
||||
|
||||
/*
|
||||
* AIPS 2
|
||||
*/
|
||||
#define MX50_AIPS2_BASE_ADDR 0x63f00000
|
||||
#define MX50_AIPS2_SIZE SZ_1M
|
||||
|
||||
#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000)
|
||||
#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000)
|
||||
#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000)
|
||||
#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000)
|
||||
#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000)
|
||||
#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000)
|
||||
#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000)
|
||||
#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000)
|
||||
#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000)
|
||||
#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000)
|
||||
#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000)
|
||||
#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000)
|
||||
#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000)
|
||||
#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000)
|
||||
#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000)
|
||||
#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000)
|
||||
#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000)
|
||||
|
||||
/*
|
||||
* Memory regions and CS
|
||||
*/
|
||||
#define MX50_CSD0_BASE_ADDR 0x70000000
|
||||
#define MX50_CSD1_BASE_ADDR 0xb0000000
|
||||
#define MX50_CS0_BASE_ADDR 0xf0000000
|
||||
|
||||
#define MX50_IO_P2V(x) IMX_IO_P2V(x)
|
||||
#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x))
|
||||
|
||||
/*
|
||||
* defines for SPBA modules
|
||||
*/
|
||||
#define MX50_SPBA_SDHC1 0x04
|
||||
#define MX50_SPBA_SDHC2 0x08
|
||||
#define MX50_SPBA_UART3 0x0c
|
||||
#define MX50_SPBA_CSPI1 0x10
|
||||
#define MX50_SPBA_SSI2 0x14
|
||||
#define MX50_SPBA_SDHC3 0x20
|
||||
#define MX50_SPBA_SDHC4 0x24
|
||||
#define MX50_SPBA_SPDIF 0x28
|
||||
#define MX50_SPBA_ATA 0x30
|
||||
#define MX50_SPBA_SLIM 0x34
|
||||
#define MX50_SPBA_HSI2C 0x38
|
||||
#define MX50_SPBA_CTRL 0x3c
|
||||
|
||||
/*
|
||||
* DMA request assignments
|
||||
*/
|
||||
#define MX50_DMA_REQ_GPC 1
|
||||
#define MX50_DMA_REQ_ATA_UART4_RX 2
|
||||
#define MX50_DMA_REQ_ATA_UART4_TX 3
|
||||
#define MX50_DMA_REQ_CSPI1_RX 6
|
||||
#define MX50_DMA_REQ_CSPI1_TX 7
|
||||
#define MX50_DMA_REQ_CSPI2_RX 8
|
||||
#define MX50_DMA_REQ_CSPI2_TX 9
|
||||
#define MX50_DMA_REQ_I2C3_SDHC3 10
|
||||
#define MX50_DMA_REQ_SDHC4 11
|
||||
#define MX50_DMA_REQ_UART2_FIRI_RX 12
|
||||
#define MX50_DMA_REQ_UART2_FIRI_TX 13
|
||||
#define MX50_DMA_REQ_EXT0 14
|
||||
#define MX50_DMA_REQ_EXT1 15
|
||||
#define MX50_DMA_REQ_UART5_RX 16
|
||||
#define MX50_DMA_REQ_UART5_TX 17
|
||||
#define MX50_DMA_REQ_UART1_RX 18
|
||||
#define MX50_DMA_REQ_UART1_TX 19
|
||||
#define MX50_DMA_REQ_I2C1_SDHC1 20
|
||||
#define MX50_DMA_REQ_I2C2_SDHC2 21
|
||||
#define MX50_DMA_REQ_SSI2_RX2 22
|
||||
#define MX50_DMA_REQ_SSI2_TX2 23
|
||||
#define MX50_DMA_REQ_SSI2_RX1 24
|
||||
#define MX50_DMA_REQ_SSI2_TX1 25
|
||||
#define MX50_DMA_REQ_SSI1_RX2 26
|
||||
#define MX50_DMA_REQ_SSI1_TX2 27
|
||||
#define MX50_DMA_REQ_SSI1_RX1 28
|
||||
#define MX50_DMA_REQ_SSI1_TX1 29
|
||||
#define MX50_DMA_REQ_CSPI_RX 38
|
||||
#define MX50_DMA_REQ_CSPI_TX 39
|
||||
#define MX50_DMA_REQ_UART3_RX 42
|
||||
#define MX50_DMA_REQ_UART3_TX 43
|
||||
|
||||
/*
|
||||
* Interrupt numbers
|
||||
*/
|
||||
#include <asm/irq.h>
|
||||
#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1)
|
||||
#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2)
|
||||
#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3)
|
||||
#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4)
|
||||
#define MX50_INT_DAP (NR_IRQS_LEGACY + 5)
|
||||
#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6)
|
||||
#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7)
|
||||
#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13)
|
||||
#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14)
|
||||
#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18)
|
||||
#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19)
|
||||
#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20)
|
||||
#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21)
|
||||
#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
|
||||
#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
|
||||
#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27)
|
||||
#define MX50_INT_NIC (NR_IRQS_LEGACY + 28)
|
||||
#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29)
|
||||
#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30)
|
||||
#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31)
|
||||
#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32)
|
||||
#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33)
|
||||
#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34)
|
||||
#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35)
|
||||
#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36)
|
||||
#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37)
|
||||
#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38)
|
||||
#define MX50_INT_GPT (NR_IRQS_LEGACY + 39)
|
||||
#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40)
|
||||
#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
|
||||
#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
|
||||
#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
|
||||
#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
|
||||
#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
|
||||
#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
|
||||
#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
|
||||
#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
|
||||
#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
|
||||
#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
|
||||
#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
|
||||
#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
|
||||
#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
|
||||
#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
|
||||
#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
|
||||
#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
|
||||
#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58)
|
||||
#define MX50_INT_KPP (NR_IRQS_LEGACY + 60)
|
||||
#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61)
|
||||
#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62)
|
||||
#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63)
|
||||
#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64)
|
||||
#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65)
|
||||
#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66)
|
||||
#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67)
|
||||
#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68)
|
||||
#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69)
|
||||
#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71)
|
||||
#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72)
|
||||
#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73)
|
||||
#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74)
|
||||
#define MX50_INT_SRC (NR_IRQS_LEGACY + 75)
|
||||
#define MX50_INT_NM (NR_IRQS_LEGACY + 76)
|
||||
#define MX50_INT_PMU (NR_IRQS_LEGACY + 77)
|
||||
#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
|
||||
#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
|
||||
#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
|
||||
#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
|
||||
#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
|
||||
#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86)
|
||||
#define MX50_INT_FEC (NR_IRQS_LEGACY + 87)
|
||||
#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88)
|
||||
#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
|
||||
#define MX50_INT_SJC (NR_IRQS_LEGACY + 90)
|
||||
#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91)
|
||||
#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92)
|
||||
#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94)
|
||||
#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97)
|
||||
#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
|
||||
#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100)
|
||||
#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102)
|
||||
#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
|
||||
#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
|
||||
#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
|
||||
#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
|
||||
#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109)
|
||||
#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110)
|
||||
#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111)
|
||||
#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112)
|
||||
#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113)
|
||||
#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114)
|
||||
#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115)
|
||||
#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116)
|
||||
#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117)
|
||||
|
||||
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
|
||||
extern int mx50_revision(void);
|
||||
#endif
|
||||
|
||||
#endif /* ifndef __MACH_MX50_H__ */
|
||||
@ -32,7 +32,6 @@
|
||||
#define MXC_CPU_MX27 27
|
||||
#define MXC_CPU_MX31 31
|
||||
#define MXC_CPU_MX35 35
|
||||
#define MXC_CPU_MX50 50
|
||||
#define MXC_CPU_MX51 51
|
||||
#define MXC_CPU_MX53 53
|
||||
|
||||
@ -126,18 +125,6 @@ extern unsigned int __mxc_cpu_type;
|
||||
# define cpu_is_mx35() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX50
|
||||
# ifdef mxc_cpu_type
|
||||
# undef mxc_cpu_type
|
||||
# define mxc_cpu_type __mxc_cpu_type
|
||||
# else
|
||||
# define mxc_cpu_type MXC_CPU_MX50
|
||||
# endif
|
||||
# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
|
||||
#else
|
||||
# define cpu_is_mx50() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
# ifdef mxc_cpu_type
|
||||
# undef mxc_cpu_type
|
||||
|
||||
@ -20,6 +20,8 @@
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define SCU_STANDBY_ENABLE (1 << 5)
|
||||
|
||||
static void __iomem *scu_base;
|
||||
|
||||
static struct map_desc scu_io_desc __initdata = {
|
||||
@ -42,6 +44,14 @@ void __init imx_scu_map_io(void)
|
||||
scu_base = IMX_IO_ADDRESS(base);
|
||||
}
|
||||
|
||||
void imx_scu_standby_enable(void)
|
||||
{
|
||||
u32 val = readl_relaxed(scu_base);
|
||||
|
||||
val |= SCU_STANDBY_ENABLE;
|
||||
writel_relaxed(val, scu_base);
|
||||
}
|
||||
|
||||
static void __cpuinit imx_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
|
||||
/*
|
||||
* set cpu low power mode before WFI instruction. This function is called
|
||||
* mx5 because it can be used for mx50, mx51, and mx53.
|
||||
* mx5 because it can be used for mx51, and mx53.
|
||||
*/
|
||||
static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
|
||||
{
|
||||
@ -85,10 +85,7 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
|
||||
__raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
|
||||
__raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
|
||||
__raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
|
||||
|
||||
/* Enable NEON SRPG for all but MX50TO1.0. */
|
||||
if (mx50_revision() != IMX_CHIP_REVISION_1_0)
|
||||
__raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
|
||||
__raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
|
||||
|
||||
if (stop_mode) {
|
||||
empgc0 |= MXC_SRPGCR_PCR;
|
||||
|
||||
@ -152,7 +152,8 @@ static int v2_set_next_event(unsigned long evt,
|
||||
|
||||
__raw_writel(tcmp, timer_base + V2_TCMP);
|
||||
|
||||
return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
|
||||
return evt < 0x7fffffff &&
|
||||
(int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
|
||||
-ETIME : 0;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user