USB: mct_u232.h: checkpatch cleanups
Minor whitespace cleanups to make checkpatch happy. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Greg Kroah-Hartman
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@ -42,34 +42,42 @@
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#define MCT_U232_SET_REQUEST_TYPE 0x40
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#define MCT_U232_GET_REQUEST_TYPE 0xc0
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#define MCT_U232_GET_MODEM_STAT_REQUEST 2 /* Get Modem Status Register (MSR) */
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/* Get Modem Status Register (MSR) */
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#define MCT_U232_GET_MODEM_STAT_REQUEST 2
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#define MCT_U232_GET_MODEM_STAT_SIZE 1
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#define MCT_U232_GET_LINE_CTRL_REQUEST 6 /* Get Line Control Register (LCR) */
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#define MCT_U232_GET_LINE_CTRL_SIZE 1 /* ... not used by this driver */
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/* Get Line Control Register (LCR) */
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/* ... not used by this driver */
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#define MCT_U232_GET_LINE_CTRL_REQUEST 6
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#define MCT_U232_GET_LINE_CTRL_SIZE 1
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#define MCT_U232_SET_BAUD_RATE_REQUEST 5 /* Set Baud Rate Divisor */
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/* Set Baud Rate Divisor */
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#define MCT_U232_SET_BAUD_RATE_REQUEST 5
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#define MCT_U232_SET_BAUD_RATE_SIZE 4
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#define MCT_U232_SET_LINE_CTRL_REQUEST 7 /* Set Line Control Register (LCR) */
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/* Set Line Control Register (LCR) */
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#define MCT_U232_SET_LINE_CTRL_REQUEST 7
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#define MCT_U232_SET_LINE_CTRL_SIZE 1
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#define MCT_U232_SET_MODEM_CTRL_REQUEST 10 /* Set Modem Control Register (MCR) */
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/* Set Modem Control Register (MCR) */
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#define MCT_U232_SET_MODEM_CTRL_REQUEST 10
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#define MCT_U232_SET_MODEM_CTRL_SIZE 1
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/* This USB device request code is not well understood. It is transmitted by
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the MCT-supplied Windows driver whenever the baud rate changes.
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*/
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/*
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* This USB device request code is not well understood. It is transmitted by
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* the MCT-supplied Windows driver whenever the baud rate changes.
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*/
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#define MCT_U232_SET_UNKNOWN1_REQUEST 11 /* Unknown functionality */
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#define MCT_U232_SET_UNKNOWN1_SIZE 1
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/* This USB device request code appears to control whether CTS is required
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during transmission.
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Sending a zero byte allows data transmission to a device which is not
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asserting CTS. Sending a '1' byte will cause transmission to be deferred
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until the device asserts CTS.
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*/
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/*
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* This USB device request code appears to control whether CTS is required
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* during transmission.
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*
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* Sending a zero byte allows data transmission to a device which is not
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* asserting CTS. Sending a '1' byte will cause transmission to be deferred
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* until the device asserts CTS.
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*/
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#define MCT_U232_SET_CTS_REQUEST 12
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#define MCT_U232_SET_CTS_SIZE 1
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@ -81,7 +89,8 @@
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* and "Intel solution". They are the regular MCT and "Sitecom" for us.
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* This is pointless to document in the header, see the code for the bits.
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*/
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static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value, speed_t *result);
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static int mct_u232_calculate_baud_rate(struct usb_serial *serial,
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speed_t value, speed_t *result);
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/*
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* Line Control Register (LCR)
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@ -290,31 +299,34 @@ static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value
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* --------------------------
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*
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* Bit 7 Error in Receiver FIFO. On the 8250/16450 UART, this bit is zero.
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* This bit is set to "1" when any of the bytes in the FIFO have one or
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* more of the following error conditions: PE, FE, or BI.
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* This bit is set to "1" when any of the bytes in the FIFO have one
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* or more of the following error conditions: PE, FE, or BI.
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* Bit 6 Transmitter Empty (TEMT). When set to "1", there are no words
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* remaining in the transmit FIFO or the transmit shift register. The
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* transmitter is completely idle.
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* Bit 5 Transmitter Holding Register Empty (THRE). When set to "1", the FIFO
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* (or holding register) now has room for at least one additional word
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* to transmit. The transmitter may still be transmitting when this bit
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* is set to "1".
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* Bit 5 Transmitter Holding Register Empty (THRE). When set to "1", the
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* FIFO (or holding register) now has room for at least one additional
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* word to transmit. The transmitter may still be transmitting when
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* this bit is set to "1".
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* Bit 4 Break Interrupt (BI). The receiver has detected a Break signal.
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* Bit 3 Framing Error (FE). A Start Bit was detected but the Stop Bit did not
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* appear at the expected time. The received word is probably garbled.
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* Bit 2 Parity Error (PE). The parity bit was incorrect for the word received.
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* Bit 1 Overrun Error (OE). A new word was received and there was no room in
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* the receive buffer. The newly-arrived word in the shift register is
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* discarded. On 8250/16450 UARTs, the word in the holding register is
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* discarded and the newly- arrived word is put in the holding register.
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* Bit 3 Framing Error (FE). A Start Bit was detected but the Stop Bit did
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* not appear at the expected time. The received word is probably
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* garbled.
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* Bit 2 Parity Error (PE). The parity bit was incorrect for the word
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* received.
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* Bit 1 Overrun Error (OE). A new word was received and there was no room
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* in the receive buffer. The newly-arrived word in the shift register
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* is discarded. On 8250/16450 UARTs, the word in the holding register
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* is discarded and the newly- arrived word is put in the holding
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* register.
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* Bit 0 Data Ready (DR). One or more words are in the receive FIFO that the
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* host may read. A word must be completely received and moved from the
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* shift register into the FIFO (or holding register for 8250/16450
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* designs) before this bit is set.
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* host may read. A word must be completely received and moved from
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* the shift register into the FIFO (or holding register for
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* 8250/16450 designs) before this bit is set.
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*
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* SniffUSB observations: the LSR is returned as second byte on the interrupt-in
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* endpoint 0x83 to signal error conditions. Such errors have been seen with
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* minicom/zmodem transfers (CRC errors).
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* SniffUSB observations: the LSR is returned as second byte on the
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* interrupt-in endpoint 0x83 to signal error conditions. Such errors have
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* been seen with minicom/zmodem transfers (CRC errors).
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*
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*
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* Unknown #1
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