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This updates the Integrator DTS files with the device

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tree nodes required by the DRM driver.
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Merge tag 'integrator-dts-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into arm/dt

This updates the Integrator DTS files with the device
tree nodes required by the DRM driver.

* tag 'integrator-dts-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
  ARM: dts: Augment panel setting for Integrator/CP

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-01-30 17:52:26 +01:00
commit 4165ef5d00
1 changed files with 57 additions and 32 deletions
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89
arch/arm/boot/dts/integratorcp.dts
View File

@ -192,6 +192,43 @@
interrupts = <27>; interrupts = <27>;
}; };
bridge {
compatible = "ti,ths8134a", "ti,ths8134";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
vga_bridge_in: endpoint {
remote-endpoint = <&clcd_pads_vga_dac>;
};
};
port@1 {
reg = <1>;
vga_bridge_out: endpoint {
remote-endpoint = <&vga_con_in>;
};
};
};
};
vga {
compatible = "vga-connector";
port {
vga_con_in: endpoint {
remote-endpoint = <&vga_bridge_out>;
};
};
};
fpga { fpga {
/* /*
* These PrimeCells are at the same location and using * These PrimeCells are at the same location and using
@ -254,39 +291,27 @@
interrupts = <22>; interrupts = <22>;
clocks = <&auxosc>, <&pclk>; clocks = <&auxosc>, <&pclk>;
clock-names = "clcdclk", "apb_pclk"; clock-names = "clcdclk", "apb_pclk";
/* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
max-memory-bandwidth = <40000000>;
port { /*
/* * This port is routed through a PLD (Programmable
* The VGA connected is implemented with a * Logic Device) that routes the output from the CLCD
* THS8134A triple DAC that can be run in 24bit * (after transformations) to the VGA DAC and also an
* or 16bit RGB mode. * external panel connector. The PLD is essential for
*/ * supporting RGB565/BGR565.
clcd_pads: endpoint { *
remote-endpoint = <&clcd_panel>; * The signals from the port thus reaches two endpoints.
arm,pl11x,tft-r0g0b0-pads = <1 7 13>; * The PLD is managed through a few special bits in the
}; * FPGA "sysreg".
}; *
* This arrangement can be clearly seen in
panel { * ARM DUI 0225D, page 3-41, figure 3-19.
compatible = "panel-dpi"; */
port@0 {
port { clcd_pads_vga_dac: endpoint {
clcd_panel: endpoint { remote-endpoint = <&vga_bridge_in>;
remote-endpoint = <&clcd_pads>; arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
/* Standard 640x480 VGA timings */
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
hback-porch = <48>;
hfront-porch = <16>;
hsync-len = <96>;
vactive = <480>;
vback-porch = <33>;
vfront-porch = <10>;
vsync-len = <2>;
}; };
}; };
}; };