forked from Minki/linux
Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
This commit is contained in:
Linus Torvalds
commit
401221501a
@ -164,6 +164,19 @@ config IA64_PAGE_SIZE_64KB
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endchoice
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choice
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prompt "Page Table Levels"
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default PGTABLE_3
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config PGTABLE_3
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bool "3 Levels"
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config PGTABLE_4
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depends on !IA64_PAGE_SIZE_64KB
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bool "4 Levels"
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endchoice
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source kernel/Kconfig.hz
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config IA64_BRL_EMU
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@ -80,6 +80,8 @@ CONFIG_MCKINLEY=y
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# CONFIG_IA64_PAGE_SIZE_8KB is not set
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CONFIG_IA64_PAGE_SIZE_16KB=y
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# CONFIG_IA64_PAGE_SIZE_64KB is not set
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# CONFIG_PGTABLE_3 is not set
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CONFIG_PGTABLE_4=y
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# CONFIG_HZ_100 is not set
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CONFIG_HZ_250=y
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# CONFIG_HZ_1000 is not set
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@ -82,6 +82,8 @@ CONFIG_MCKINLEY=y
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# CONFIG_IA64_PAGE_SIZE_8KB is not set
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CONFIG_IA64_PAGE_SIZE_16KB=y
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# CONFIG_IA64_PAGE_SIZE_64KB is not set
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CONFIG_PGTABLE_3=y
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# CONFIG_PGTABLE_4 is not set
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# CONFIG_HZ_100 is not set
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CONFIG_HZ_250=y
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# CONFIG_HZ_1000 is not set
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@ -114,7 +114,7 @@ ENTRY(vhpt_miss)
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shl r21=r16,3 // shift bit 60 into sign bit
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shr.u r17=r16,61 // get the region number into r17
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;;
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shr r22=r21,3
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shr.u r22=r21,3
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#ifdef CONFIG_HUGETLB_PAGE
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extr.u r26=r25,2,6
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;;
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@ -140,20 +140,34 @@ ENTRY(vhpt_miss)
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(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
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(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
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cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
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shr.u r18=r22,PMD_SHIFT // shift L2 index into position
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#ifdef CONFIG_PGTABLE_4
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shr.u r28=r22,PUD_SHIFT // shift L2 index into position
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#else
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shr.u r18=r22,PMD_SHIFT // shift L3 index into position
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#endif
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;;
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ld8 r17=[r17] // fetch the L1 entry (may be 0)
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;;
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(p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
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dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
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#ifdef CONFIG_PGTABLE_4
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dep r28=r28,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
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;;
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(p7) ld8 r20=[r17] // fetch the L2 entry (may be 0)
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shr.u r19=r22,PAGE_SHIFT // shift L3 index into position
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shr.u r18=r22,PMD_SHIFT // shift L3 index into position
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(p7) ld8 r29=[r28] // fetch the L2 entry (may be 0)
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;;
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(p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L2 entry NULL?
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dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
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(p7) cmp.eq.or.andcm p6,p7=r29,r0 // was L2 entry NULL?
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dep r17=r18,r29,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
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#else
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dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
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#endif
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;;
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(p7) ld8 r18=[r21] // read the L3 PTE
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(p7) ld8 r20=[r17] // fetch the L3 entry (may be 0)
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shr.u r19=r22,PAGE_SHIFT // shift L4 index into position
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;;
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(p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L3 entry NULL?
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dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L4 page table entry
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;;
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(p7) ld8 r18=[r21] // read the L4 PTE
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mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss
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;;
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(p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
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@ -192,14 +206,21 @@ ENTRY(vhpt_miss)
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* between reading the pagetable and the "itc". If so, flush the entry we
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* inserted and retry.
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*/
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ld8 r25=[r21] // read L3 PTE again
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ld8 r26=[r17] // read L2 entry again
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ld8 r25=[r21] // read L4 entry again
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ld8 r26=[r17] // read L3 PTE again
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#ifdef CONFIG_PGTABLE_4
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ld8 r18=[r28] // read L2 entry again
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#endif
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cmp.ne p6,p7=r0,r0
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;;
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cmp.ne p6,p7=r26,r20 // did L2 entry change
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cmp.ne.or.andcm p6,p7=r26,r20 // did L3 entry change
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#ifdef CONFIG_PGTABLE_4
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cmp.ne.or.andcm p6,p7=r29,r18 // did L4 PTE change
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#endif
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mov r27=PAGE_SHIFT<<2
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;;
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(p6) ptc.l r22,r27 // purge PTE page translation
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(p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L3 PTE change
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(p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L4 PTE change
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;;
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(p6) ptc.l r16,r27 // purge translation
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#endif
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@ -432,18 +453,30 @@ ENTRY(nested_dtlb_miss)
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(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
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(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
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cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
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shr.u r18=r22,PMD_SHIFT // shift L2 index into position
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#ifdef CONFIG_PGTABLE_4
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shr.u r18=r22,PUD_SHIFT // shift L2 index into position
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#else
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shr.u r18=r22,PMD_SHIFT // shift L3 index into position
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#endif
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;;
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ld8 r17=[r17] // fetch the L1 entry (may be 0)
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;;
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(p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
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dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
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;;
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#ifdef CONFIG_PGTABLE_4
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(p7) ld8 r17=[r17] // fetch the L2 entry (may be 0)
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shr.u r19=r22,PAGE_SHIFT // shift L3 index into position
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shr.u r18=r22,PMD_SHIFT // shift L3 index into position
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;;
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(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL?
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dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
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dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
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;;
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#endif
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(p7) ld8 r17=[r17] // fetch the L3 entry (may be 0)
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shr.u r19=r22,PAGE_SHIFT // shift L4 index into position
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;;
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(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L3 entry NULL?
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dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L4 page table entry
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(p6) br.cond.spnt page_fault
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mov b0=r30
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br.sptk.many b0 // return to continuation point
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@ -30,6 +30,7 @@
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#include <linux/root_dev.h>
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#include <linux/nodemask.h>
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#include <linux/pm.h>
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#include <linux/efi.h>
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#include <asm/io.h>
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#include <asm/sal.h>
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@ -242,6 +243,135 @@ static void __init sn_check_for_wars(void)
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}
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}
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/*
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* Scan the EFI PCDP table (if it exists) for an acceptable VGA console
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* output device. If one exists, pick it and set sn_legacy_{io,mem} to
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* reflect the bus offsets needed to address it.
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*
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* Since pcdp support in SN is not supported in the 2.4 kernel (or at least
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* the one lbs is based on) just declare the needed structs here.
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*
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* Reference spec http://www.dig64.org/specifications/DIG64_PCDPv20.pdf
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*
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* Returns 0 if no acceptable vga is found, !0 otherwise.
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*
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* Note: This stuff is duped here because Altix requires the PCDP to
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* locate a usable VGA device due to lack of proper ACPI support. Structures
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* could be used from drivers/firmware/pcdp.h, but it was decided that moving
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* this file to a more public location just for Altix use was undesireable.
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*/
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struct hcdp_uart_desc {
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u8 pad[45];
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};
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struct pcdp {
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u8 signature[4]; /* should be 'HCDP' */
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u32 length;
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u8 rev; /* should be >=3 for pcdp, <3 for hcdp */
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u8 sum;
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u8 oem_id[6];
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u64 oem_tableid;
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u32 oem_rev;
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u32 creator_id;
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u32 creator_rev;
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u32 num_type0;
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struct hcdp_uart_desc uart[0]; /* num_type0 of these */
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/* pcdp descriptors follow */
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} __attribute__((packed));
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struct pcdp_device_desc {
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u8 type;
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u8 primary;
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u16 length;
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u16 index;
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/* interconnect specific structure follows */
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/* device specific structure follows that */
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} __attribute__((packed));
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struct pcdp_interface_pci {
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u8 type; /* 1 == pci */
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u8 reserved;
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u16 length;
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u8 segment;
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u8 bus;
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u8 dev;
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u8 fun;
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u16 devid;
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u16 vendid;
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u32 acpi_interrupt;
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u64 mmio_tra;
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u64 ioport_tra;
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u8 flags;
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u8 translation;
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} __attribute__((packed));
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struct pcdp_vga_device {
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u8 num_eas_desc;
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/* ACPI Extended Address Space Desc follows */
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} __attribute__((packed));
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/* from pcdp_device_desc.primary */
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#define PCDP_PRIMARY_CONSOLE 0x01
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/* from pcdp_device_desc.type */
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#define PCDP_CONSOLE_INOUT 0x0
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#define PCDP_CONSOLE_DEBUG 0x1
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#define PCDP_CONSOLE_OUT 0x2
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#define PCDP_CONSOLE_IN 0x3
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#define PCDP_CONSOLE_TYPE_VGA 0x8
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#define PCDP_CONSOLE_VGA (PCDP_CONSOLE_TYPE_VGA | PCDP_CONSOLE_OUT)
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/* from pcdp_interface_pci.type */
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#define PCDP_IF_PCI 1
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/* from pcdp_interface_pci.translation */
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#define PCDP_PCI_TRANS_IOPORT 0x02
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#define PCDP_PCI_TRANS_MMIO 0x01
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static void
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sn_scan_pcdp(void)
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{
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u8 *bp;
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struct pcdp *pcdp;
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struct pcdp_device_desc device;
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struct pcdp_interface_pci if_pci;
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extern struct efi efi;
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pcdp = efi.hcdp;
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if (! pcdp)
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return; /* no hcdp/pcdp table */
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if (pcdp->rev < 3)
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return; /* only support PCDP (rev >= 3) */
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for (bp = (u8 *)&pcdp->uart[pcdp->num_type0];
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bp < (u8 *)pcdp + pcdp->length;
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bp += device.length) {
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memcpy(&device, bp, sizeof(device));
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if (! (device.primary & PCDP_PRIMARY_CONSOLE))
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continue; /* not primary console */
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if (device.type != PCDP_CONSOLE_VGA)
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continue; /* not VGA descriptor */
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memcpy(&if_pci, bp+sizeof(device), sizeof(if_pci));
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if (if_pci.type != PCDP_IF_PCI)
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continue; /* not PCI interconnect */
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if (if_pci.translation & PCDP_PCI_TRANS_IOPORT)
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vga_console_iobase =
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if_pci.ioport_tra | __IA64_UNCACHED_OFFSET;
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if (if_pci.translation & PCDP_PCI_TRANS_MMIO)
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vga_console_membase =
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if_pci.mmio_tra | __IA64_UNCACHED_OFFSET;
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break; /* once we find the primary, we're done */
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}
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}
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/**
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* sn_setup - SN platform setup routine
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* @cmdline_p: kernel command line
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@ -263,16 +393,35 @@ void __init sn_setup(char **cmdline_p)
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#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
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/*
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* If there was a primary vga adapter identified through the
|
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* EFI PCDP table, make it the preferred console. Otherwise
|
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* zero out conswitchp.
|
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* Handle SN vga console.
|
||||
*
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||||
* SN systems do not have enough ACPI table information
|
||||
* being passed from prom to identify VGA adapters and the legacy
|
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* addresses to access them. Until that is done, SN systems rely
|
||||
* on the PCDP table to identify the primary VGA console if one
|
||||
* exists.
|
||||
*
|
||||
* However, kernel PCDP support is optional, and even if it is built
|
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* into the kernel, it will not be used if the boot cmdline contains
|
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* console= directives.
|
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*
|
||||
* So, to work around this mess, we duplicate some of the PCDP code
|
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* here so that the primary VGA console (as defined by PCDP) will
|
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* work on SN systems even if a different console (e.g. serial) is
|
||||
* selected on the boot line (or CONFIG_EFI_PCDP is off).
|
||||
*/
|
||||
|
||||
if (! vga_console_membase)
|
||||
sn_scan_pcdp();
|
||||
|
||||
if (vga_console_membase) {
|
||||
/* usable vga ... make tty0 the preferred default console */
|
||||
add_preferred_console("tty", 0, NULL);
|
||||
if (!strstr(*cmdline_p, "console="))
|
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add_preferred_console("tty", 0, NULL);
|
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} else {
|
||||
printk(KERN_DEBUG "SGI: Disabling VGA console\n");
|
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if (!strstr(*cmdline_p, "console="))
|
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add_preferred_console("ttySG", 0, NULL);
|
||||
#ifdef CONFIG_DUMMY_CONSOLE
|
||||
conswitchp = &dummy_con;
|
||||
#else
|
||||
|
||||
@ -47,8 +47,6 @@
|
||||
#define PERCPU_PAGE_SHIFT 16 /* log2() of max. size of per-CPU area */
|
||||
#define PERCPU_PAGE_SIZE (__IA64_UL_CONST(1) << PERCPU_PAGE_SHIFT)
|
||||
|
||||
#define RGN_MAP_LIMIT ((1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE) /* per region addr limit */
|
||||
|
||||
|
||||
#ifdef CONFIG_HUGETLB_PAGE
|
||||
# define HPAGE_REGION_BASE RGN_BASE(RGN_HPAGE)
|
||||
@ -175,11 +173,17 @@ get_order (unsigned long size)
|
||||
*/
|
||||
typedef struct { unsigned long pte; } pte_t;
|
||||
typedef struct { unsigned long pmd; } pmd_t;
|
||||
#ifdef CONFIG_PGTABLE_4
|
||||
typedef struct { unsigned long pud; } pud_t;
|
||||
#endif
|
||||
typedef struct { unsigned long pgd; } pgd_t;
|
||||
typedef struct { unsigned long pgprot; } pgprot_t;
|
||||
|
||||
# define pte_val(x) ((x).pte)
|
||||
# define pmd_val(x) ((x).pmd)
|
||||
#ifdef CONFIG_PGTABLE_4
|
||||
# define pud_val(x) ((x).pud)
|
||||
#endif
|
||||
# define pgd_val(x) ((x).pgd)
|
||||
# define pgprot_val(x) ((x).pgprot)
|
||||
|
||||
|
||||
@ -86,6 +86,25 @@ static inline void pgd_free(pgd_t * pgd)
|
||||
pgtable_quicklist_free(pgd);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PGTABLE_4
|
||||
static inline void
|
||||
pgd_populate(struct mm_struct *mm, pgd_t * pgd_entry, pud_t * pud)
|
||||
{
|
||||
pgd_val(*pgd_entry) = __pa(pud);
|
||||
}
|
||||
|
||||
static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
|
||||
{
|
||||
return pgtable_quicklist_alloc();
|
||||
}
|
||||
|
||||
static inline void pud_free(pud_t * pud)
|
||||
{
|
||||
pgtable_quicklist_free(pud);
|
||||
}
|
||||
#define __pud_free_tlb(tlb, pud) pud_free(pud)
|
||||
#endif /* CONFIG_PGTABLE_4 */
|
||||
|
||||
static inline void
|
||||
pud_populate(struct mm_struct *mm, pud_t * pud_entry, pmd_t * pmd)
|
||||
{
|
||||
|
||||
@ -83,34 +83,57 @@
|
||||
#define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
|
||||
#define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED
|
||||
|
||||
/*
|
||||
* How many pointers will a page table level hold expressed in shift
|
||||
*/
|
||||
#define PTRS_PER_PTD_SHIFT (PAGE_SHIFT-3)
|
||||
|
||||
/*
|
||||
* Definitions for fourth level:
|
||||
*/
|
||||
#define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT))
|
||||
|
||||
/*
|
||||
* Definitions for third level:
|
||||
*
|
||||
* PMD_SHIFT determines the size of the area a third-level page table
|
||||
* can map.
|
||||
*/
|
||||
#define PMD_SHIFT (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT))
|
||||
#define PMD_SIZE (1UL << PMD_SHIFT)
|
||||
#define PMD_MASK (~(PMD_SIZE-1))
|
||||
#define PTRS_PER_PMD (1UL << (PTRS_PER_PTD_SHIFT))
|
||||
|
||||
#ifdef CONFIG_PGTABLE_4
|
||||
/*
|
||||
* Definitions for second level:
|
||||
*
|
||||
* PUD_SHIFT determines the size of the area a second-level page table
|
||||
* can map.
|
||||
*/
|
||||
#define PUD_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
|
||||
#define PUD_SIZE (1UL << PUD_SHIFT)
|
||||
#define PUD_MASK (~(PUD_SIZE-1))
|
||||
#define PTRS_PER_PUD (1UL << (PTRS_PER_PTD_SHIFT))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Definitions for first level:
|
||||
*
|
||||
* PGDIR_SHIFT determines what a first-level page table entry can map.
|
||||
*/
|
||||
#define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
|
||||
#ifdef CONFIG_PGTABLE_4
|
||||
#define PGDIR_SHIFT (PUD_SHIFT + (PTRS_PER_PTD_SHIFT))
|
||||
#else
|
||||
#define PGDIR_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
|
||||
#endif
|
||||
#define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
|
||||
#define PGDIR_MASK (~(PGDIR_SIZE-1))
|
||||
#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3))
|
||||
#define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT
|
||||
#define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT)
|
||||
#define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */
|
||||
#define FIRST_USER_ADDRESS 0
|
||||
|
||||
/*
|
||||
* Definitions for second level:
|
||||
*
|
||||
* PMD_SHIFT determines the size of the area a second-level page table
|
||||
* can map.
|
||||
*/
|
||||
#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
|
||||
#define PMD_SIZE (1UL << PMD_SHIFT)
|
||||
#define PMD_MASK (~(PMD_SIZE-1))
|
||||
#define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3))
|
||||
|
||||
/*
|
||||
* Definitions for third level:
|
||||
*/
|
||||
#define PTRS_PER_PTE (__IA64_UL(1) << (PAGE_SHIFT-3))
|
||||
|
||||
/*
|
||||
* All the normal masks have the "page accessed" bits on, as any time
|
||||
* they are used, the page is accessed. They are cleared only by the
|
||||
@ -161,6 +184,9 @@
|
||||
#define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
|
||||
|
||||
#define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
|
||||
#ifdef CONFIG_PGTABLE_4
|
||||
#define pud_ERROR(e) printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
|
||||
#endif
|
||||
#define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
|
||||
#define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
|
||||
|
||||
@ -218,6 +244,9 @@ ia64_phys_addr_valid (unsigned long addr)
|
||||
#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE))
|
||||
#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE))
|
||||
|
||||
#define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3)
|
||||
#define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE) /* per region addr limit */
|
||||
|
||||
/*
|
||||
* Conversion functions: convert page frame number (pfn) and a protection value to a page
|
||||
* table entry (pte).
|
||||
@ -254,9 +283,16 @@ ia64_phys_addr_valid (unsigned long addr)
|
||||
#define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud)))
|
||||
#define pud_present(pud) (pud_val(pud) != 0UL)
|
||||
#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
|
||||
|
||||
#define pud_page(pud) ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
|
||||
|
||||
#ifdef CONFIG_PGTABLE_4
|
||||
#define pgd_none(pgd) (!pgd_val(pgd))
|
||||
#define pgd_bad(pgd) (!ia64_phys_addr_valid(pgd_val(pgd)))
|
||||
#define pgd_present(pgd) (pgd_val(pgd) != 0UL)
|
||||
#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL)
|
||||
#define pgd_page(pgd) ((unsigned long) __va(pgd_val(pgd) & _PFN_MASK))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The following have defined behavior only work if pte_present() is true.
|
||||
*/
|
||||
@ -324,7 +360,13 @@ pgd_offset (struct mm_struct *mm, unsigned long address)
|
||||
here. */
|
||||
#define pgd_offset_gate(mm, addr) pgd_offset_k(addr)
|
||||
|
||||
#ifdef CONFIG_PGTABLE_4
|
||||
/* Find an entry in the second-level page table.. */
|
||||
#define pud_offset(dir,addr) \
|
||||
((pud_t *) pgd_page(*(dir)) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
|
||||
#endif
|
||||
|
||||
/* Find an entry in the third-level page table.. */
|
||||
#define pmd_offset(dir,addr) \
|
||||
((pmd_t *) pud_page(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
|
||||
|
||||
@ -557,7 +599,9 @@ do { \
|
||||
#define __HAVE_ARCH_PGD_OFFSET_GATE
|
||||
#define __HAVE_ARCH_LAZY_MMU_PROT_UPDATE
|
||||
|
||||
#ifndef CONFIG_PGTABLE_4
|
||||
#include <asm-generic/pgtable-nopud.h>
|
||||
#endif
|
||||
#include <asm-generic/pgtable.h>
|
||||
|
||||
#endif /* _ASM_IA64_PGTABLE_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user