Merge remote-tracking branches 'asoc/fix/davinci', 'asoc/fix/es8328', 'asoc/fix/fsl-sai', 'asoc/fix/rockchip', 'asoc/fix/sgtl5000' and 'asoc/fix/wm8974' into asoc-linus
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commit
3dd5fc0eeb
@ -85,7 +85,15 @@ static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
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static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
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static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
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static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
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static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
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static const int deemph_settings[] = { 0, 32000, 44100, 48000 };
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static const struct {
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int rate;
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unsigned int val;
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} deemph_settings[] = {
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{ 0, ES8328_DACCONTROL6_DEEMPH_OFF },
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{ 32000, ES8328_DACCONTROL6_DEEMPH_32k },
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{ 44100, ES8328_DACCONTROL6_DEEMPH_44_1k },
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{ 48000, ES8328_DACCONTROL6_DEEMPH_48k },
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};
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static int es8328_set_deemph(struct snd_soc_codec *codec)
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static int es8328_set_deemph(struct snd_soc_codec *codec)
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{
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{
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@ -97,21 +105,22 @@ static int es8328_set_deemph(struct snd_soc_codec *codec)
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* rate.
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* rate.
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*/
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*/
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if (es8328->deemph) {
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if (es8328->deemph) {
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best = 1;
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best = 0;
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for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
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for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
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if (abs(deemph_settings[i] - es8328->playback_fs) <
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if (abs(deemph_settings[i].rate - es8328->playback_fs) <
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abs(deemph_settings[best] - es8328->playback_fs))
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abs(deemph_settings[best].rate - es8328->playback_fs))
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best = i;
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best = i;
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}
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}
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val = best << 1;
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val = deemph_settings[best].val;
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} else {
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} else {
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val = 0;
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val = ES8328_DACCONTROL6_DEEMPH_OFF;
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}
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}
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dev_dbg(codec->dev, "Set deemphasis %d\n", val);
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dev_dbg(codec->dev, "Set deemphasis %d\n", val);
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return snd_soc_update_bits(codec, ES8328_DACCONTROL6, 0x6, val);
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return snd_soc_update_bits(codec, ES8328_DACCONTROL6,
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ES8328_DACCONTROL6_DEEMPH_MASK, val);
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}
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}
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static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
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static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
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@ -153,6 +153,7 @@ int es8328_probe(struct device *dev, struct regmap *regmap);
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#define ES8328_DACCONTROL6_CLICKFREE (1 << 3)
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#define ES8328_DACCONTROL6_CLICKFREE (1 << 3)
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#define ES8328_DACCONTROL6_DAC_INVR (1 << 4)
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#define ES8328_DACCONTROL6_DAC_INVR (1 << 4)
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#define ES8328_DACCONTROL6_DAC_INVL (1 << 5)
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#define ES8328_DACCONTROL6_DAC_INVL (1 << 5)
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#define ES8328_DACCONTROL6_DEEMPH_MASK (3 << 6)
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#define ES8328_DACCONTROL6_DEEMPH_OFF (0 << 6)
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#define ES8328_DACCONTROL6_DEEMPH_OFF (0 << 6)
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#define ES8328_DACCONTROL6_DEEMPH_32k (1 << 6)
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#define ES8328_DACCONTROL6_DEEMPH_32k (1 << 6)
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#define ES8328_DACCONTROL6_DEEMPH_44_1k (2 << 6)
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#define ES8328_DACCONTROL6_DEEMPH_44_1k (2 << 6)
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@ -189,6 +189,7 @@ static int power_vag_event(struct snd_soc_dapm_widget *w,
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case SND_SOC_DAPM_POST_PMU:
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case SND_SOC_DAPM_POST_PMU:
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snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
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snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
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SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
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SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
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msleep(400);
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break;
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break;
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case SND_SOC_DAPM_PRE_PMD:
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case SND_SOC_DAPM_PRE_PMD:
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@ -574,6 +574,7 @@ static const struct regmap_config wm8974_regmap = {
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.max_register = WM8974_MONOMIX,
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.max_register = WM8974_MONOMIX,
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.reg_defaults = wm8974_reg_defaults,
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.reg_defaults = wm8974_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(wm8974_reg_defaults),
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.num_reg_defaults = ARRAY_SIZE(wm8974_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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};
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};
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static int wm8974_probe(struct snd_soc_codec *codec)
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static int wm8974_probe(struct snd_soc_codec *codec)
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@ -223,8 +223,8 @@ static void mcasp_start_tx(struct davinci_mcasp *mcasp)
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/* wait for XDATA to be cleared */
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/* wait for XDATA to be cleared */
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cnt = 0;
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cnt = 0;
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while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) &
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while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
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~XRDATA) && (cnt < 100000))
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(cnt < 100000))
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cnt++;
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cnt++;
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/* Release TX state machine */
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/* Release TX state machine */
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@ -505,6 +505,24 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
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regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
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FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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/*
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* For sai master mode, after several open/close sai,
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* there will be no frame clock, and can't recover
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* anymore. Add software reset to fix this issue.
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* This is a hardware bug, and will be fix in the
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* next sai version.
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*/
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if (!sai->is_slave_mode) {
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/* Software Reset for both Tx and Rx */
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regmap_write(sai->regmap,
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FSL_SAI_TCSR, FSL_SAI_CSR_SR);
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regmap_write(sai->regmap,
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FSL_SAI_RCSR, FSL_SAI_CSR_SR);
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/* Clear SR bit to finish the reset */
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regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
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regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
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}
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}
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}
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break;
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break;
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default:
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default:
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@ -152,8 +152,10 @@ static int rk_spdif_trigger(struct snd_pcm_substream *substream,
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
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ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
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SPDIF_DMACR_TDE_ENABLE,
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SPDIF_DMACR_TDE_ENABLE |
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SPDIF_DMACR_TDE_ENABLE);
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SPDIF_DMACR_TDL_MASK,
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SPDIF_DMACR_TDE_ENABLE |
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SPDIF_DMACR_TDL(16));
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if (ret != 0)
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if (ret != 0)
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return ret;
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return ret;
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@ -42,7 +42,7 @@
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#define SPDIF_DMACR_TDL_SHIFT 0
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#define SPDIF_DMACR_TDL_SHIFT 0
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#define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT)
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#define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT)
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#define SPDIF_DMACR_TDL_MASK (0x1f << SDPIF_DMACR_TDL_SHIFT)
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#define SPDIF_DMACR_TDL_MASK (0x1f << SPDIF_DMACR_TDL_SHIFT)
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/*
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/*
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* XFER
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* XFER
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