mlx5-fixes-2020-04-08
-----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEGhZs6bAKwk/OTgTpSD+KveBX+j4FAl6OVGEACgkQSD+KveBX +j7E8gf+K3xqUtcXUL3sCx1M2kY2Kj4ZjvL9H3m286mTmTAbSwMdEOJWaHfWVqZJ 8cf3Df/keK723YH+xPYbSQPloUgSIpazIFzjP6fvAkLKAu/AhLoVhBj3TF5hFaib BrK8L/QKoY6GGSuZb4+VJTenPYUPGFjNTlAHbchRO9V7SA9ngKZIz34ipVI8U+lT kRE8+YVsNM4c4ia3A4VcgAN/MCAbn+bTojS8/O5+ZyFYr3ErdgwFRHMzRiVnYeHE 9WFO4or2AVk4yiI5hqzH1/nJdhjOUK930Al68dfNdrHmmZXnD4lX9M4I+AoNB3qh zzykSerxjUC4yx4t8Nrq3na0U6RiSA== =KWRI -----END PGP SIGNATURE----- Merge tag 'mlx5-fixes-2020-04-08' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== Mellanox, mlx5 fixes 2020-04-08 This series introduces some fixes to mlx5 driver. Please pull and let me know if there is any problem. For -stable v5.3 ('net/mlx5: Fix frequent ioread PCI access during recovery') ('net/mlx5e: Add missing release firmware call') For -stable v5.4 ('net/mlx5e: Fix nest_level for vlan pop action') ('net/mlx5e: Fix pfnum in devlink port attribute') ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
3d61a39def
@ -23,7 +23,10 @@ static int mlx5_devlink_flash_update(struct devlink *devlink,
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if (err)
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return err;
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return mlx5_firmware_flash(dev, fw, extack);
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err = mlx5_firmware_flash(dev, fw, extack);
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release_firmware(fw);
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return err;
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}
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static u8 mlx5_fw_ver_major(u32 version)
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@ -67,11 +67,9 @@ struct mlx5_ct_ft {
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struct nf_flowtable *nf_ft;
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struct mlx5_tc_ct_priv *ct_priv;
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struct rhashtable ct_entries_ht;
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struct list_head ct_entries_list;
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};
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struct mlx5_ct_entry {
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struct list_head list;
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u16 zone;
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struct rhash_head node;
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struct flow_rule *flow_rule;
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@ -617,8 +615,6 @@ mlx5_tc_ct_block_flow_offload_add(struct mlx5_ct_ft *ft,
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if (err)
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goto err_insert;
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list_add(&entry->list, &ft->ct_entries_list);
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return 0;
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err_insert:
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@ -646,7 +642,6 @@ mlx5_tc_ct_block_flow_offload_del(struct mlx5_ct_ft *ft,
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WARN_ON(rhashtable_remove_fast(&ft->ct_entries_ht,
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&entry->node,
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cts_ht_params));
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list_del(&entry->list);
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kfree(entry);
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return 0;
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@ -818,7 +813,6 @@ mlx5_tc_ct_add_ft_cb(struct mlx5_tc_ct_priv *ct_priv, u16 zone,
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ft->zone = zone;
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ft->nf_ft = nf_ft;
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ft->ct_priv = ct_priv;
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INIT_LIST_HEAD(&ft->ct_entries_list);
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refcount_set(&ft->refcount, 1);
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err = rhashtable_init(&ft->ct_entries_ht, &cts_ht_params);
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@ -847,12 +841,12 @@ err_init:
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}
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static void
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mlx5_tc_ct_flush_ft(struct mlx5_tc_ct_priv *ct_priv, struct mlx5_ct_ft *ft)
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mlx5_tc_ct_flush_ft_entry(void *ptr, void *arg)
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{
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struct mlx5_ct_entry *entry;
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struct mlx5_tc_ct_priv *ct_priv = arg;
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struct mlx5_ct_entry *entry = ptr;
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list_for_each_entry(entry, &ft->ct_entries_list, list)
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mlx5_tc_ct_entry_del_rules(ft->ct_priv, entry);
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mlx5_tc_ct_entry_del_rules(ct_priv, entry);
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}
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static void
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@ -863,9 +857,10 @@ mlx5_tc_ct_del_ft_cb(struct mlx5_tc_ct_priv *ct_priv, struct mlx5_ct_ft *ft)
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nf_flow_table_offload_del_cb(ft->nf_ft,
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mlx5_tc_ct_block_flow_offload, ft);
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mlx5_tc_ct_flush_ft(ct_priv, ft);
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rhashtable_remove_fast(&ct_priv->zone_ht, &ft->node, zone_params);
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rhashtable_destroy(&ft->ct_entries_ht);
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rhashtable_free_and_destroy(&ft->ct_entries_ht,
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mlx5_tc_ct_flush_ft_entry,
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ct_priv);
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kfree(ft);
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}
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@ -5526,8 +5526,8 @@ static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
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#ifdef CONFIG_MLX5_CORE_EN_DCB
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mlx5e_dcbnl_delete_app(priv);
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#endif
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mlx5e_devlink_port_unregister(priv);
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unregister_netdev(priv->netdev);
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mlx5e_devlink_port_unregister(priv);
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mlx5e_detach(mdev, vpriv);
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mlx5e_destroy_netdev(priv);
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}
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@ -2050,29 +2050,30 @@ static int register_devlink_port(struct mlx5_core_dev *dev,
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struct mlx5_eswitch_rep *rep = rpriv->rep;
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struct netdev_phys_item_id ppid = {};
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unsigned int dl_port_index = 0;
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u16 pfnum;
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if (!is_devlink_port_supported(dev, rpriv))
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return 0;
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mlx5e_rep_get_port_parent_id(rpriv->netdev, &ppid);
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pfnum = PCI_FUNC(dev->pdev->devfn);
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if (rep->vport == MLX5_VPORT_UPLINK) {
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devlink_port_attrs_set(&rpriv->dl_port,
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DEVLINK_PORT_FLAVOUR_PHYSICAL,
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PCI_FUNC(dev->pdev->devfn), false, 0,
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pfnum, false, 0,
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&ppid.id[0], ppid.id_len);
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dl_port_index = vport_to_devlink_port_index(dev, rep->vport);
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} else if (rep->vport == MLX5_VPORT_PF) {
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devlink_port_attrs_pci_pf_set(&rpriv->dl_port,
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&ppid.id[0], ppid.id_len,
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dev->pdev->devfn);
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pfnum);
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dl_port_index = rep->vport;
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} else if (mlx5_eswitch_is_vf_vport(dev->priv.eswitch,
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rpriv->rep->vport)) {
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devlink_port_attrs_pci_vf_set(&rpriv->dl_port,
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&ppid.id[0], ppid.id_len,
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dev->pdev->devfn,
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rep->vport - 1);
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pfnum, rep->vport - 1);
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dl_port_index = vport_to_devlink_port_index(dev, rep->vport);
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}
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@ -1343,7 +1343,8 @@ mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
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if (err)
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return err;
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if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
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if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
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!(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
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err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
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dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
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if (err)
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@ -3558,12 +3559,13 @@ static int add_vlan_pop_action(struct mlx5e_priv *priv,
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struct mlx5_esw_flow_attr *attr,
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u32 *action)
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{
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int nest_level = attr->parse_attr->filter_dev->lower_level;
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struct flow_action_entry vlan_act = {
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.id = FLOW_ACTION_VLAN_POP,
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};
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int err = 0;
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int nest_level, err = 0;
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nest_level = attr->parse_attr->filter_dev->lower_level -
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priv->netdev->lower_level;
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while (nest_level--) {
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err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
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if (err)
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@ -403,7 +403,6 @@ enum {
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MLX5_ESW_ATTR_FLAG_VLAN_HANDLED = BIT(0),
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MLX5_ESW_ATTR_FLAG_SLOW_PATH = BIT(1),
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MLX5_ESW_ATTR_FLAG_NO_IN_PORT = BIT(2),
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MLX5_ESW_ATTR_FLAG_HAIRPIN = BIT(3),
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};
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struct mlx5_esw_flow_attr {
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@ -300,7 +300,6 @@ mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
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bool split = !!(attr->split_count);
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struct mlx5_flow_handle *rule;
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struct mlx5_flow_table *fdb;
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bool hairpin = false;
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int j, i = 0;
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if (esw->mode != MLX5_ESWITCH_OFFLOADS)
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@ -398,21 +397,16 @@ mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
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goto err_esw_get;
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}
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if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec)) {
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if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
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rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, attr,
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&flow_act, dest, i);
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hairpin = true;
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} else {
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else
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rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
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}
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if (IS_ERR(rule))
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goto err_add_rule;
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else
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atomic64_inc(&esw->offloads.num_flows);
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if (hairpin)
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attr->flags |= MLX5_ESW_ATTR_FLAG_HAIRPIN;
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return rule;
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err_add_rule:
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@ -501,7 +495,7 @@ __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
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mlx5_del_flow_rules(rule);
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if (attr->flags & MLX5_ESW_ATTR_FLAG_HAIRPIN) {
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if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
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/* unref the term table */
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for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
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if (attr->dests[i].termtbl)
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@ -243,7 +243,7 @@ recover_from_sw_reset:
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if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
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break;
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cond_resched();
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msleep(20);
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} while (!time_after(jiffies, end));
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if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
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