forked from Minki/linux
drm/i915/guc: kill the GuC client
We now only use 1 client without any plan to add more. The client is also only holding information about the WQ and the process desc, so we can just move those in the intel_guc structure and always use stage_id 0. v2: fix comment (John) v3: fix the comment for real, fix kerneldoc Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191205220243.27403-4-daniele.ceraolospurio@intel.com
This commit is contained in:
Daniele Ceraolo Spurio
parent
e9362e1336
commit
3c9abe886a
@ -466,9 +466,6 @@ GuC-based command submission
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.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
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:doc: GuC-based command submission
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.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
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:internal:
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HuC
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---
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.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
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@ -21,6 +21,7 @@
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#include "intel_reset.h"
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#include "uc/intel_guc.h"
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#include "uc/intel_guc_submission.h"
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#define RESET_MAX_RETRIES 3
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@ -1085,6 +1086,7 @@ static inline int intel_gt_reset_engine(struct intel_engine_cs *engine)
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int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
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{
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struct intel_gt *gt = engine->gt;
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bool uses_guc = intel_engine_in_guc_submission_mode(engine);
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int ret;
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GEM_TRACE("%s flags=%lx\n", engine->name, gt->reset.flags);
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@ -1100,14 +1102,14 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
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"Resetting %s for %s\n", engine->name, msg);
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atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
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if (!engine->gt->uc.guc.execbuf_client)
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if (!uses_guc)
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ret = intel_gt_reset_engine(engine);
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else
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ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
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if (ret) {
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/* If we fail here, we expect to fallback to a global reset */
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DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
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engine->gt->uc.guc.execbuf_client ? "GuC " : "",
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uses_guc ? "GuC " : "",
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engine->name, ret);
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goto out;
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}
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@ -46,9 +46,13 @@ struct intel_guc {
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struct i915_vma *stage_desc_pool;
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void *stage_desc_pool_vaddr;
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struct ida stage_ids;
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struct intel_guc_client *execbuf_client;
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struct i915_vma *workqueue;
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void *workqueue_vaddr;
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spinlock_t wq_lock;
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struct i915_vma *proc_desc;
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void *proc_desc_vaddr;
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/* Control params for fw initialization */
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u32 params[GUC_CTL_MAX_DWORDS];
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@ -31,7 +31,6 @@
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#define GUC_DOORBELL_INVALID 256
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#define GUC_PD_SIZE (PAGE_SIZE)
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#define GUC_WQ_SIZE (PAGE_SIZE * 2)
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/* Work queue item header definitions */
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@ -27,24 +27,13 @@
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* code) matches the old submission model and will be updated as part of the
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* upgrade to the new flow.
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*
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* GuC client:
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* A intel_guc_client refers to a submission path through GuC. Currently, there
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* is only one client, which is charged with all submissions to the GuC. This
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* struct is the owner of a process descriptor and a workqueue (both of them
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* inside a single gem object that contains all required pages for these
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* elements).
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*
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* GuC stage descriptor:
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* During initialization, the driver allocates a static pool of 1024 such
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* descriptors, and shares them with the GuC.
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* Currently, there exists a 1:1 mapping between a intel_guc_client and a
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* guc_stage_desc (via the client's stage_id), so effectively only one
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* gets used. This stage descriptor lets the GuC know about the workqueue and
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* descriptors, and shares them with the GuC. Currently, we only use one
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* descriptor. This stage descriptor lets the GuC know about the workqueue and
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* process descriptor. Theoretically, it also lets the GuC know about our HW
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* contexts (context ID, etc...), but we actually employ a kind of submission
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* where the GuC uses the LRCA sent via the work item instead (the single
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* guc_stage_desc associated to execbuf client contains information about the
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* default kernel context only, but this is essentially unused). This is called
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* where the GuC uses the LRCA sent via the work item instead. This is called
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* a "proxy" submission.
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*
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* The Scratch registers:
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@ -71,33 +60,45 @@ static inline struct i915_priolist *to_priolist(struct rb_node *rb)
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return rb_entry(rb, struct i915_priolist, node);
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}
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static inline bool is_high_priority(struct intel_guc_client *client)
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static struct guc_stage_desc *__get_stage_desc(struct intel_guc *guc, u32 id)
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{
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return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH ||
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client->priority == GUC_CLIENT_PRIORITY_HIGH);
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struct guc_stage_desc *base = guc->stage_desc_pool_vaddr;
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return &base[id];
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}
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static struct guc_stage_desc *__get_stage_desc(struct intel_guc_client *client)
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static int guc_workqueue_create(struct intel_guc *guc)
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{
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struct guc_stage_desc *base = client->guc->stage_desc_pool_vaddr;
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return &base[client->stage_id];
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return intel_guc_allocate_and_map_vma(guc, GUC_WQ_SIZE, &guc->workqueue,
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&guc->workqueue_vaddr);
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}
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static inline struct guc_process_desc *
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__get_process_desc(struct intel_guc_client *client)
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static void guc_workqueue_destroy(struct intel_guc *guc)
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{
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return client->vaddr;
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i915_vma_unpin_and_release(&guc->workqueue, I915_VMA_RELEASE_MAP);
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}
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/*
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* Initialise the process descriptor shared with the GuC firmware.
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*/
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static void guc_proc_desc_init(struct intel_guc_client *client)
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static int guc_proc_desc_create(struct intel_guc *guc)
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{
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const u32 size = PAGE_ALIGN(sizeof(struct guc_process_desc));
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return intel_guc_allocate_and_map_vma(guc, size, &guc->proc_desc,
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&guc->proc_desc_vaddr);
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}
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static void guc_proc_desc_destroy(struct intel_guc *guc)
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{
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i915_vma_unpin_and_release(&guc->proc_desc, I915_VMA_RELEASE_MAP);
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}
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static void guc_proc_desc_init(struct intel_guc *guc)
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{
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struct guc_process_desc *desc;
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desc = memset(__get_process_desc(client), 0, sizeof(*desc));
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desc = memset(guc->proc_desc_vaddr, 0, sizeof(*desc));
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/*
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* XXX: pDoorbell and WQVBaseAddress are pointers in process address
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@ -108,39 +109,27 @@ static void guc_proc_desc_init(struct intel_guc_client *client)
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desc->wq_base_addr = 0;
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desc->db_base_addr = 0;
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desc->stage_id = client->stage_id;
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desc->wq_size_bytes = GUC_WQ_SIZE;
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desc->wq_status = WQ_STATUS_ACTIVE;
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desc->priority = client->priority;
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desc->priority = GUC_CLIENT_PRIORITY_KMD_NORMAL;
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}
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static void guc_proc_desc_fini(struct intel_guc_client *client)
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static void guc_proc_desc_fini(struct intel_guc *guc)
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{
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struct guc_process_desc *desc;
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desc = __get_process_desc(client);
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memset(desc, 0, sizeof(*desc));
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memset(guc->proc_desc_vaddr, 0, sizeof(struct guc_process_desc));
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}
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static int guc_stage_desc_pool_create(struct intel_guc *guc)
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{
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u32 size = PAGE_ALIGN(sizeof(struct guc_stage_desc) *
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GUC_MAX_STAGE_DESCRIPTORS);
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int ret;
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ret = intel_guc_allocate_and_map_vma(guc, size, &guc->stage_desc_pool,
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&guc->stage_desc_pool_vaddr);
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if (ret)
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return ret;
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ida_init(&guc->stage_ids);
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return 0;
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return intel_guc_allocate_and_map_vma(guc, size, &guc->stage_desc_pool,
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&guc->stage_desc_pool_vaddr);
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}
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static void guc_stage_desc_pool_destroy(struct intel_guc *guc)
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{
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ida_destroy(&guc->stage_ids);
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i915_vma_unpin_and_release(&guc->stage_desc_pool, I915_VMA_RELEASE_MAP);
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}
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@ -148,58 +137,49 @@ static void guc_stage_desc_pool_destroy(struct intel_guc *guc)
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* Initialise/clear the stage descriptor shared with the GuC firmware.
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*
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* This descriptor tells the GuC where (in GGTT space) to find the important
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* data structures relating to this client (process descriptor, write queue,
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* data structures related to work submission (process descriptor, write queue,
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* etc).
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*/
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static void guc_stage_desc_init(struct intel_guc_client *client)
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static void guc_stage_desc_init(struct intel_guc *guc)
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{
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struct intel_guc *guc = client->guc;
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struct guc_stage_desc *desc;
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u32 gfx_addr;
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desc = __get_stage_desc(client);
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/* we only use 1 stage desc, so hardcode it to 0 */
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desc = __get_stage_desc(guc, 0);
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memset(desc, 0, sizeof(*desc));
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desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE |
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GUC_STAGE_DESC_ATTR_KERNEL;
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if (is_high_priority(client))
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desc->attribute |= GUC_STAGE_DESC_ATTR_PREEMPT;
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desc->stage_id = client->stage_id;
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desc->priority = client->priority;
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/*
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* The process descriptor and workqueue are all parts of the client
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* object, which the GuC will reference via the GGTT
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*/
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gfx_addr = intel_guc_ggtt_offset(guc, client->vma);
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desc->process_desc = gfx_addr;
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desc->wq_addr = gfx_addr + GUC_PD_SIZE;
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desc->stage_id = 0;
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desc->priority = GUC_CLIENT_PRIORITY_KMD_NORMAL;
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desc->process_desc = intel_guc_ggtt_offset(guc, guc->proc_desc);
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desc->wq_addr = intel_guc_ggtt_offset(guc, guc->workqueue);
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desc->wq_size = GUC_WQ_SIZE;
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desc->desc_private = ptr_to_u64(client);
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}
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static void guc_stage_desc_fini(struct intel_guc_client *client)
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static void guc_stage_desc_fini(struct intel_guc *guc)
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{
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struct guc_stage_desc *desc;
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desc = __get_stage_desc(client);
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desc = __get_stage_desc(guc, 0);
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memset(desc, 0, sizeof(*desc));
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}
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/* Construct a Work Item and append it to the GuC's Work Queue */
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static void guc_wq_item_append(struct intel_guc_client *client,
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static void guc_wq_item_append(struct intel_guc *guc,
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u32 target_engine, u32 context_desc,
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u32 ring_tail, u32 fence_id)
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{
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/* wqi_len is in DWords, and does not include the one-word header */
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const size_t wqi_size = sizeof(struct guc_wq_item);
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const u32 wqi_len = wqi_size / sizeof(u32) - 1;
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struct guc_process_desc *desc = __get_process_desc(client);
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struct guc_process_desc *desc = guc->proc_desc_vaddr;
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struct guc_wq_item *wqi;
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u32 wq_off;
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lockdep_assert_held(&client->wq_lock);
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lockdep_assert_held(&guc->wq_lock);
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/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
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* should not have the case where structure wqi is across page, neither
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@ -219,8 +199,7 @@ static void guc_wq_item_append(struct intel_guc_client *client,
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GUC_WQ_SIZE) < wqi_size);
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GEM_BUG_ON(wq_off & (wqi_size - 1));
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/* WQ starts from the page after process_desc */
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wqi = client->vaddr + wq_off + GUC_PD_SIZE;
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wqi = guc->workqueue_vaddr + wq_off;
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/* Now fill in the 4-word work queue item */
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wqi->header = WQ_TYPE_INORDER |
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@ -238,12 +217,11 @@ static void guc_wq_item_append(struct intel_guc_client *client,
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static void guc_add_request(struct intel_guc *guc, struct i915_request *rq)
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{
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struct intel_guc_client *client = guc->execbuf_client;
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struct intel_engine_cs *engine = rq->engine;
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u32 ctx_desc = lower_32_bits(rq->hw_context->lrc_desc);
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u32 ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
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guc_wq_item_append(client, engine->guc_id, ctx_desc,
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guc_wq_item_append(guc, engine->guc_id, ctx_desc,
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ring_tail, rq->fence.seqno);
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}
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@ -266,9 +244,8 @@ static void guc_submit(struct intel_engine_cs *engine,
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struct i915_request **end)
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{
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struct intel_guc *guc = &engine->gt->uc.guc;
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struct intel_guc_client *client = guc->execbuf_client;
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spin_lock(&client->wq_lock);
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spin_lock(&guc->wq_lock);
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do {
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struct i915_request *rq = *out++;
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@ -277,7 +254,7 @@ static void guc_submit(struct intel_engine_cs *engine,
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guc_add_request(guc, rq);
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} while (out != end);
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spin_unlock(&client->wq_lock);
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spin_unlock(&guc->wq_lock);
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}
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static inline int rq_prio(const struct i915_request *rq)
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@ -528,126 +505,6 @@ static void guc_reset_finish(struct intel_engine_cs *engine)
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* path of guc_submit() above.
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*/
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/**
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* guc_client_alloc() - Allocate an intel_guc_client
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* @guc: the intel_guc structure
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* @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
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* The kernel client to replace ExecList submission is created with
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* NORMAL priority. Priority of a client for scheduler can be HIGH,
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* while a preemption context can use CRITICAL.
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*
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* Return: An intel_guc_client object if success, else NULL.
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*/
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static struct intel_guc_client *
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guc_client_alloc(struct intel_guc *guc, u32 priority)
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{
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struct intel_guc_client *client;
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struct i915_vma *vma;
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void *vaddr;
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int ret;
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client = kzalloc(sizeof(*client), GFP_KERNEL);
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if (!client)
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return ERR_PTR(-ENOMEM);
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client->guc = guc;
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client->priority = priority;
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spin_lock_init(&client->wq_lock);
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ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS,
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GFP_KERNEL);
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if (ret < 0)
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goto err_client;
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client->stage_id = ret;
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/* The first page is proc_desc. Two following pages are wq. */
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vma = intel_guc_allocate_vma(guc, GUC_PD_SIZE + GUC_WQ_SIZE);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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goto err_id;
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}
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/* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
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client->vma = vma;
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vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
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if (IS_ERR(vaddr)) {
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ret = PTR_ERR(vaddr);
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goto err_vma;
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}
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client->vaddr = vaddr;
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DRM_DEBUG_DRIVER("new priority %u client %p: stage_id %u\n",
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priority, client, client->stage_id);
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return client;
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err_vma:
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i915_vma_unpin_and_release(&client->vma, 0);
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err_id:
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ida_simple_remove(&guc->stage_ids, client->stage_id);
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err_client:
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kfree(client);
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return ERR_PTR(ret);
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}
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static void guc_client_free(struct intel_guc_client *client)
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{
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i915_vma_unpin_and_release(&client->vma, I915_VMA_RELEASE_MAP);
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ida_simple_remove(&client->guc->stage_ids, client->stage_id);
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kfree(client);
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}
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static int guc_clients_create(struct intel_guc *guc)
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{
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struct intel_guc_client *client;
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GEM_BUG_ON(guc->execbuf_client);
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client = guc_client_alloc(guc, GUC_CLIENT_PRIORITY_KMD_NORMAL);
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if (IS_ERR(client)) {
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DRM_ERROR("Failed to create GuC client for submission!\n");
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return PTR_ERR(client);
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}
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guc->execbuf_client = client;
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return 0;
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}
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static void guc_clients_destroy(struct intel_guc *guc)
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{
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struct intel_guc_client *client;
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|
||||
client = fetch_and_zero(&guc->execbuf_client);
|
||||
if (client)
|
||||
guc_client_free(client);
|
||||
}
|
||||
|
||||
static void __guc_client_enable(struct intel_guc_client *client)
|
||||
{
|
||||
guc_proc_desc_init(client);
|
||||
guc_stage_desc_init(client);
|
||||
}
|
||||
|
||||
static void __guc_client_disable(struct intel_guc_client *client)
|
||||
{
|
||||
/* Note: By the time we're here, GuC may have already been reset */
|
||||
guc_stage_desc_fini(client);
|
||||
guc_proc_desc_fini(client);
|
||||
}
|
||||
|
||||
static void guc_clients_enable(struct intel_guc *guc)
|
||||
{
|
||||
__guc_client_enable(guc->execbuf_client);
|
||||
}
|
||||
|
||||
static void guc_clients_disable(struct intel_guc *guc)
|
||||
{
|
||||
if (guc->execbuf_client)
|
||||
__guc_client_disable(guc->execbuf_client);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up the memory resources to be shared with the GuC (via the GGTT)
|
||||
* at firmware loading time.
|
||||
@ -668,12 +525,20 @@ int intel_guc_submission_init(struct intel_guc *guc)
|
||||
*/
|
||||
GEM_BUG_ON(!guc->stage_desc_pool);
|
||||
|
||||
ret = guc_clients_create(guc);
|
||||
ret = guc_workqueue_create(guc);
|
||||
if (ret)
|
||||
goto err_pool;
|
||||
|
||||
ret = guc_proc_desc_create(guc);
|
||||
if (ret)
|
||||
goto err_workqueue;
|
||||
|
||||
spin_lock_init(&guc->wq_lock);
|
||||
|
||||
return 0;
|
||||
|
||||
err_workqueue:
|
||||
guc_workqueue_destroy(guc);
|
||||
err_pool:
|
||||
guc_stage_desc_pool_destroy(guc);
|
||||
return ret;
|
||||
@ -681,10 +546,11 @@ err_pool:
|
||||
|
||||
void intel_guc_submission_fini(struct intel_guc *guc)
|
||||
{
|
||||
guc_clients_destroy(guc);
|
||||
|
||||
if (guc->stage_desc_pool)
|
||||
if (guc->stage_desc_pool) {
|
||||
guc_proc_desc_destroy(guc);
|
||||
guc_workqueue_destroy(guc);
|
||||
guc_stage_desc_pool_destroy(guc);
|
||||
}
|
||||
}
|
||||
|
||||
static void guc_interrupts_capture(struct intel_gt *gt)
|
||||
@ -770,9 +636,8 @@ void intel_guc_submission_enable(struct intel_guc *guc)
|
||||
sizeof(struct guc_wq_item) *
|
||||
I915_NUM_ENGINES > GUC_WQ_SIZE);
|
||||
|
||||
GEM_BUG_ON(!guc->execbuf_client);
|
||||
|
||||
guc_clients_enable(guc);
|
||||
guc_proc_desc_init(guc);
|
||||
guc_stage_desc_init(guc);
|
||||
|
||||
/* Take over from manual control of ELSP (execlists) */
|
||||
guc_interrupts_capture(gt);
|
||||
@ -789,8 +654,12 @@ void intel_guc_submission_disable(struct intel_guc *guc)
|
||||
|
||||
GEM_BUG_ON(gt->awake); /* GT should be parked first */
|
||||
|
||||
/* Note: By the time we're here, GuC may have already been reset */
|
||||
|
||||
guc_interrupts_release(gt);
|
||||
guc_clients_disable(guc);
|
||||
|
||||
guc_stage_desc_fini(guc);
|
||||
guc_proc_desc_fini(guc);
|
||||
}
|
||||
|
||||
static bool __guc_submission_support(struct intel_guc *guc)
|
||||
@ -808,3 +677,8 @@ void intel_guc_submission_init_early(struct intel_guc *guc)
|
||||
{
|
||||
guc->submission_supported = __guc_submission_support(guc);
|
||||
}
|
||||
|
||||
bool intel_engine_in_guc_submission_mode(const struct intel_engine_cs *engine)
|
||||
{
|
||||
return engine->set_default_submission == guc_set_default_submission;
|
||||
}
|
||||
|
||||
@ -6,48 +6,10 @@
|
||||
#ifndef _INTEL_GUC_SUBMISSION_H_
|
||||
#define _INTEL_GUC_SUBMISSION_H_
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "gt/intel_engine_types.h"
|
||||
|
||||
#include "i915_gem.h"
|
||||
#include "i915_selftest.h"
|
||||
|
||||
struct drm_i915_private;
|
||||
|
||||
/*
|
||||
* This structure primarily describes the GEM object shared with the GuC.
|
||||
* The specs sometimes refer to this object as a "GuC context", but we use
|
||||
* the term "client" to avoid confusion with hardware contexts. This
|
||||
* GEM object is held for the entire lifetime of our interaction with
|
||||
* the GuC, being allocated before the GuC is loaded with its firmware.
|
||||
* Because there's no way to update the address used by the GuC after
|
||||
* initialisation, the shared object must stay pinned into the GGTT as
|
||||
* long as the GuC is in use. We also keep the first page (only) mapped
|
||||
* into kernel address space, as it includes shared data that must be
|
||||
* updated on every request submission.
|
||||
*
|
||||
* The single GEM object described here is actually made up of several
|
||||
* separate areas, as far as the GuC is concerned. The first page (kept
|
||||
* kmap'd) includes the "process descriptor" which holds sequence data for
|
||||
* the doorbell, and one cacheline which actually *is* the doorbell; a
|
||||
* write to this will "ring the doorbell" (i.e. send an interrupt to the
|
||||
* GuC). The subsequent pages of the client object constitute the work
|
||||
* queue (a circular array of work items), again described in the process
|
||||
* descriptor. Work queue pages are mapped momentarily as required.
|
||||
*/
|
||||
struct intel_guc_client {
|
||||
struct i915_vma *vma;
|
||||
void *vaddr;
|
||||
struct intel_guc *guc;
|
||||
|
||||
/* bitmap of (host) engine ids */
|
||||
u32 priority;
|
||||
u32 stage_id;
|
||||
|
||||
/* Protects GuC client's WQ access */
|
||||
spinlock_t wq_lock;
|
||||
};
|
||||
struct intel_guc;
|
||||
struct intel_engine_cs;
|
||||
|
||||
void intel_guc_submission_init_early(struct intel_guc *guc);
|
||||
int intel_guc_submission_init(struct intel_guc *guc);
|
||||
@ -56,5 +18,6 @@ void intel_guc_submission_disable(struct intel_guc *guc);
|
||||
void intel_guc_submission_fini(struct intel_guc *guc);
|
||||
int intel_guc_preempt_work_create(struct intel_guc *guc);
|
||||
void intel_guc_preempt_work_destroy(struct intel_guc *guc);
|
||||
bool intel_engine_in_guc_submission_mode(const struct intel_engine_cs *engine);
|
||||
|
||||
#endif
|
||||
|
||||
@ -1792,23 +1792,12 @@ static void i915_guc_log_info(struct seq_file *m,
|
||||
static int i915_guc_info(struct seq_file *m, void *data)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = node_to_i915(m->private);
|
||||
const struct intel_guc *guc = &dev_priv->gt.uc.guc;
|
||||
struct intel_guc_client *client = guc->execbuf_client;
|
||||
|
||||
if (!USES_GUC(dev_priv))
|
||||
return -ENODEV;
|
||||
|
||||
i915_guc_log_info(m, dev_priv);
|
||||
|
||||
if (!USES_GUC_SUBMISSION(dev_priv))
|
||||
return 0;
|
||||
|
||||
GEM_BUG_ON(!guc->execbuf_client);
|
||||
|
||||
seq_printf(m, "\nGuC execbuf client @ %p:\n", client);
|
||||
seq_printf(m, "\tPriority %d, GuC stage index: %u\n",
|
||||
client->priority,
|
||||
client->stage_id);
|
||||
/* Add more as required ... */
|
||||
|
||||
return 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user