dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings
On the first revision of the bindings, only the gates + resets were known in the AO Clock HW, but more registers used to configures AO clock are known to be spread among the AO register space. This patch adds a parent node for the entire system control zone for the AO domain then moves the clock controller as a subnode of the system control node. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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@ -5,9 +5,11 @@ controllers within the Always-On part of the SoC.
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Required Properties:
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- compatible: should be "amlogic,gxbb-aoclkc"
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- reg: physical base address of the clock controller and length of memory
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mapped region.
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- compatible: value should be different for each SoC family as :
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- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
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- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
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- GXM (S912) : "amlogic,meson-gxm-aoclkc"
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followed by the common "amlogic,meson-gx-aoclkc"
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- #clock-cells: should be 1.
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@ -23,14 +25,22 @@ to specify the reset which they consume. All available resets are defined as
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preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
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used in device tree sources.
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Parent node should have the following properties :
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- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
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- reg: base address and size of the AO system control register space.
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Example: AO Clock controller node:
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clkc_AO: clock-controller@040 {
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compatible = "amlogic,gxbb-aoclkc";
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reg = <0x0 0x040 0x0 0x4>;
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ao_sysctrl: sys-ctrl@0 {
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compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
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reg = <0x0 0x0 0x0 0x100>;
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clkc_AO: clock-controller {
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compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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Example: UART controller node that consumes the clock and reset generated
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by the clock controller:
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