forked from Minki/linux
Merge remote-tracking branches 'asoc/fix/fsl-mxs-saif' and 'asoc/fix/sunxi' into asoc-linus
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commit
39bc30f253
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@ -119,23 +119,33 @@ static int mxs_saif_set_clk(struct mxs_saif *saif,
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* Set SAIF clock
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* Set SAIF clock
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*
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*
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* The SAIF clock should be either 384*fs or 512*fs.
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* The SAIF clock should be either 384*fs or 512*fs.
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* If MCLK is used, the SAIF clk ratio need to match mclk ratio.
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* If MCLK is used, the SAIF clk ratio needs to match mclk ratio.
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* For 32x mclk, set saif clk as 512*fs.
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* For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs.
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* For 48x mclk, set saif clk as 384*fs.
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* For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs.
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*
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*
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* If MCLK is not used, we just set saif clk to 512*fs.
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* If MCLK is not used, we just set saif clk to 512*fs.
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*/
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*/
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clk_prepare_enable(master_saif->clk);
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clk_prepare_enable(master_saif->clk);
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if (master_saif->mclk_in_use) {
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if (master_saif->mclk_in_use) {
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if (mclk % 32 == 0) {
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switch (mclk / rate) {
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case 32:
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case 64:
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case 128:
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case 256:
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case 512:
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scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
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scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
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ret = clk_set_rate(master_saif->clk, 512 * rate);
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ret = clk_set_rate(master_saif->clk, 512 * rate);
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} else if (mclk % 48 == 0) {
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break;
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case 48:
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case 96:
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case 192:
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case 384:
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scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
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scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
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ret = clk_set_rate(master_saif->clk, 384 * rate);
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ret = clk_set_rate(master_saif->clk, 384 * rate);
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} else {
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break;
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/* SAIF MCLK should be either 32x or 48x */
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default:
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/* SAIF MCLK should be a sub-rate of 512x or 384x */
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clk_disable_unprepare(master_saif->clk);
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clk_disable_unprepare(master_saif->clk);
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return -EINVAL;
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return -EINVAL;
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}
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}
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@ -299,6 +309,16 @@ static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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return -EBUSY;
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return -EBUSY;
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}
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}
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/* If SAIF1 is configured as slave, the clk gate needs to be cleared
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* before the register can be written.
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*/
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if (saif->id != saif->master_id) {
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__raw_writel(BM_SAIF_CTRL_SFTRST,
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saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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__raw_writel(BM_SAIF_CTRL_CLKGATE,
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saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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}
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scr0 = __raw_readl(saif->base + SAIF_CTRL);
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scr0 = __raw_readl(saif->base + SAIF_CTRL);
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scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
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scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
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& ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
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& ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
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@ -694,10 +694,10 @@ static int sun4i_i2s_probe(struct platform_device *pdev)
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}
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}
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i2s->playback_dma_data.addr = res->start + SUN4I_I2S_FIFO_TX_REG;
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i2s->playback_dma_data.addr = res->start + SUN4I_I2S_FIFO_TX_REG;
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i2s->playback_dma_data.maxburst = 4;
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i2s->playback_dma_data.maxburst = 8;
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i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
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i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
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i2s->capture_dma_data.maxburst = 4;
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i2s->capture_dma_data.maxburst = 8;
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pm_runtime_enable(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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if (!pm_runtime_enabled(&pdev->dev)) {
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if (!pm_runtime_enabled(&pdev->dev)) {
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