forked from Minki/linux
dmaengine: fsl-edma: add edma version and configurable registers
This patch adds configurable registers (using __iomem addresses) to allow the use of fsl-edma-common code with slightly different edma module versions, as Vybrid (v1) and ColdFire (v2) are. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Tested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
parent
9d831528a6
commit
377eaf3b3c
@ -43,20 +43,20 @@
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static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
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{
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void __iomem *addr = fsl_chan->edma->membase;
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struct edma_regs *regs = &fsl_chan->edma->regs;
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u32 ch = fsl_chan->vchan.chan.chan_id;
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edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
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edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
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edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
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edma_writeb(fsl_chan->edma, ch, regs->serq);
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}
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void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
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{
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void __iomem *addr = fsl_chan->edma->membase;
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struct edma_regs *regs = &fsl_chan->edma->regs;
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u32 ch = fsl_chan->vchan.chan.chan_id;
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edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
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edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
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edma_writeb(fsl_chan->edma, ch, regs->cerq);
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edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
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}
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EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
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@ -184,7 +184,7 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
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struct virt_dma_desc *vdesc, bool in_progress)
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{
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struct fsl_edma_desc *edesc = fsl_chan->edesc;
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void __iomem *addr = fsl_chan->edma->membase;
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struct edma_regs *regs = &fsl_chan->edma->regs;
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u32 ch = fsl_chan->vchan.chan.chan_id;
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enum dma_transfer_direction dir = fsl_chan->fsc.dir;
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dma_addr_t cur_addr, dma_addr;
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@ -200,11 +200,9 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
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return len;
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if (dir == DMA_MEM_TO_DEV)
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cur_addr = edma_readl(
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fsl_chan->edma, addr + EDMA_TCD_SADDR(ch));
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cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].saddr);
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else
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cur_addr = edma_readl(
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fsl_chan->edma, addr + EDMA_TCD_DADDR(ch));
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cur_addr = edma_readl(fsl_chan->edma, ®s->tcd[ch].daddr);
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/* figure out the finished and calculate the residue */
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for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
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@ -261,7 +259,7 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
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struct fsl_edma_hw_tcd *tcd)
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{
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struct fsl_edma_engine *edma = fsl_chan->edma;
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void __iomem *addr = fsl_chan->edma->membase;
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struct edma_regs *regs = &fsl_chan->edma->regs;
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u32 ch = fsl_chan->vchan.chan.chan_id;
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/*
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@ -269,24 +267,24 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
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* endian format. However, we need to load the TCD registers in
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* big- or little-endian obeying the eDMA engine model endian.
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*/
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edma_writew(edma, 0, addr + EDMA_TCD_CSR(ch));
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edma_writel(edma, le32_to_cpu(tcd->saddr), addr + EDMA_TCD_SADDR(ch));
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edma_writel(edma, le32_to_cpu(tcd->daddr), addr + EDMA_TCD_DADDR(ch));
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edma_writew(edma, 0, ®s->tcd[ch].csr);
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edma_writel(edma, le32_to_cpu(tcd->saddr), ®s->tcd[ch].saddr);
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edma_writel(edma, le32_to_cpu(tcd->daddr), ®s->tcd[ch].daddr);
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edma_writew(edma, le16_to_cpu(tcd->attr), addr + EDMA_TCD_ATTR(ch));
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edma_writew(edma, le16_to_cpu(tcd->soff), addr + EDMA_TCD_SOFF(ch));
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edma_writew(edma, le16_to_cpu(tcd->attr), ®s->tcd[ch].attr);
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edma_writew(edma, le16_to_cpu(tcd->soff), ®s->tcd[ch].soff);
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edma_writel(edma, le32_to_cpu(tcd->nbytes), addr + EDMA_TCD_NBYTES(ch));
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edma_writel(edma, le32_to_cpu(tcd->slast), addr + EDMA_TCD_SLAST(ch));
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edma_writel(edma, le32_to_cpu(tcd->nbytes), ®s->tcd[ch].nbytes);
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edma_writel(edma, le32_to_cpu(tcd->slast), ®s->tcd[ch].slast);
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edma_writew(edma, le16_to_cpu(tcd->citer), addr + EDMA_TCD_CITER(ch));
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edma_writew(edma, le16_to_cpu(tcd->biter), addr + EDMA_TCD_BITER(ch));
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edma_writew(edma, le16_to_cpu(tcd->doff), addr + EDMA_TCD_DOFF(ch));
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edma_writew(edma, le16_to_cpu(tcd->citer), ®s->tcd[ch].citer);
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edma_writew(edma, le16_to_cpu(tcd->biter), ®s->tcd[ch].biter);
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edma_writew(edma, le16_to_cpu(tcd->doff), ®s->tcd[ch].doff);
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edma_writel(edma,
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le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA(ch));
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edma_writel(edma, le32_to_cpu(tcd->dlast_sga),
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®s->tcd[ch].dlast_sga);
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edma_writew(edma, le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR(ch));
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edma_writew(edma, le16_to_cpu(tcd->csr), ®s->tcd[ch].csr);
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}
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static inline
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@ -308,15 +306,15 @@ void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
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tcd->attr = cpu_to_le16(attr);
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tcd->soff = cpu_to_le16(EDMA_TCD_SOFF_SOFF(soff));
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tcd->soff = cpu_to_le16(soff);
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tcd->nbytes = cpu_to_le32(EDMA_TCD_NBYTES_NBYTES(nbytes));
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tcd->slast = cpu_to_le32(EDMA_TCD_SLAST_SLAST(slast));
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tcd->nbytes = cpu_to_le32(nbytes);
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tcd->slast = cpu_to_le32(slast);
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tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer));
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tcd->doff = cpu_to_le16(EDMA_TCD_DOFF_DOFF(doff));
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tcd->doff = cpu_to_le16(doff);
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tcd->dlast_sga = cpu_to_le32(EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga));
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tcd->dlast_sga = cpu_to_le32(dlast_sga);
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tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter));
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if (major_int)
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@ -549,4 +547,52 @@ void fsl_edma_cleanup_vchan(struct dma_device *dmadev)
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}
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EXPORT_SYMBOL_GPL(fsl_edma_cleanup_vchan);
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/*
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* On the 32 channels Vybrid/mpc577x edma version (here called "v1"),
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* register offsets are different compared to ColdFire mcf5441x 64 channels
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* edma (here called "v2").
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*
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* This function sets up register offsets as per proper declared version
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* so must be called in xxx_edma_probe() just after setting the
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* edma "version" and "membase" appropriately.
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*/
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void fsl_edma_setup_regs(struct fsl_edma_engine *edma)
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{
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edma->regs.cr = edma->membase + EDMA_CR;
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edma->regs.es = edma->membase + EDMA_ES;
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edma->regs.erql = edma->membase + EDMA_ERQ;
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edma->regs.eeil = edma->membase + EDMA_EEI;
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edma->regs.serq = edma->membase + ((edma->version == v1) ?
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EDMA_SERQ : EDMA64_SERQ);
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edma->regs.cerq = edma->membase + ((edma->version == v1) ?
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EDMA_CERQ : EDMA64_CERQ);
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edma->regs.seei = edma->membase + ((edma->version == v1) ?
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EDMA_SEEI : EDMA64_SEEI);
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edma->regs.ceei = edma->membase + ((edma->version == v1) ?
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EDMA_CEEI : EDMA64_CEEI);
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edma->regs.cint = edma->membase + ((edma->version == v1) ?
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EDMA_CINT : EDMA64_CINT);
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edma->regs.cerr = edma->membase + ((edma->version == v1) ?
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EDMA_CERR : EDMA64_CERR);
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edma->regs.ssrt = edma->membase + ((edma->version == v1) ?
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EDMA_SSRT : EDMA64_SSRT);
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edma->regs.cdne = edma->membase + ((edma->version == v1) ?
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EDMA_CDNE : EDMA64_CDNE);
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edma->regs.intl = edma->membase + ((edma->version == v1) ?
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EDMA_INTR : EDMA64_INTL);
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edma->regs.errl = edma->membase + ((edma->version == v1) ?
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EDMA_ERR : EDMA64_ERRL);
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if (edma->version == v2) {
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edma->regs.erqh = edma->membase + EDMA64_ERQH;
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edma->regs.eeih = edma->membase + EDMA64_EEIH;
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edma->regs.errh = edma->membase + EDMA64_ERRH;
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edma->regs.inth = edma->membase + EDMA64_INTH;
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}
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edma->regs.tcd = edma->membase + EDMA_TCD;
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}
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EXPORT_SYMBOL_GPL(fsl_edma_setup_regs);
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MODULE_LICENSE("GPL v2");
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@ -8,35 +8,6 @@
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#include "virt-dma.h"
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#define EDMA_CR 0x00
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#define EDMA_ES 0x04
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#define EDMA_ERQ 0x0C
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#define EDMA_EEI 0x14
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#define EDMA_SERQ 0x1B
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#define EDMA_CERQ 0x1A
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#define EDMA_SEEI 0x19
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#define EDMA_CEEI 0x18
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#define EDMA_CINT 0x1F
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#define EDMA_CERR 0x1E
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#define EDMA_SSRT 0x1D
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#define EDMA_CDNE 0x1C
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#define EDMA_INTR 0x24
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#define EDMA_ERR 0x2C
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#define EDMA_TCD_SADDR(x) (0x1000 + 32 * (x))
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#define EDMA_TCD_SOFF(x) (0x1004 + 32 * (x))
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#define EDMA_TCD_ATTR(x) (0x1006 + 32 * (x))
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#define EDMA_TCD_NBYTES(x) (0x1008 + 32 * (x))
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#define EDMA_TCD_SLAST(x) (0x100C + 32 * (x))
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#define EDMA_TCD_DADDR(x) (0x1010 + 32 * (x))
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#define EDMA_TCD_DOFF(x) (0x1014 + 32 * (x))
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#define EDMA_TCD_CITER_ELINK(x) (0x1016 + 32 * (x))
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#define EDMA_TCD_CITER(x) (0x1016 + 32 * (x))
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#define EDMA_TCD_DLAST_SGA(x) (0x1018 + 32 * (x))
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#define EDMA_TCD_CSR(x) (0x101C + 32 * (x))
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#define EDMA_TCD_BITER_ELINK(x) (0x101E + 32 * (x))
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#define EDMA_TCD_BITER(x) (0x101E + 32 * (x))
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#define EDMA_CR_EDBG BIT(1)
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#define EDMA_CR_ERCA BIT(2)
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#define EDMA_CR_ERGA BIT(3)
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@ -114,6 +85,31 @@ struct fsl_edma_hw_tcd {
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__le16 biter;
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};
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/*
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* These are iomem pointers, for both v32 and v64.
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*/
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struct edma_regs {
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void __iomem *cr;
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void __iomem *es;
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void __iomem *erqh;
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void __iomem *erql; /* aka erq on v32 */
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void __iomem *eeih;
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void __iomem *eeil; /* aka eei on v32 */
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void __iomem *seei;
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void __iomem *ceei;
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void __iomem *serq;
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void __iomem *cerq;
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void __iomem *cint;
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void __iomem *cerr;
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void __iomem *ssrt;
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void __iomem *cdne;
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void __iomem *inth;
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void __iomem *intl;
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void __iomem *errh;
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void __iomem *errl;
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struct fsl_edma_hw_tcd __iomem *tcd;
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};
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struct fsl_edma_sw_tcd {
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dma_addr_t ptcd;
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struct fsl_edma_hw_tcd *vtcd;
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@ -147,6 +143,11 @@ struct fsl_edma_desc {
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struct fsl_edma_sw_tcd tcd[];
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};
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enum edma_version {
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v1, /* 32ch, Vybdir, mpc57x, etc */
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v2, /* 64ch Coldfire */
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};
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struct fsl_edma_engine {
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struct dma_device dma_dev;
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void __iomem *membase;
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@ -157,6 +158,8 @@ struct fsl_edma_engine {
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int txirq;
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int errirq;
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bool big_endian;
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enum edma_version version;
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struct edma_regs regs;
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struct fsl_edma_chan chans[];
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};
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@ -237,5 +240,6 @@ void fsl_edma_issue_pending(struct dma_chan *chan);
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int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
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void fsl_edma_free_chan_resources(struct dma_chan *chan);
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void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
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void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
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#endif /* _FSL_EDMA_COMMON_H_ */
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@ -28,19 +28,16 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
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{
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struct fsl_edma_engine *fsl_edma = dev_id;
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unsigned int intr, ch;
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void __iomem *base_addr;
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struct edma_regs *regs = &fsl_edma->regs;
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struct fsl_edma_chan *fsl_chan;
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base_addr = fsl_edma->membase;
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intr = edma_readl(fsl_edma, base_addr + EDMA_INTR);
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intr = edma_readl(fsl_edma, regs->intl);
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if (!intr)
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return IRQ_NONE;
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for (ch = 0; ch < fsl_edma->n_chans; ch++) {
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if (intr & (0x1 << ch)) {
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edma_writeb(fsl_edma, EDMA_CINT_CINT(ch),
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base_addr + EDMA_CINT);
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edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
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fsl_chan = &fsl_edma->chans[ch];
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@ -68,16 +65,16 @@ static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
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{
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struct fsl_edma_engine *fsl_edma = dev_id;
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unsigned int err, ch;
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struct edma_regs *regs = &fsl_edma->regs;
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err = edma_readl(fsl_edma, fsl_edma->membase + EDMA_ERR);
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err = edma_readl(fsl_edma, regs->errl);
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if (!err)
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return IRQ_NONE;
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for (ch = 0; ch < fsl_edma->n_chans; ch++) {
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if (err & (0x1 << ch)) {
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fsl_edma_disable_request(&fsl_edma->chans[ch]);
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edma_writeb(fsl_edma, EDMA_CERR_CERR(ch),
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fsl_edma->membase + EDMA_CERR);
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edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
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fsl_edma->chans[ch].status = DMA_ERROR;
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fsl_edma->chans[ch].idle = true;
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}
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@ -192,6 +189,7 @@ static int fsl_edma_probe(struct platform_device *pdev)
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struct device_node *np = pdev->dev.of_node;
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struct fsl_edma_engine *fsl_edma;
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struct fsl_edma_chan *fsl_chan;
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struct edma_regs *regs;
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struct resource *res;
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int len, chans;
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int ret, i;
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@ -207,6 +205,7 @@ static int fsl_edma_probe(struct platform_device *pdev)
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if (!fsl_edma)
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return -ENOMEM;
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fsl_edma->version = v1;
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fsl_edma->n_chans = chans;
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mutex_init(&fsl_edma->fsl_edma_mutex);
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@ -215,6 +214,9 @@ static int fsl_edma_probe(struct platform_device *pdev)
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if (IS_ERR(fsl_edma->membase))
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return PTR_ERR(fsl_edma->membase);
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fsl_edma_setup_regs(fsl_edma);
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regs = &fsl_edma->regs;
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for (i = 0; i < DMAMUX_NR; i++) {
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char clkname[32];
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@ -255,11 +257,11 @@ static int fsl_edma_probe(struct platform_device *pdev)
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fsl_chan->vchan.desc_free = fsl_edma_free_desc;
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vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
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edma_writew(fsl_edma, 0x0, fsl_edma->membase + EDMA_TCD_CSR(i));
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edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
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fsl_edma_chan_mux(fsl_chan, 0, false);
|
||||
}
|
||||
|
||||
edma_writel(fsl_edma, ~0, fsl_edma->membase + EDMA_INTR);
|
||||
edma_writel(fsl_edma, ~0, regs->intl);
|
||||
ret = fsl_edma_irq_init(pdev, fsl_edma);
|
||||
if (ret)
|
||||
return ret;
|
||||
@ -306,7 +308,7 @@ static int fsl_edma_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
/* enable round robin arbitration */
|
||||
edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, fsl_edma->membase + EDMA_CR);
|
||||
edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -353,18 +355,18 @@ static int fsl_edma_resume_early(struct device *dev)
|
||||
{
|
||||
struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
|
||||
struct fsl_edma_chan *fsl_chan;
|
||||
struct edma_regs *regs = &fsl_edma->regs;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < fsl_edma->n_chans; i++) {
|
||||
fsl_chan = &fsl_edma->chans[i];
|
||||
fsl_chan->pm_state = RUNNING;
|
||||
edma_writew(fsl_edma, 0x0, fsl_edma->membase + EDMA_TCD_CSR(i));
|
||||
edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
|
||||
if (fsl_chan->slave_id != 0)
|
||||
fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
|
||||
}
|
||||
|
||||
edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA,
|
||||
fsl_edma->membase + EDMA_CR);
|
||||
edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user