forked from Minki/linux
Amlogic clock driver updates for 4.14
* meson8b: add the reset controller to the clkc * meson: expose all clk ids * gxbb-aoclk: Add CEC 32k clock * gxbb: add mmc input 0 clocks * meson: fix protection against undefined clks * gxbb: fix audio divider flags -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZhJ1CAAoJEHfc29rIyEnRRfkP/3ZFN6URCoh2FGaS39SYHVg8 PuaeCaoDd6/DMuLAWGMlsPtbwqsmqIsA03ZhB8XBzcezfsvc8yGMveTsw8omvJr5 ejXKqeyMxBoRmqrho6+OeMNdkyrHPIkJ9CyTT5PUVlh6jLEnRP2cnsbQYzWRaICN 4BvmkNKZm8yqTkAaneHIzUmcWDDXSq3C43Y3q8622Et2V4h6J74O1KtQLw7o1AAo 0T5mRgAIzo5tJQ4olFfhqOzgcLUbKZmA7jCR7uTaV2Nvde8IHLHpLIStnHCe532s XEjWWgGGS+E2Df3gB3AiHbCgstXZDcdEimt/r//y2+pw2TauuDTcvxIfdfMxMBLI mEDdwFqNG3zXXaIMgYIa7FY7lJl+TQj5d8CgzmpmQGwWkMrL3I6KWywhCPLHlKGu OiwBqRDMq3pJRfhKVDmImanlg+FNsoP0UE+QfGQxW5XGJclWdKo5JTSwh876UsVi ZZGhDwTetPHU1LpEXg0Fvaynecdp1wgLK0ofHFLAUfmhd2FImWGZG1qBwuwhj1iS 1uYB7d+pez91lpU08wNm9dfkSKaXc59ph44j3eEFfJOiRrswkz1rPH7tHCQz7sM4 yUcq2AEmAet6rpqPNikfOZkvItFjk5HcZCMdaOKp30kIdSD22Xzh55ni0Ji1x7Yv ZmvPT65ZU+kWqJjF6Xzo =Ihpj -----END PGP SIGNATURE----- Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into clk-next Pull Amlogic clock driver updates from Neil Armstrong: * meson8b: add the reset controller to the clkc * meson: expose all clk ids * gxbb-aoclk: Add CEC 32k clock * gxbb: add mmc input 0 clocks * meson: fix protection against undefined clks * gxbb: fix audio divider flags * tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson: clk: meson: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb-aoclk: Switch to regmap for register access dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings clk: meson: gxbb: Add sd_emmc clk0 clocks clk: meson: gxbb: fix clk_mclk_i958 divider flags clk: meson: gxbb: fix meson cts_amclk divider flags clk: meson: meson8b: register the built-in reset controller dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb: Add sd_emmc clk0 clkids clk: meson-gxbb: expose almost every clock in the bindings clk: meson8b: expose every clock in the bindings clk: meson: gxbb: fix protection against undefined clks clk: meson: meson8b: fix protection against undefined clks dt-bindings: clock: meson8b: describe the embedded reset controller
This commit is contained in:
Stephen Boyd
commit
3477a72b41
@ -5,9 +5,11 @@ controllers within the Always-On part of the SoC.
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Required Properties:
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- compatible: should be "amlogic,gxbb-aoclkc"
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- reg: physical base address of the clock controller and length of memory
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mapped region.
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- compatible: value should be different for each SoC family as :
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- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
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- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
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- GXM (S912) : "amlogic,meson-gxm-aoclkc"
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followed by the common "amlogic,meson-gx-aoclkc"
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- #clock-cells: should be 1.
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@ -23,14 +25,22 @@ to specify the reset which they consume. All available resets are defined as
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preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
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used in device tree sources.
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Parent node should have the following properties :
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- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
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- reg: base address and size of the AO system control register space.
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Example: AO Clock controller node:
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clkc_AO: clock-controller@040 {
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compatible = "amlogic,gxbb-aoclkc";
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reg = <0x0 0x040 0x0 0x4>;
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ao_sysctrl: sys-ctrl@0 {
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compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
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reg = <0x0 0x0 0x0 0x100>;
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clkc_AO: clock-controller {
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compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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Example: UART controller node that consumes the clock and reset generated
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by the clock controller:
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@ -16,18 +16,25 @@ Required Properties:
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mapped region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
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used in device tree sources.
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Similarly a preprocessor macro for each reset line is defined in
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dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
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device tree sources).
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Example: Clock controller node:
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clkc: clock-controller@c1104000 {
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#clock-cells = <1>;
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compatible = "amlogic,meson8b-clkc";
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reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@ -6,6 +6,7 @@ config COMMON_CLK_AMLOGIC
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config COMMON_CLK_MESON8B
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bool
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depends on COMMON_CLK_AMLOGIC
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select RESET_CONTROLLER
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help
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Support for the clock controller on AmLogic S802 (Meson8),
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S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
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@ -4,4 +4,4 @@
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o
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194
drivers/clk/meson/gxbb-aoclk-32k.c
Normal file
194
drivers/clk/meson/gxbb-aoclk-32k.c
Normal file
@ -0,0 +1,194 @@
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/*
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* Copyright (c) 2017 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/clk-provider.h>
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#include <linux/bitfield.h>
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#include <linux/regmap.h>
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#include "gxbb-aoclk.h"
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/*
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* The AO Domain embeds a dual/divider to generate a more precise
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* 32,768KHz clock for low-power suspend mode and CEC.
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* ______ ______
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* | | | |
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* ______ | Div1 |-| Cnt1 | ______
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* | | /|______| |______|\ | |
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* Xtal-->| Gate |---| ______ ______ X-X--| Gate |-->
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* |______| | \| | | |/ | |______|
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* | | Div2 |-| Cnt2 | |
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* | |______| |______| |
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* |_______________________|
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*
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* The dividing can be switched to single or dual, with a counter
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* for each divider to set when the switching is done.
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* The entire dividing mechanism can be also bypassed.
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*/
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#define CLK_CNTL0_N1_MASK GENMASK(11, 0)
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#define CLK_CNTL0_N2_MASK GENMASK(23, 12)
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#define CLK_CNTL0_DUALDIV_EN BIT(28)
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#define CLK_CNTL0_OUT_GATE_EN BIT(30)
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#define CLK_CNTL0_IN_GATE_EN BIT(31)
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#define CLK_CNTL1_M1_MASK GENMASK(11, 0)
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#define CLK_CNTL1_M2_MASK GENMASK(23, 12)
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#define CLK_CNTL1_BYPASS_EN BIT(24)
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#define CLK_CNTL1_SELECT_OSC BIT(27)
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#define PWR_CNTL_ALT_32K_SEL GENMASK(13, 10)
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struct cec_32k_freq_table {
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unsigned long parent_rate;
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unsigned long target_rate;
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bool dualdiv;
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unsigned int n1;
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unsigned int n2;
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unsigned int m1;
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unsigned int m2;
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};
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static const struct cec_32k_freq_table aoclk_cec_32k_table[] = {
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[0] = {
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.parent_rate = 24000000,
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.target_rate = 32768,
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.dualdiv = true,
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.n1 = 733,
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.n2 = 732,
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.m1 = 8,
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.m2 = 11,
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},
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};
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/*
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* If CLK_CNTL0_DUALDIV_EN == 0
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* - will use N1 divider only
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* If CLK_CNTL0_DUALDIV_EN == 1
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* - hold M1 cycles of N1 divider then changes to N2
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* - hold M2 cycles of N2 divider then changes to N1
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* Then we can get more accurate division.
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*/
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static unsigned long aoclk_cec_32k_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct aoclk_cec_32k *cec_32k = to_aoclk_cec_32k(hw);
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unsigned long n1;
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u32 reg0, reg1;
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regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, ®0);
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regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, ®1);
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if (reg1 & CLK_CNTL1_BYPASS_EN)
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return parent_rate;
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if (reg0 & CLK_CNTL0_DUALDIV_EN) {
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unsigned long n2, m1, m2, f1, f2, p1, p2;
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n1 = FIELD_GET(CLK_CNTL0_N1_MASK, reg0) + 1;
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n2 = FIELD_GET(CLK_CNTL0_N2_MASK, reg0) + 1;
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m1 = FIELD_GET(CLK_CNTL1_M1_MASK, reg1) + 1;
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m2 = FIELD_GET(CLK_CNTL1_M2_MASK, reg1) + 1;
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f1 = DIV_ROUND_CLOSEST(parent_rate, n1);
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f2 = DIV_ROUND_CLOSEST(parent_rate, n2);
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p1 = DIV_ROUND_CLOSEST(100000000 * m1, f1 * (m1 + m2));
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p2 = DIV_ROUND_CLOSEST(100000000 * m2, f2 * (m1 + m2));
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return DIV_ROUND_UP(100000000, p1 + p2);
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}
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n1 = FIELD_GET(CLK_CNTL0_N1_MASK, reg0) + 1;
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return DIV_ROUND_CLOSEST(parent_rate, n1);
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}
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static const struct cec_32k_freq_table *find_cec_32k_freq(unsigned long rate,
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unsigned long prate)
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{
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int i;
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for (i = 0 ; i < ARRAY_SIZE(aoclk_cec_32k_table) ; ++i)
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if (aoclk_cec_32k_table[i].parent_rate == prate &&
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aoclk_cec_32k_table[i].target_rate == rate)
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return &aoclk_cec_32k_table[i];
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return NULL;
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}
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static long aoclk_cec_32k_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
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*prate);
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/* If invalid return first one */
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if (!freq)
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return aoclk_cec_32k_table[0].target_rate;
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return freq->target_rate;
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}
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/*
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* From the Amlogic init procedure, the IN and OUT gates needs to be handled
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* in the init procedure to avoid any glitches.
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*/
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static int aoclk_cec_32k_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
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parent_rate);
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struct aoclk_cec_32k *cec_32k = to_aoclk_cec_32k(hw);
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u32 reg = 0;
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if (!freq)
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return -EINVAL;
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/* Disable clock */
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regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
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CLK_CNTL0_IN_GATE_EN | CLK_CNTL0_OUT_GATE_EN, 0);
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reg = FIELD_PREP(CLK_CNTL0_N1_MASK, freq->n1 - 1);
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if (freq->dualdiv)
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reg |= CLK_CNTL0_DUALDIV_EN |
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FIELD_PREP(CLK_CNTL0_N2_MASK, freq->n2 - 1);
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regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, reg);
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reg = FIELD_PREP(CLK_CNTL1_M1_MASK, freq->m1 - 1);
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if (freq->dualdiv)
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reg |= FIELD_PREP(CLK_CNTL1_M2_MASK, freq->m2 - 1);
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regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, reg);
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/* Enable clock */
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regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
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CLK_CNTL0_IN_GATE_EN, CLK_CNTL0_IN_GATE_EN);
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udelay(200);
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regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
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CLK_CNTL0_OUT_GATE_EN, CLK_CNTL0_OUT_GATE_EN);
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regmap_update_bits(cec_32k->regmap, AO_CRT_CLK_CNTL1,
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CLK_CNTL1_SELECT_OSC, CLK_CNTL1_SELECT_OSC);
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/* Select 32k from XTAL */
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regmap_update_bits(cec_32k->regmap,
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AO_RTI_PWR_CNTL_REG0,
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PWR_CNTL_ALT_32K_SEL,
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FIELD_PREP(PWR_CNTL_ALT_32K_SEL, 4));
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return 0;
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}
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const struct clk_ops meson_aoclk_cec_32k_ops = {
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.recalc_rate = aoclk_cec_32k_recalc_rate,
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.round_rate = aoclk_cec_32k_round_rate,
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.set_rate = aoclk_cec_32k_set_rate,
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};
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46
drivers/clk/meson/gxbb-aoclk-regmap.c
Normal file
46
drivers/clk/meson/gxbb-aoclk-regmap.c
Normal file
@ -0,0 +1,46 @@
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/*
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* Copyright (c) 2017 BayLibre, SAS.
|
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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||||
*
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||||
* SPDX-License-Identifier: GPL-2.0+
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*/
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|
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#include <linux/clk-provider.h>
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#include <linux/bitfield.h>
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#include <linux/regmap.h>
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#include "gxbb-aoclk.h"
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|
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static int aoclk_gate_regmap_enable(struct clk_hw *hw)
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||||
{
|
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struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw);
|
||||
|
||||
return regmap_update_bits(gate->regmap, AO_RTI_GEN_CNTL_REG0,
|
||||
BIT(gate->bit_idx), BIT(gate->bit_idx));
|
||||
}
|
||||
|
||||
static void aoclk_gate_regmap_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw);
|
||||
|
||||
regmap_update_bits(gate->regmap, AO_RTI_GEN_CNTL_REG0,
|
||||
BIT(gate->bit_idx), 0);
|
||||
}
|
||||
|
||||
static int aoclk_gate_regmap_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw);
|
||||
unsigned int val;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(gate->regmap, AO_RTI_GEN_CNTL_REG0, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return (val & BIT(gate->bit_idx)) != 0;
|
||||
}
|
||||
|
||||
const struct clk_ops meson_aoclk_gate_regmap_ops = {
|
||||
.enable = aoclk_gate_regmap_enable,
|
||||
.disable = aoclk_gate_regmap_disable,
|
||||
.is_enabled = aoclk_gate_regmap_is_enabled,
|
||||
};
|
||||
@ -56,16 +56,20 @@
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <dt-bindings/clock/gxbb-aoclkc.h>
|
||||
#include <dt-bindings/reset/gxbb-aoclkc.h>
|
||||
#include "gxbb-aoclk.h"
|
||||
|
||||
static DEFINE_SPINLOCK(gxbb_aoclk_lock);
|
||||
|
||||
struct gxbb_aoclk_reset_controller {
|
||||
struct reset_controller_dev reset;
|
||||
unsigned int *data;
|
||||
void __iomem *base;
|
||||
struct regmap *regmap;
|
||||
};
|
||||
|
||||
static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
|
||||
@ -74,9 +78,8 @@ static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
|
||||
struct gxbb_aoclk_reset_controller *reset =
|
||||
container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
|
||||
|
||||
writel(BIT(reset->data[id]), reset->base);
|
||||
|
||||
return 0;
|
||||
return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
|
||||
BIT(reset->data[id]));
|
||||
}
|
||||
|
||||
static const struct reset_control_ops gxbb_aoclk_reset_ops = {
|
||||
@ -84,13 +87,12 @@ static const struct reset_control_ops gxbb_aoclk_reset_ops = {
|
||||
};
|
||||
|
||||
#define GXBB_AO_GATE(_name, _bit) \
|
||||
static struct clk_gate _name##_ao = { \
|
||||
.reg = (void __iomem *)0, \
|
||||
static struct aoclk_gate_regmap _name##_ao = { \
|
||||
.bit_idx = (_bit), \
|
||||
.lock = &gxbb_aoclk_lock, \
|
||||
.hw.init = &(struct clk_init_data) { \
|
||||
.name = #_name "_ao", \
|
||||
.ops = &clk_gate_ops, \
|
||||
.ops = &meson_aoclk_gate_regmap_ops, \
|
||||
.parent_names = (const char *[]){ "clk81" }, \
|
||||
.num_parents = 1, \
|
||||
.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
|
||||
@ -104,6 +106,17 @@ GXBB_AO_GATE(uart1, 3);
|
||||
GXBB_AO_GATE(uart2, 5);
|
||||
GXBB_AO_GATE(ir_blaster, 6);
|
||||
|
||||
static struct aoclk_cec_32k cec_32k_ao = {
|
||||
.lock = &gxbb_aoclk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cec_32k_ao",
|
||||
.ops = &meson_aoclk_cec_32k_ops,
|
||||
.parent_names = (const char *[]){ "xtal" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned int gxbb_aoclk_reset[] = {
|
||||
[RESET_AO_REMOTE] = 16,
|
||||
[RESET_AO_I2C_MASTER] = 18,
|
||||
@ -113,7 +126,7 @@ static unsigned int gxbb_aoclk_reset[] = {
|
||||
[RESET_AO_IR_BLASTER] = 23,
|
||||
};
|
||||
|
||||
static struct clk_gate *gxbb_aoclk_gate[] = {
|
||||
static struct aoclk_gate_regmap *gxbb_aoclk_gate[] = {
|
||||
[CLKID_AO_REMOTE] = &remote_ao,
|
||||
[CLKID_AO_I2C_MASTER] = &i2c_master_ao,
|
||||
[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao,
|
||||
@ -130,30 +143,30 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
|
||||
[CLKID_AO_UART1] = &uart1_ao.hw,
|
||||
[CLKID_AO_UART2] = &uart2_ao.hw,
|
||||
[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
|
||||
[CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
|
||||
},
|
||||
.num = ARRAY_SIZE(gxbb_aoclk_gate),
|
||||
.num = 7,
|
||||
};
|
||||
|
||||
static int gxbb_aoclkc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
int ret, clkid;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct gxbb_aoclk_reset_controller *rstc;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct regmap *regmap;
|
||||
int ret, clkid;
|
||||
|
||||
rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
|
||||
if (!rstc)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Generic clocks */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
|
||||
if (IS_ERR(regmap)) {
|
||||
dev_err(dev, "failed to get regmap\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Reset Controller */
|
||||
rstc->base = base;
|
||||
rstc->regmap = regmap;
|
||||
rstc->data = gxbb_aoclk_reset;
|
||||
rstc->reset.ops = &gxbb_aoclk_reset_ops;
|
||||
rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
|
||||
@ -161,10 +174,10 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
|
||||
ret = devm_reset_controller_register(dev, &rstc->reset);
|
||||
|
||||
/*
|
||||
* Populate base address and register all clks
|
||||
* Populate regmap and register all clks
|
||||
*/
|
||||
for (clkid = 0; clkid < gxbb_aoclk_onecell_data.num; clkid++) {
|
||||
gxbb_aoclk_gate[clkid]->reg = base;
|
||||
for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
|
||||
gxbb_aoclk_gate[clkid]->regmap = regmap;
|
||||
|
||||
ret = devm_clk_hw_register(dev,
|
||||
gxbb_aoclk_onecell_data.hws[clkid]);
|
||||
@ -172,12 +185,18 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Specific clocks */
|
||||
cec_32k_ao.regmap = regmap;
|
||||
ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
|
||||
&gxbb_aoclk_onecell_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id gxbb_aoclkc_match_table[] = {
|
||||
{ .compatible = "amlogic,gxbb-aoclkc" },
|
||||
{ .compatible = "amlogic,meson-gx-aoclkc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
42
drivers/clk/meson/gxbb-aoclk.h
Normal file
42
drivers/clk/meson/gxbb-aoclk.h
Normal file
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (c) 2017 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __GXBB_AOCLKC_H
|
||||
#define __GXBB_AOCLKC_H
|
||||
|
||||
/* AO Configuration Clock registers offsets */
|
||||
#define AO_RTI_PWR_CNTL_REG1 0x0c
|
||||
#define AO_RTI_PWR_CNTL_REG0 0x10
|
||||
#define AO_RTI_GEN_CNTL_REG0 0x40
|
||||
#define AO_OSCIN_CNTL 0x58
|
||||
#define AO_CRT_CLK_CNTL1 0x68
|
||||
#define AO_RTC_ALT_CLK_CNTL0 0x94
|
||||
#define AO_RTC_ALT_CLK_CNTL1 0x98
|
||||
|
||||
struct aoclk_gate_regmap {
|
||||
struct clk_hw hw;
|
||||
unsigned bit_idx;
|
||||
struct regmap *regmap;
|
||||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_aoclk_gate_regmap(_hw) \
|
||||
container_of(_hw, struct aoclk_gate_regmap, hw)
|
||||
|
||||
extern const struct clk_ops meson_aoclk_gate_regmap_ops;
|
||||
|
||||
struct aoclk_cec_32k {
|
||||
struct clk_hw hw;
|
||||
struct regmap *regmap;
|
||||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_aoclk_cec_32k(_hw) container_of(_hw, struct aoclk_cec_32k, hw)
|
||||
|
||||
extern const struct clk_ops meson_aoclk_cec_32k_ops;
|
||||
|
||||
#endif /* __GXBB_AOCLKC_H */
|
||||
@ -850,13 +850,14 @@ static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
|
||||
.shift = 0,
|
||||
.width = 8,
|
||||
},
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_amclk_div",
|
||||
.ops = &meson_clk_audio_divider_ops,
|
||||
.parent_names = (const char *[]){ "cts_amclk_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
@ -880,7 +881,7 @@ static struct clk_mux gxbb_cts_mclk_i958_sel = {
|
||||
/* Default parent unknown (register reset value: 0) */
|
||||
.table = (u32[]){ 1, 2, 3 },
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cts_mclk_i958_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
|
||||
@ -894,12 +895,13 @@ static struct clk_divider gxbb_cts_mclk_i958_div = {
|
||||
.shift = 16,
|
||||
.width = 8,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cts_mclk_i958_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.parent_names = (const char *[]){ "cts_mclk_i958_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
@ -979,6 +981,156 @@ static struct clk_mux gxbb_32k_clk_sel = {
|
||||
},
|
||||
};
|
||||
|
||||
static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
|
||||
"xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
|
||||
|
||||
/*
|
||||
* Following these parent clocks, we should also have had mpll2, mpll3
|
||||
* and gp0_pll but these clocks are too precious to be used here. All
|
||||
* the necessary rates for MMC and NAND operation can be acheived using
|
||||
* xtal or fclk_div clocks
|
||||
*/
|
||||
};
|
||||
|
||||
/* SDIO clock */
|
||||
static struct clk_mux gxbb_sd_emmc_a_clk0_sel = {
|
||||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 9,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_a_clk0_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
.parent_names = gxbb_sd_emmc_clk0_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
|
||||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_a_clk0_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate gxbb_sd_emmc_a_clk0 = {
|
||||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.bit_idx = 7,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sd_emmc_a_clk0",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
|
||||
.num_parents = 1,
|
||||
|
||||
/*
|
||||
* FIXME:
|
||||
* We need CLK_IGNORE_UNUSED because mmc DT node point to xtal
|
||||
* instead of this clock. CCF would gate this on boot, killing
|
||||
* the mmc controller. Please remove this flag once DT properly
|
||||
* point to this clock instead of xtal
|
||||
*
|
||||
* Same goes for emmc B and C clocks
|
||||
*/
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
/* SDcard clock */
|
||||
static struct clk_mux gxbb_sd_emmc_b_clk0_sel = {
|
||||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 25,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_b_clk0_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
.parent_names = gxbb_sd_emmc_clk0_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
|
||||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_b_clk0_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate gxbb_sd_emmc_b_clk0 = {
|
||||
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
|
||||
.bit_idx = 23,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sd_emmc_b_clk0",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
/* EMMC/NAND clock */
|
||||
static struct clk_mux gxbb_sd_emmc_c_clk0_sel = {
|
||||
.reg = (void *)HHI_NAND_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 9,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_c_clk0_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
.parent_names = gxbb_sd_emmc_clk0_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
|
||||
.reg = (void *)HHI_NAND_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sd_emmc_c_clk0_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate gxbb_sd_emmc_c_clk0 = {
|
||||
.reg = (void *)HHI_NAND_CLK_CNTL,
|
||||
.bit_idx = 7,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sd_emmc_c_clk0",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
/* Everything Else (EE) domain gates */
|
||||
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
|
||||
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
|
||||
@ -1188,6 +1340,16 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
|
||||
[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
|
||||
[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
|
||||
[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
};
|
||||
@ -1310,6 +1472,16 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
|
||||
[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
|
||||
[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
|
||||
[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
};
|
||||
@ -1425,6 +1597,9 @@ static struct clk_gate *const gxbb_clk_gates[] = {
|
||||
&gxbb_cts_amclk,
|
||||
&gxbb_cts_mclk_i958,
|
||||
&gxbb_32k_clk,
|
||||
&gxbb_sd_emmc_a_clk0,
|
||||
&gxbb_sd_emmc_b_clk0,
|
||||
&gxbb_sd_emmc_c_clk0,
|
||||
};
|
||||
|
||||
static struct clk_mux *const gxbb_clk_muxes[] = {
|
||||
@ -1437,6 +1612,9 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
|
||||
&gxbb_cts_mclk_i958_sel,
|
||||
&gxbb_cts_i958,
|
||||
&gxbb_32k_clk_sel,
|
||||
&gxbb_sd_emmc_a_clk0_sel,
|
||||
&gxbb_sd_emmc_b_clk0_sel,
|
||||
&gxbb_sd_emmc_c_clk0_sel,
|
||||
};
|
||||
|
||||
static struct clk_divider *const gxbb_clk_dividers[] = {
|
||||
@ -1446,6 +1624,9 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
|
||||
&gxbb_mali_1_div,
|
||||
&gxbb_cts_mclk_i958_div,
|
||||
&gxbb_32k_clk_div,
|
||||
&gxbb_sd_emmc_a_clk0_div,
|
||||
&gxbb_sd_emmc_b_clk0_div,
|
||||
&gxbb_sd_emmc_c_clk0_div,
|
||||
};
|
||||
|
||||
static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
|
||||
|
||||
@ -167,130 +167,33 @@
|
||||
* CLKID index values
|
||||
*
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
* Migrate them out of this header and into the DT header file when they need
|
||||
* to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
|
||||
* It has now been decided to expose everything by default in the DT header:
|
||||
* include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
|
||||
* to expose, such as the internal muxes and dividers of composite clocks,
|
||||
* will remain defined here.
|
||||
*/
|
||||
#define CLKID_SYS_PLL 0
|
||||
/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
|
||||
/* CLKID_HDMI_PLL */
|
||||
#define CLKID_FIXED_PLL 3
|
||||
/* CLKID_FCLK_DIV2 */
|
||||
/* CLKID_FCLK_DIV3 */
|
||||
/* CLKID_FCLK_DIV4 */
|
||||
#define CLKID_FCLK_DIV5 7
|
||||
#define CLKID_FCLK_DIV7 8
|
||||
/* CLKID_GP0_PLL */
|
||||
#define CLKID_MPEG_SEL 10
|
||||
#define CLKID_MPEG_DIV 11
|
||||
/* CLKID_CLK81 */
|
||||
#define CLKID_MPLL0 13
|
||||
#define CLKID_MPLL1 14
|
||||
/* CLKID_MPLL2 */
|
||||
#define CLKID_DDR 16
|
||||
#define CLKID_DOS 17
|
||||
#define CLKID_ISA 18
|
||||
#define CLKID_PL301 19
|
||||
#define CLKID_PERIPHS 20
|
||||
/* CLKID_SPICC */
|
||||
/* CLKID_I2C */
|
||||
/* #define CLKID_SAR_ADC */
|
||||
#define CLKID_SMART_CARD 24
|
||||
/* CLKID_RNG0 */
|
||||
/* CLKID_UART0 */
|
||||
#define CLKID_SDHC 27
|
||||
#define CLKID_STREAM 28
|
||||
#define CLKID_ASYNC_FIFO 29
|
||||
#define CLKID_SDIO 30
|
||||
#define CLKID_ABUF 31
|
||||
#define CLKID_HIU_IFACE 32
|
||||
#define CLKID_ASSIST_MISC 33
|
||||
/* CLKID_SPI */
|
||||
#define CLKID_I2S_SPDIF 35
|
||||
/* CLKID_ETH */
|
||||
#define CLKID_DEMUX 37
|
||||
/* CLKID_AIU_GLUE */
|
||||
/* CLKID_IEC958 */
|
||||
/* CLKID_I2S_OUT */
|
||||
#define CLKID_AMCLK 41
|
||||
#define CLKID_AIFIFO2 42
|
||||
#define CLKID_MIXER 43
|
||||
/* CLKID_MIXER_IFACE */
|
||||
#define CLKID_ADC 45
|
||||
#define CLKID_BLKMV 46
|
||||
/* CLKID_AIU */
|
||||
/* CLKID_UART1 */
|
||||
#define CLKID_G2D 49
|
||||
/* CLKID_USB0 */
|
||||
/* CLKID_USB1 */
|
||||
#define CLKID_RESET 52
|
||||
#define CLKID_NAND 53
|
||||
#define CLKID_DOS_PARSER 54
|
||||
/* CLKID_USB */
|
||||
#define CLKID_VDIN1 56
|
||||
#define CLKID_AHB_ARB0 57
|
||||
#define CLKID_EFUSE 58
|
||||
#define CLKID_BOOT_ROM 59
|
||||
#define CLKID_AHB_DATA_BUS 60
|
||||
#define CLKID_AHB_CTRL_BUS 61
|
||||
#define CLKID_HDMI_INTR_SYNC 62
|
||||
/* CLKID_HDMI_PCLK */
|
||||
/* CLKID_USB1_DDR_BRIDGE */
|
||||
/* CLKID_USB0_DDR_BRIDGE */
|
||||
#define CLKID_MMC_PCLK 66
|
||||
#define CLKID_DVIN 67
|
||||
/* CLKID_UART2 */
|
||||
/* #define CLKID_SANA */
|
||||
#define CLKID_VPU_INTR 70
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
|
||||
#define CLKID_CLK81_A53 72
|
||||
#define CLKID_VCLK2_VENCI0 73
|
||||
#define CLKID_VCLK2_VENCI1 74
|
||||
#define CLKID_VCLK2_VENCP0 75
|
||||
#define CLKID_VCLK2_VENCP1 76
|
||||
/* CLKID_GCLK_VENCI_INT0 */
|
||||
#define CLKID_GCLK_VENCI_INT 78
|
||||
#define CLKID_DAC_CLK 79
|
||||
/* CLKID_AOCLK_GATE */
|
||||
/* CLKID_IEC958_GATE */
|
||||
#define CLKID_ENC480P 82
|
||||
#define CLKID_RNG1 83
|
||||
#define CLKID_GCLK_VENCI_INT1 84
|
||||
#define CLKID_VCLK2_VENCLMCC 85
|
||||
#define CLKID_VCLK2_VENCL 86
|
||||
#define CLKID_VCLK_OTHER 87
|
||||
#define CLKID_EDP 88
|
||||
#define CLKID_AO_MEDIA_CPU 89
|
||||
#define CLKID_AO_AHB_SRAM 90
|
||||
#define CLKID_AO_AHB_BUS 91
|
||||
#define CLKID_AO_IFACE 92
|
||||
/* CLKID_AO_I2C */
|
||||
/* CLKID_SD_EMMC_A */
|
||||
/* CLKID_SD_EMMC_B */
|
||||
/* CLKID_SD_EMMC_C */
|
||||
/* CLKID_SAR_ADC_CLK */
|
||||
/* CLKID_SAR_ADC_SEL */
|
||||
#define CLKID_SAR_ADC_DIV 99
|
||||
/* CLKID_MALI_0_SEL */
|
||||
#define CLKID_MALI_0_DIV 101
|
||||
/* CLKID_MALI_0 */
|
||||
/* CLKID_MALI_1_SEL */
|
||||
#define CLKID_MALI_1_DIV 104
|
||||
/* CLKID_MALI_1 */
|
||||
/* CLKID_MALI */
|
||||
/* CLKID_CTS_AMCLK */
|
||||
#define CLKID_MALI_0_DIV 101
|
||||
#define CLKID_MALI_1_DIV 104
|
||||
#define CLKID_CTS_AMCLK_SEL 108
|
||||
#define CLKID_CTS_AMCLK_DIV 109
|
||||
/* CLKID_CTS_MCLK_I958 */
|
||||
#define CLKID_CTS_MCLK_I958_SEL 111
|
||||
#define CLKID_CTS_MCLK_I958_DIV 112
|
||||
/* CLKID_CTS_I958 */
|
||||
#define CLKID_32K_CLK 114
|
||||
#define CLKID_32K_CLK_SEL 115
|
||||
#define CLKID_32K_CLK_DIV 116
|
||||
#define CLKID_SD_EMMC_A_CLK0_SEL 117
|
||||
#define CLKID_SD_EMMC_A_CLK0_DIV 118
|
||||
#define CLKID_SD_EMMC_B_CLK0_SEL 120
|
||||
#define CLKID_SD_EMMC_B_CLK0_DIV 121
|
||||
#define CLKID_SD_EMMC_C_CLK0_SEL 123
|
||||
#define CLKID_SD_EMMC_C_CLK0_DIV 124
|
||||
|
||||
#define NR_CLKS 117
|
||||
#define NR_CLKS 126
|
||||
|
||||
/* include the CLKIDs that have been made part of the stable DT binding */
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/gxbb-clkc.h>
|
||||
|
||||
#endif /* __GXBB_H */
|
||||
|
||||
@ -25,6 +25,8 @@
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include "clkc.h"
|
||||
@ -32,6 +34,13 @@
|
||||
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
|
||||
static void __iomem *clk_base;
|
||||
|
||||
struct meson8b_clk_reset {
|
||||
struct reset_controller_dev reset;
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
static const struct pll_rate_table sys_pll_rate_table[] = {
|
||||
PLL_RATE(312000000, 52, 1, 2),
|
||||
PLL_RATE(336000000, 56, 1, 2),
|
||||
@ -590,6 +599,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
||||
[CLKID_MPLL0] = &meson8b_mpll0.hw,
|
||||
[CLKID_MPLL1] = &meson8b_mpll1.hw,
|
||||
[CLKID_MPLL2] = &meson8b_mpll2.hw,
|
||||
[CLK_NR_CLKS] = NULL,
|
||||
},
|
||||
.num = CLK_NR_CLKS,
|
||||
};
|
||||
@ -695,20 +705,114 @@ static struct clk_divider *const meson8b_clk_dividers[] = {
|
||||
&meson8b_mpeg_clk_div,
|
||||
};
|
||||
|
||||
static const struct meson8b_clk_reset_line {
|
||||
u32 reg;
|
||||
u8 bit_idx;
|
||||
} meson8b_clk_reset_bits[] = {
|
||||
[CLKC_RESET_L2_CACHE_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
|
||||
},
|
||||
[CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
|
||||
},
|
||||
[CLKC_RESET_SCU_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
|
||||
},
|
||||
[CLKC_RESET_CPU3_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
|
||||
},
|
||||
[CLKC_RESET_CPU2_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
|
||||
},
|
||||
[CLKC_RESET_CPU1_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
|
||||
},
|
||||
[CLKC_RESET_CPU0_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
|
||||
},
|
||||
[CLKC_RESET_A5_GLOBAL_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
|
||||
},
|
||||
[CLKC_RESET_A5_AXI_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
|
||||
},
|
||||
[CLKC_RESET_A5_ABP_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
|
||||
},
|
||||
[CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
|
||||
},
|
||||
[CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
|
||||
.reg = HHI_VID_CLK_CNTL, .bit_idx = 15
|
||||
},
|
||||
[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
|
||||
.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
|
||||
},
|
||||
[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
|
||||
.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
|
||||
},
|
||||
[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
|
||||
.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
|
||||
},
|
||||
[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
|
||||
.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
|
||||
},
|
||||
};
|
||||
|
||||
static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool assert)
|
||||
{
|
||||
struct meson8b_clk_reset *meson8b_clk_reset =
|
||||
container_of(rcdev, struct meson8b_clk_reset, reset);
|
||||
unsigned long flags;
|
||||
const struct meson8b_clk_reset_line *reset;
|
||||
u32 val;
|
||||
|
||||
if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
|
||||
return -EINVAL;
|
||||
|
||||
reset = &meson8b_clk_reset_bits[id];
|
||||
|
||||
spin_lock_irqsave(&clk_lock, flags);
|
||||
|
||||
val = readl(meson8b_clk_reset->base + reset->reg);
|
||||
if (assert)
|
||||
val |= BIT(reset->bit_idx);
|
||||
else
|
||||
val &= ~BIT(reset->bit_idx);
|
||||
writel(val, meson8b_clk_reset->base + reset->reg);
|
||||
|
||||
spin_unlock_irqrestore(&clk_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return meson8b_clk_reset_update(rcdev, id, true);
|
||||
}
|
||||
|
||||
static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return meson8b_clk_reset_update(rcdev, id, false);
|
||||
}
|
||||
|
||||
static const struct reset_control_ops meson8b_clk_reset_ops = {
|
||||
.assert = meson8b_clk_reset_assert,
|
||||
.deassert = meson8b_clk_reset_deassert,
|
||||
};
|
||||
|
||||
static int meson8b_clkc_probe(struct platform_device *pdev)
|
||||
{
|
||||
void __iomem *clk_base;
|
||||
int ret, clkid, i;
|
||||
struct clk_hw *parent_hw;
|
||||
struct clk *parent_clk;
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
/* Generic clocks and PLLs */
|
||||
clk_base = of_iomap(dev->of_node, 1);
|
||||
if (!clk_base) {
|
||||
pr_err("%s: Unable to map clk base\n", __func__);
|
||||
if (!clk_base)
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
/* Populate base address for PLLs */
|
||||
for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
|
||||
@ -748,7 +852,7 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
|
||||
/* FIXME convert to devm_clk_register */
|
||||
ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
|
||||
if (ret)
|
||||
goto iounmap;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -771,15 +875,11 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
|
||||
if (ret) {
|
||||
pr_err("%s: failed to register clock notifier for cpu_clk\n",
|
||||
__func__);
|
||||
goto iounmap;
|
||||
return ret;
|
||||
}
|
||||
|
||||
return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
|
||||
&meson8b_hw_onecell_data);
|
||||
|
||||
iounmap:
|
||||
iounmap(clk_base);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id meson8b_clkc_match_table[] = {
|
||||
@ -798,3 +898,39 @@ static struct platform_driver meson8b_driver = {
|
||||
};
|
||||
|
||||
builtin_platform_driver(meson8b_driver);
|
||||
|
||||
static void __init meson8b_clkc_reset_init(struct device_node *np)
|
||||
{
|
||||
struct meson8b_clk_reset *rstc;
|
||||
int ret;
|
||||
|
||||
/* Generic clocks, PLLs and some of the reset-bits */
|
||||
clk_base = of_iomap(np, 1);
|
||||
if (!clk_base) {
|
||||
pr_err("%s: Unable to map clk base\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
|
||||
if (!rstc)
|
||||
return;
|
||||
|
||||
/* Reset Controller */
|
||||
rstc->base = clk_base;
|
||||
rstc->reset.ops = &meson8b_clk_reset_ops;
|
||||
rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
|
||||
rstc->reset.of_node = np;
|
||||
ret = reset_controller_register(&rstc->reset);
|
||||
if (ret) {
|
||||
pr_err("%s: Failed to register clkc reset controller: %d\n",
|
||||
__func__, ret);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
|
||||
meson8b_clkc_reset_init);
|
||||
CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
|
||||
meson8b_clkc_reset_init);
|
||||
CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
|
||||
meson8b_clkc_reset_init);
|
||||
|
||||
@ -37,6 +37,9 @@
|
||||
#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
|
||||
#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
|
||||
#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
|
||||
#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
|
||||
#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
|
||||
#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
|
||||
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
|
||||
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
|
||||
#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
|
||||
@ -60,110 +63,19 @@
|
||||
* CLKID index values
|
||||
*
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
* Migrate them out of this header and into the DT header file when they need
|
||||
* to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h
|
||||
* It has now been decided to expose everything by default in the DT header:
|
||||
* include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
|
||||
* to expose, such as the internal muxes and dividers of composite clocks,
|
||||
* will remain defined here.
|
||||
*/
|
||||
|
||||
/* CLKID_UNUSED */
|
||||
/* CLKID_XTAL */
|
||||
/* CLKID_PLL_FIXED */
|
||||
/* CLKID_PLL_VID */
|
||||
/* CLKID_PLL_SYS */
|
||||
/* CLKID_FCLK_DIV2 */
|
||||
/* CLKID_FCLK_DIV3 */
|
||||
/* CLKID_FCLK_DIV4 */
|
||||
/* CLKID_FCLK_DIV5 */
|
||||
/* CLKID_FCLK_DIV7 */
|
||||
/* CLKID_CLK81 */
|
||||
/* CLKID_MALI */
|
||||
/* CLKID_CPUCLK */
|
||||
/* CLKID_ZERO */
|
||||
/* CLKID_MPEG_SEL */
|
||||
/* CLKID_MPEG_DIV */
|
||||
#define CLKID_DDR 16
|
||||
#define CLKID_DOS 17
|
||||
#define CLKID_ISA 18
|
||||
#define CLKID_PL301 19
|
||||
#define CLKID_PERIPHS 20
|
||||
#define CLKID_SPICC 21
|
||||
#define CLKID_I2C 22
|
||||
/* #define CLKID_SAR_ADC */
|
||||
#define CLKID_SMART_CARD 24
|
||||
/* #define CLKID_RNG0 */
|
||||
#define CLKID_UART0 26
|
||||
#define CLKID_SDHC 27
|
||||
#define CLKID_STREAM 28
|
||||
#define CLKID_ASYNC_FIFO 29
|
||||
/* #define CLKID_SDIO */
|
||||
#define CLKID_ABUF 31
|
||||
#define CLKID_HIU_IFACE 32
|
||||
#define CLKID_ASSIST_MISC 33
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_I2S_SPDIF 35
|
||||
/* #define CLKID_ETH */
|
||||
#define CLKID_DEMUX 37
|
||||
#define CLKID_AIU_GLUE 38
|
||||
#define CLKID_IEC958 39
|
||||
#define CLKID_I2S_OUT 40
|
||||
#define CLKID_AMCLK 41
|
||||
#define CLKID_AIFIFO2 42
|
||||
#define CLKID_MIXER 43
|
||||
#define CLKID_MIXER_IFACE 44
|
||||
#define CLKID_ADC 45
|
||||
#define CLKID_BLKMV 46
|
||||
#define CLKID_AIU 47
|
||||
#define CLKID_UART1 48
|
||||
#define CLKID_G2D 49
|
||||
/* #define CLKID_USB0 */
|
||||
/* #define CLKID_USB1 */
|
||||
#define CLKID_RESET 52
|
||||
#define CLKID_NAND 53
|
||||
#define CLKID_DOS_PARSER 54
|
||||
/* #define CLKID_USB */
|
||||
#define CLKID_VDIN1 56
|
||||
#define CLKID_AHB_ARB0 57
|
||||
#define CLKID_EFUSE 58
|
||||
#define CLKID_BOOT_ROM 59
|
||||
#define CLKID_AHB_DATA_BUS 60
|
||||
#define CLKID_AHB_CTRL_BUS 61
|
||||
#define CLKID_HDMI_INTR_SYNC 62
|
||||
#define CLKID_HDMI_PCLK 63
|
||||
/* CLKID_USB1_DDR_BRIDGE */
|
||||
/* CLKID_USB0_DDR_BRIDGE */
|
||||
#define CLKID_MMC_PCLK 66
|
||||
#define CLKID_DVIN 67
|
||||
#define CLKID_UART2 68
|
||||
/* #define CLKID_SANA */
|
||||
#define CLKID_VPU_INTR 70
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
|
||||
#define CLKID_CLK81_A9 72
|
||||
#define CLKID_VCLK2_VENCI0 73
|
||||
#define CLKID_VCLK2_VENCI1 74
|
||||
#define CLKID_VCLK2_VENCP0 75
|
||||
#define CLKID_VCLK2_VENCP1 76
|
||||
#define CLKID_GCLK_VENCI_INT 77
|
||||
#define CLKID_GCLK_VENCP_INT 78
|
||||
#define CLKID_DAC_CLK 79
|
||||
#define CLKID_AOCLK_GATE 80
|
||||
#define CLKID_IEC958_GATE 81
|
||||
#define CLKID_ENC480P 82
|
||||
#define CLKID_RNG1 83
|
||||
#define CLKID_GCLK_VENCL_INT 84
|
||||
#define CLKID_VCLK2_VENCLMCC 85
|
||||
#define CLKID_VCLK2_VENCL 86
|
||||
#define CLKID_VCLK2_OTHER 87
|
||||
#define CLKID_EDP 88
|
||||
#define CLKID_AO_MEDIA_CPU 89
|
||||
#define CLKID_AO_AHB_SRAM 90
|
||||
#define CLKID_AO_AHB_BUS 91
|
||||
#define CLKID_AO_IFACE 92
|
||||
#define CLKID_MPLL0 93
|
||||
#define CLKID_MPLL1 94
|
||||
#define CLKID_MPLL2 95
|
||||
|
||||
#define CLK_NR_CLKS 96
|
||||
|
||||
/* include the CLKIDs that have been made part of the stable DT binding */
|
||||
/*
|
||||
* include the CLKID and RESETID that have
|
||||
* been made part of the stable DT binding
|
||||
*/
|
||||
#include <dt-bindings/clock/meson8b-clkc.h>
|
||||
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
|
||||
|
||||
#endif /* __MESON8B_H */
|
||||
|
||||
@ -62,5 +62,6 @@
|
||||
#define CLKID_AO_UART1 3
|
||||
#define CLKID_AO_UART2 4
|
||||
#define CLKID_AO_IR_BLASTER 5
|
||||
#define CLKID_AO_CEC_32K 6
|
||||
|
||||
#endif
|
||||
|
||||
@ -5,37 +5,96 @@
|
||||
#ifndef __GXBB_CLKC_H
|
||||
#define __GXBB_CLKC_H
|
||||
|
||||
#define CLKID_SYS_PLL 0
|
||||
#define CLKID_HDMI_PLL 2
|
||||
#define CLKID_FIXED_PLL 3
|
||||
#define CLKID_FCLK_DIV2 4
|
||||
#define CLKID_FCLK_DIV3 5
|
||||
#define CLKID_FCLK_DIV4 6
|
||||
#define CLKID_FCLK_DIV5 7
|
||||
#define CLKID_FCLK_DIV7 8
|
||||
#define CLKID_GP0_PLL 9
|
||||
#define CLKID_CLK81 12
|
||||
#define CLKID_MPLL0 13
|
||||
#define CLKID_MPLL1 14
|
||||
#define CLKID_MPLL2 15
|
||||
#define CLKID_DDR 16
|
||||
#define CLKID_DOS 17
|
||||
#define CLKID_ISA 18
|
||||
#define CLKID_PL301 19
|
||||
#define CLKID_PERIPHS 20
|
||||
#define CLKID_SPICC 21
|
||||
#define CLKID_I2C 22
|
||||
#define CLKID_SAR_ADC 23
|
||||
#define CLKID_SMART_CARD 24
|
||||
#define CLKID_RNG0 25
|
||||
#define CLKID_UART0 26
|
||||
#define CLKID_SDHC 27
|
||||
#define CLKID_STREAM 28
|
||||
#define CLKID_ASYNC_FIFO 29
|
||||
#define CLKID_SDIO 30
|
||||
#define CLKID_ABUF 31
|
||||
#define CLKID_HIU_IFACE 32
|
||||
#define CLKID_ASSIST_MISC 33
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_I2S_SPDIF 35
|
||||
#define CLKID_DEMUX 37
|
||||
#define CLKID_AIU_GLUE 38
|
||||
#define CLKID_IEC958 39
|
||||
#define CLKID_I2S_OUT 40
|
||||
#define CLKID_AMCLK 41
|
||||
#define CLKID_AIFIFO2 42
|
||||
#define CLKID_MIXER 43
|
||||
#define CLKID_MIXER_IFACE 44
|
||||
#define CLKID_ADC 45
|
||||
#define CLKID_BLKMV 46
|
||||
#define CLKID_AIU 47
|
||||
#define CLKID_UART1 48
|
||||
#define CLKID_G2D 49
|
||||
#define CLKID_USB0 50
|
||||
#define CLKID_USB1 51
|
||||
#define CLKID_RESET 52
|
||||
#define CLKID_NAND 53
|
||||
#define CLKID_DOS_PARSER 54
|
||||
#define CLKID_USB 55
|
||||
#define CLKID_VDIN1 56
|
||||
#define CLKID_AHB_ARB0 57
|
||||
#define CLKID_EFUSE 58
|
||||
#define CLKID_BOOT_ROM 59
|
||||
#define CLKID_AHB_DATA_BUS 60
|
||||
#define CLKID_AHB_CTRL_BUS 61
|
||||
#define CLKID_HDMI_INTR_SYNC 62
|
||||
#define CLKID_HDMI_PCLK 63
|
||||
#define CLKID_USB1_DDR_BRIDGE 64
|
||||
#define CLKID_USB0_DDR_BRIDGE 65
|
||||
#define CLKID_MMC_PCLK 66
|
||||
#define CLKID_DVIN 67
|
||||
#define CLKID_UART2 68
|
||||
#define CLKID_SANA 69
|
||||
#define CLKID_VPU_INTR 70
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
|
||||
#define CLKID_CLK81_A53 72
|
||||
#define CLKID_VCLK2_VENCI0 73
|
||||
#define CLKID_VCLK2_VENCI1 74
|
||||
#define CLKID_VCLK2_VENCP0 75
|
||||
#define CLKID_VCLK2_VENCP1 76
|
||||
#define CLKID_GCLK_VENCI_INT0 77
|
||||
#define CLKID_GCLK_VENCI_INT 78
|
||||
#define CLKID_DAC_CLK 79
|
||||
#define CLKID_AOCLK_GATE 80
|
||||
#define CLKID_IEC958_GATE 81
|
||||
#define CLKID_ENC480P 82
|
||||
#define CLKID_RNG1 83
|
||||
#define CLKID_GCLK_VENCI_INT1 84
|
||||
#define CLKID_VCLK2_VENCLMCC 85
|
||||
#define CLKID_VCLK2_VENCL 86
|
||||
#define CLKID_VCLK_OTHER 87
|
||||
#define CLKID_EDP 88
|
||||
#define CLKID_AO_MEDIA_CPU 89
|
||||
#define CLKID_AO_AHB_SRAM 90
|
||||
#define CLKID_AO_AHB_BUS 91
|
||||
#define CLKID_AO_IFACE 92
|
||||
#define CLKID_AO_I2C 93
|
||||
#define CLKID_SD_EMMC_A 94
|
||||
#define CLKID_SD_EMMC_B 95
|
||||
@ -50,5 +109,9 @@
|
||||
#define CLKID_CTS_AMCLK 107
|
||||
#define CLKID_CTS_MCLK_I958 110
|
||||
#define CLKID_CTS_I958 113
|
||||
#define CLKID_32K_CLK 114
|
||||
#define CLKID_SD_EMMC_A_CLK0 119
|
||||
#define CLKID_SD_EMMC_B_CLK0 122
|
||||
#define CLKID_SD_EMMC_C_CLK0 125
|
||||
|
||||
#endif /* __GXBB_CLKC_H */
|
||||
|
||||
@ -21,15 +21,85 @@
|
||||
#define CLKID_ZERO 13
|
||||
#define CLKID_MPEG_SEL 14
|
||||
#define CLKID_MPEG_DIV 15
|
||||
#define CLKID_DDR 16
|
||||
#define CLKID_DOS 17
|
||||
#define CLKID_ISA 18
|
||||
#define CLKID_PL301 19
|
||||
#define CLKID_PERIPHS 20
|
||||
#define CLKID_SPICC 21
|
||||
#define CLKID_I2C 22
|
||||
#define CLKID_SAR_ADC 23
|
||||
#define CLKID_SMART_CARD 24
|
||||
#define CLKID_RNG0 25
|
||||
#define CLKID_UART0 26
|
||||
#define CLKID_SDHC 27
|
||||
#define CLKID_STREAM 28
|
||||
#define CLKID_ASYNC_FIFO 29
|
||||
#define CLKID_SDIO 30
|
||||
#define CLKID_ABUF 31
|
||||
#define CLKID_HIU_IFACE 32
|
||||
#define CLKID_ASSIST_MISC 33
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_I2S_SPDIF 35
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_DEMUX 37
|
||||
#define CLKID_AIU_GLUE 38
|
||||
#define CLKID_IEC958 39
|
||||
#define CLKID_I2S_OUT 40
|
||||
#define CLKID_AMCLK 41
|
||||
#define CLKID_AIFIFO2 42
|
||||
#define CLKID_MIXER 43
|
||||
#define CLKID_MIXER_IFACE 44
|
||||
#define CLKID_ADC 45
|
||||
#define CLKID_BLKMV 46
|
||||
#define CLKID_AIU 47
|
||||
#define CLKID_UART1 48
|
||||
#define CLKID_G2D 49
|
||||
#define CLKID_USB0 50
|
||||
#define CLKID_USB1 51
|
||||
#define CLKID_RESET 52
|
||||
#define CLKID_NAND 53
|
||||
#define CLKID_DOS_PARSER 54
|
||||
#define CLKID_USB 55
|
||||
#define CLKID_VDIN1 56
|
||||
#define CLKID_AHB_ARB0 57
|
||||
#define CLKID_EFUSE 58
|
||||
#define CLKID_BOOT_ROM 59
|
||||
#define CLKID_AHB_DATA_BUS 60
|
||||
#define CLKID_AHB_CTRL_BUS 61
|
||||
#define CLKID_HDMI_INTR_SYNC 62
|
||||
#define CLKID_HDMI_PCLK 63
|
||||
#define CLKID_USB1_DDR_BRIDGE 64
|
||||
#define CLKID_USB0_DDR_BRIDGE 65
|
||||
#define CLKID_MMC_PCLK 66
|
||||
#define CLKID_DVIN 67
|
||||
#define CLKID_UART2 68
|
||||
#define CLKID_SANA 69
|
||||
#define CLKID_VPU_INTR 70
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
|
||||
#define CLKID_CLK81_A9 72
|
||||
#define CLKID_VCLK2_VENCI0 73
|
||||
#define CLKID_VCLK2_VENCI1 74
|
||||
#define CLKID_VCLK2_VENCP0 75
|
||||
#define CLKID_VCLK2_VENCP1 76
|
||||
#define CLKID_GCLK_VENCI_INT 77
|
||||
#define CLKID_GCLK_VENCP_INT 78
|
||||
#define CLKID_DAC_CLK 79
|
||||
#define CLKID_AOCLK_GATE 80
|
||||
#define CLKID_IEC958_GATE 81
|
||||
#define CLKID_ENC480P 82
|
||||
#define CLKID_RNG1 83
|
||||
#define CLKID_GCLK_VENCL_INT 84
|
||||
#define CLKID_VCLK2_VENCLMCC 85
|
||||
#define CLKID_VCLK2_VENCL 86
|
||||
#define CLKID_VCLK2_OTHER 87
|
||||
#define CLKID_EDP 88
|
||||
#define CLKID_AO_MEDIA_CPU 89
|
||||
#define CLKID_AO_AHB_SRAM 90
|
||||
#define CLKID_AO_AHB_BUS 91
|
||||
#define CLKID_AO_IFACE 92
|
||||
#define CLKID_MPLL0 93
|
||||
#define CLKID_MPLL1 94
|
||||
#define CLKID_MPLL2 95
|
||||
|
||||
#endif /* __MESON8B_CLKC_H */
|
||||
|
||||
27
include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
Normal file
27
include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
|
||||
#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
|
||||
|
||||
#define CLKC_RESET_L2_CACHE_SOFT_RESET 0
|
||||
#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET 1
|
||||
#define CLKC_RESET_SCU_SOFT_RESET 2
|
||||
#define CLKC_RESET_CPU0_SOFT_RESET 3
|
||||
#define CLKC_RESET_CPU1_SOFT_RESET 4
|
||||
#define CLKC_RESET_CPU2_SOFT_RESET 5
|
||||
#define CLKC_RESET_CPU3_SOFT_RESET 6
|
||||
#define CLKC_RESET_A5_GLOBAL_RESET 7
|
||||
#define CLKC_RESET_A5_AXI_SOFT_RESET 8
|
||||
#define CLKC_RESET_A5_ABP_SOFT_RESET 9
|
||||
#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET 10
|
||||
#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET 11
|
||||
#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST 12
|
||||
#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE 13
|
||||
#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST 14
|
||||
#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE 15
|
||||
|
||||
#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */
|
||||
Loading…
Reference in New Issue
Block a user