[CPUFREQ] Lots of whitespace & CodingStyle cleanup.
Signed-off-by: Dave Jones <davej@redhat.com>
This commit is contained in:
Dave Jones
parent
8ad5496d23
commit
32ee8c3e47
@ -96,7 +96,6 @@ config X86_POWERNOW_K8_ACPI
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config X86_GX_SUSPMOD
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tristate "Cyrix MediaGX/NatSemi Geode Suspend Modulation"
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depends on PCI
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help
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This add the CPUFreq driver for NatSemi Geode processors which
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support suspend modulation.
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@ -57,7 +57,7 @@ MODULE_PARM_DESC(min_fsb,
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#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)
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/*
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/**
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* nforce2_calc_fsb - calculate FSB
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* @pll: PLL value
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*
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@ -76,7 +76,7 @@ static int nforce2_calc_fsb(int pll)
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return 0;
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}
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/*
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/**
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* nforce2_calc_pll - calculate PLL value
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* @fsb: FSB
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*
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@ -106,7 +106,7 @@ static int nforce2_calc_pll(unsigned int fsb)
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return NFORCE2_PLL(mul, div);
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}
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/*
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/**
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* nforce2_write_pll - write PLL value to chipset
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* @pll: PLL value
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*
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@ -121,15 +121,13 @@ static void nforce2_write_pll(int pll)
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pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);
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/* Now write the value in all 64 registers */
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for (temp = 0; temp <= 0x3f; temp++) {
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pci_write_config_dword(nforce2_chipset_dev,
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NFORCE2_PLLREG, pll);
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}
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for (temp = 0; temp <= 0x3f; temp++)
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pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLREG, pll);
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return;
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}
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/*
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/**
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* nforce2_fsb_read - Read FSB
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*
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* Read FSB from chipset
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@ -140,14 +138,9 @@ static unsigned int nforce2_fsb_read(int bootfsb)
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struct pci_dev *nforce2_sub5;
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u32 fsb, temp = 0;
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/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
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nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
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0x01EF,
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PCI_ANY_ID,
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PCI_ANY_ID,
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NULL);
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0x01EF,PCI_ANY_ID,PCI_ANY_ID,NULL);
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if (!nforce2_sub5)
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return 0;
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@ -155,21 +148,19 @@ static unsigned int nforce2_fsb_read(int bootfsb)
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fsb /= 1000000;
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/* Check if PLL register is already set */
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pci_read_config_byte(nforce2_chipset_dev,
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NFORCE2_PLLENABLE, (u8 *)&temp);
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pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
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if(bootfsb || !temp)
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return fsb;
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/* Use PLL register FSB value */
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pci_read_config_dword(nforce2_chipset_dev,
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NFORCE2_PLLREG, &temp);
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pci_read_config_dword(nforce2_chipset_dev,NFORCE2_PLLREG, &temp);
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fsb = nforce2_calc_fsb(temp);
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return fsb;
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}
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/*
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/**
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* nforce2_set_fsb - set new FSB
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* @fsb: New FSB
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*
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@ -194,8 +185,7 @@ static int nforce2_set_fsb(unsigned int fsb)
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}
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/* First write? Then set actual value */
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pci_read_config_byte(nforce2_chipset_dev,
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NFORCE2_PLLENABLE, (u8 *)&temp);
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pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
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if (!temp) {
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pll = nforce2_calc_pll(tfsb);
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@ -405,10 +395,8 @@ static unsigned int nforce2_detect_chipset(void)
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u8 revision;
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nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
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PCI_DEVICE_ID_NVIDIA_NFORCE2,
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PCI_ANY_ID,
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PCI_ANY_ID,
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NULL);
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PCI_DEVICE_ID_NVIDIA_NFORCE2,
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PCI_ANY_ID, PCI_ANY_ID, NULL);
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if (nforce2_chipset_dev == NULL)
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return -ENODEV;
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@ -1,5 +1,5 @@
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/*
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* elanfreq: cpufreq driver for the AMD ELAN family
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* elanfreq: cpufreq driver for the AMD ELAN family
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*
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* (c) Copyright 2002 Robert Schwebel <r.schwebel@pengutronix.de>
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*
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@ -28,7 +28,7 @@
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#include <asm/timex.h>
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#include <asm/io.h>
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#define REG_CSCIR 0x22 /* Chip Setup and Control Index Register */
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#define REG_CSCIR 0x22 /* Chip Setup and Control Index Register */
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#define REG_CSCDR 0x23 /* Chip Setup and Control Data Register */
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/* Module parameter */
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@ -79,46 +79,46 @@ static struct cpufreq_frequency_table elanfreq_table[] = {
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static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu)
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{
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u8 clockspeed_reg; /* Clock Speed Register */
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u8 clockspeed_reg; /* Clock Speed Register */
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local_irq_disable();
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outb_p(0x80,REG_CSCIR);
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clockspeed_reg = inb_p(REG_CSCDR);
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outb_p(0x80,REG_CSCIR);
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clockspeed_reg = inb_p(REG_CSCDR);
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local_irq_enable();
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if ((clockspeed_reg & 0xE0) == 0xE0) { return 0; }
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if ((clockspeed_reg & 0xE0) == 0xE0)
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return 0;
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/* Are we in CPU clock multiplied mode (66/99 MHz)? */
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if ((clockspeed_reg & 0xE0) == 0xC0) {
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if ((clockspeed_reg & 0x01) == 0) {
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/* Are we in CPU clock multiplied mode (66/99 MHz)? */
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if ((clockspeed_reg & 0xE0) == 0xC0) {
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if ((clockspeed_reg & 0x01) == 0)
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return 66000;
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} else {
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else
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return 99000;
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}
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}
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}
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/* 33 MHz is not 32 MHz... */
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if ((clockspeed_reg & 0xE0)==0xA0)
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return 33000;
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return ((1<<((clockspeed_reg & 0xE0) >> 5)) * 1000);
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return ((1<<((clockspeed_reg & 0xE0) >> 5)) * 1000);
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}
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/**
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* elanfreq_set_cpu_frequency: Change the CPU core frequency
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* @cpu: cpu number
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* elanfreq_set_cpu_frequency: Change the CPU core frequency
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* @cpu: cpu number
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* @freq: frequency in kHz
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*
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* This function takes a frequency value and changes the CPU frequency
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* This function takes a frequency value and changes the CPU frequency
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* according to this. Note that the frequency has to be checked by
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* elanfreq_validatespeed() for correctness!
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*
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* There is no return value.
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*/
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static void elanfreq_set_cpu_state (unsigned int state) {
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static void elanfreq_set_cpu_state (unsigned int state)
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{
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struct cpufreq_freqs freqs;
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freqs.old = elanfreq_get_cpu_frequency(0);
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@ -127,7 +127,8 @@ static void elanfreq_set_cpu_state (unsigned int state) {
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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printk(KERN_INFO "elanfreq: attempting to set frequency to %i kHz\n",elan_multiplier[state].clock);
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printk(KERN_INFO "elanfreq: attempting to set frequency to %i kHz\n",
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elan_multiplier[state].clock);
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/*
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@ -143,7 +144,7 @@ static void elanfreq_set_cpu_state (unsigned int state) {
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*/
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local_irq_disable();
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outb_p(0x40,REG_CSCIR); /* Disable hyperspeed mode */
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outb_p(0x40,REG_CSCIR); /* Disable hyperspeed mode */
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outb_p(0x00,REG_CSCDR);
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local_irq_enable(); /* wait till internal pipelines and */
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udelay(1000); /* buffers have cleaned up */
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@ -166,10 +167,10 @@ static void elanfreq_set_cpu_state (unsigned int state) {
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/**
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* elanfreq_validatespeed: test if frequency range is valid
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* @policy: the policy to validate
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* @policy: the policy to validate
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*
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* This function checks if a given frequency range in kHz is valid
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* for the hardware supported by the driver.
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* for the hardware supported by the driver.
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*/
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static int elanfreq_verify (struct cpufreq_policy *policy)
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@ -181,7 +182,7 @@ static int elanfreq_target (struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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unsigned int newstate = 0;
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unsigned int newstate = 0;
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if (cpufreq_frequency_table_target(policy, &elanfreq_table[0], target_freq, relation, &newstate))
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return -EINVAL;
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@ -212,7 +213,7 @@ static int elanfreq_cpu_init(struct cpufreq_policy *policy)
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max_freq = elanfreq_get_cpu_frequency(0);
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/* table init */
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for (i=0; (elanfreq_table[i].frequency != CPUFREQ_TABLE_END); i++) {
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for (i=0; (elanfreq_table[i].frequency != CPUFREQ_TABLE_END); i++) {
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if (elanfreq_table[i].frequency > max_freq)
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elanfreq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
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}
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@ -226,8 +227,7 @@ static int elanfreq_cpu_init(struct cpufreq_policy *policy)
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if (result)
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return (result);
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cpufreq_frequency_table_get_attr(elanfreq_table, policy->cpu);
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cpufreq_frequency_table_get_attr(elanfreq_table, policy->cpu);
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return 0;
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}
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@ -268,9 +268,9 @@ static struct freq_attr* elanfreq_attr[] = {
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static struct cpufreq_driver elanfreq_driver = {
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.get = elanfreq_get_cpu_frequency,
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.verify = elanfreq_verify,
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.target = elanfreq_target,
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.get = elanfreq_get_cpu_frequency,
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.verify = elanfreq_verify,
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.target = elanfreq_target,
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.init = elanfreq_cpu_init,
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.exit = elanfreq_cpu_exit,
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.name = "elanfreq",
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@ -285,12 +285,10 @@ static int __init elanfreq_init(void)
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/* Test if we have the right hardware */
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if ((c->x86_vendor != X86_VENDOR_AMD) ||
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(c->x86 != 4) || (c->x86_model!=10))
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{
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(c->x86 != 4) || (c->x86_model!=10)) {
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printk(KERN_INFO "elanfreq: error: no Elan processor found!\n");
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return -ENODEV;
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}
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return cpufreq_register_driver(&elanfreq_driver);
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}
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@ -309,4 +307,3 @@ MODULE_DESCRIPTION("cpufreq driver for AMD's Elan CPUs");
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module_init(elanfreq_init);
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module_exit(elanfreq_exit);
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@ -32,7 +32,7 @@
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* to the processor.
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*
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* These counters define a ratio which is the effective frequency
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* of operation of the system.
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* of operation of the system.
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*
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* OFF Count
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* F_eff = Fgx * ----------------------
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@ -52,11 +52,11 @@
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*---------------------------------------------------------------------------
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*
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* ChangeLog:
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* Dec. 12, 2003 Hiroshi Miura <miura@da-cha.org>
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* - fix on/off register mistake
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* - fix cpu_khz calc when it stops cpu modulation.
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* Dec. 12, 2003 Hiroshi Miura <miura@da-cha.org>
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* - fix on/off register mistake
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* - fix cpu_khz calc when it stops cpu modulation.
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*
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* Dec. 11, 2002 Hiroshi Miura <miura@da-cha.org>
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* Dec. 11, 2002 Hiroshi Miura <miura@da-cha.org>
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* - rewrite for Cyrix MediaGX Cx5510/5520 and
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* NatSemi Geode Cs5530(A).
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*
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@ -83,31 +83,31 @@
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#include <asm/errno.h>
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/* PCI config registers, all at F0 */
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#define PCI_PMER1 0x80 /* power management enable register 1 */
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#define PCI_PMER2 0x81 /* power management enable register 2 */
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#define PCI_PMER3 0x82 /* power management enable register 3 */
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#define PCI_IRQTC 0x8c /* irq speedup timer counter register:typical 2 to 4ms */
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#define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */
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#define PCI_MODOFF 0x94 /* suspend modulation OFF counter register, 1 = 32us */
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#define PCI_MODON 0x95 /* suspend modulation ON counter register */
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#define PCI_SUSCFG 0x96 /* suspend configuration register */
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#define PCI_PMER1 0x80 /* power management enable register 1 */
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#define PCI_PMER2 0x81 /* power management enable register 2 */
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#define PCI_PMER3 0x82 /* power management enable register 3 */
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#define PCI_IRQTC 0x8c /* irq speedup timer counter register:typical 2 to 4ms */
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#define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */
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#define PCI_MODOFF 0x94 /* suspend modulation OFF counter register, 1 = 32us */
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#define PCI_MODON 0x95 /* suspend modulation ON counter register */
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#define PCI_SUSCFG 0x96 /* suspend configuration register */
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/* PMER1 bits */
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#define GPM (1<<0) /* global power management */
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#define GIT (1<<1) /* globally enable PM device idle timers */
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#define GTR (1<<2) /* globally enable IO traps */
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#define IRQ_SPDUP (1<<3) /* disable clock throttle during interrupt handling */
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#define VID_SPDUP (1<<4) /* disable clock throttle during vga video handling */
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#define GPM (1<<0) /* global power management */
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#define GIT (1<<1) /* globally enable PM device idle timers */
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#define GTR (1<<2) /* globally enable IO traps */
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#define IRQ_SPDUP (1<<3) /* disable clock throttle during interrupt handling */
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#define VID_SPDUP (1<<4) /* disable clock throttle during vga video handling */
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/* SUSCFG bits */
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#define SUSMOD (1<<0) /* enable/disable suspend modulation */
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#define SUSMOD (1<<0) /* enable/disable suspend modulation */
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/* the belows support only with cs5530 (after rev.1.2)/cs5530A */
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#define SMISPDUP (1<<1) /* select how SMI re-enable suspend modulation: */
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/* IRQTC timer or read SMI speedup disable reg.(F1BAR[08-09h]) */
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#define SUSCFG (1<<2) /* enable powering down a GXLV processor. "Special 3Volt Suspend" mode */
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#define SMISPDUP (1<<1) /* select how SMI re-enable suspend modulation: */
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/* IRQTC timer or read SMI speedup disable reg.(F1BAR[08-09h]) */
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#define SUSCFG (1<<2) /* enable powering down a GXLV processor. "Special 3Volt Suspend" mode */
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/* the belows support only with cs5530A */
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#define PWRSVE_ISA (1<<3) /* stop ISA clock */
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#define PWRSVE (1<<4) /* active idle */
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#define PWRSVE_ISA (1<<3) /* stop ISA clock */
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#define PWRSVE (1<<4) /* active idle */
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struct gxfreq_params {
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u8 on_duration;
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@ -144,17 +144,17 @@ module_param (max_duration, int, 0444);
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#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "gx-suspmod", msg)
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/**
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* we can detect a core multipiler from dir0_lsb
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* from GX1 datasheet p.56,
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* MULT[3:0]:
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* 0000 = SYSCLK multiplied by 4 (test only)
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* 0001 = SYSCLK multiplied by 10
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* 0010 = SYSCLK multiplied by 4
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* 0011 = SYSCLK multiplied by 6
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* 0100 = SYSCLK multiplied by 9
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* 0101 = SYSCLK multiplied by 5
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* 0110 = SYSCLK multiplied by 7
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* 0111 = SYSCLK multiplied by 8
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* we can detect a core multipiler from dir0_lsb
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* from GX1 datasheet p.56,
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* MULT[3:0]:
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* 0000 = SYSCLK multiplied by 4 (test only)
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* 0001 = SYSCLK multiplied by 10
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* 0010 = SYSCLK multiplied by 4
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* 0011 = SYSCLK multiplied by 6
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* 0100 = SYSCLK multiplied by 9
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* 0101 = SYSCLK multiplied by 5
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* 0110 = SYSCLK multiplied by 7
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* 0111 = SYSCLK multiplied by 8
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* of 33.3MHz
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**/
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static int gx_freq_mult[16] = {
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@ -164,17 +164,17 @@ static int gx_freq_mult[16] = {
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/****************************************************************
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* Low Level chipset interface *
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* Low Level chipset interface *
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****************************************************************/
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static struct pci_device_id gx_chipset_tbl[] __initdata = {
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{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, PCI_ANY_ID, PCI_ANY_ID },
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{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID },
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{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID },
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{ 0, },
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{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, PCI_ANY_ID, PCI_ANY_ID },
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{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID },
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{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID },
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{ 0, },
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};
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/**
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* gx_detect_chipset:
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* gx_detect_chipset:
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*
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**/
|
||||
static __init struct pci_dev *gx_detect_chipset(void)
|
||||
@ -182,7 +182,7 @@ static __init struct pci_dev *gx_detect_chipset(void)
|
||||
struct pci_dev *gx_pci = NULL;
|
||||
|
||||
/* check if CPU is a MediaGX or a Geode. */
|
||||
if ((current_cpu_data.x86_vendor != X86_VENDOR_NSC) &&
|
||||
if ((current_cpu_data.x86_vendor != X86_VENDOR_NSC) &&
|
||||
(current_cpu_data.x86_vendor != X86_VENDOR_CYRIX)) {
|
||||
dprintk("error: no MediaGX/Geode processor found!\n");
|
||||
return NULL;
|
||||
@ -190,9 +190,8 @@ static __init struct pci_dev *gx_detect_chipset(void)
|
||||
|
||||
/* detect which companion chip is used */
|
||||
while ((gx_pci = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, gx_pci)) != NULL) {
|
||||
if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL) {
|
||||
if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL)
|
||||
return gx_pci;
|
||||
}
|
||||
}
|
||||
|
||||
dprintk("error: no supported chipset found!\n");
|
||||
@ -200,7 +199,7 @@ static __init struct pci_dev *gx_detect_chipset(void)
|
||||
}
|
||||
|
||||
/**
|
||||
* gx_get_cpuspeed:
|
||||
* gx_get_cpuspeed:
|
||||
*
|
||||
* Finds out at which efficient frequency the Cyrix MediaGX/NatSemi Geode CPU runs.
|
||||
*/
|
||||
@ -217,7 +216,7 @@ static unsigned int gx_get_cpuspeed(unsigned int cpu)
|
||||
* gx_validate_speed:
|
||||
* determine current cpu speed
|
||||
*
|
||||
**/
|
||||
**/
|
||||
|
||||
static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, u8 *off_duration)
|
||||
{
|
||||
@ -247,18 +246,17 @@ static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, u8 *off
|
||||
|
||||
|
||||
/**
|
||||
* gx_set_cpuspeed:
|
||||
* set cpu speed in khz.
|
||||
* gx_set_cpuspeed:
|
||||
* set cpu speed in khz.
|
||||
**/
|
||||
|
||||
static void gx_set_cpuspeed(unsigned int khz)
|
||||
{
|
||||
u8 suscfg, pmer1;
|
||||
u8 suscfg, pmer1;
|
||||
unsigned int new_khz;
|
||||
unsigned long flags;
|
||||
struct cpufreq_freqs freqs;
|
||||
|
||||
|
||||
freqs.cpu = 0;
|
||||
freqs.old = gx_get_cpuspeed(0);
|
||||
|
||||
@ -303,17 +301,17 @@ static void gx_set_cpuspeed(unsigned int khz)
|
||||
pci_write_config_byte(gx_params->cs55x0, PCI_MODOFF, gx_params->off_duration);
|
||||
pci_write_config_byte(gx_params->cs55x0, PCI_MODON, gx_params->on_duration);
|
||||
|
||||
pci_write_config_byte(gx_params->cs55x0, PCI_SUSCFG, suscfg);
|
||||
pci_read_config_byte(gx_params->cs55x0, PCI_SUSCFG, &suscfg);
|
||||
pci_write_config_byte(gx_params->cs55x0, PCI_SUSCFG, suscfg);
|
||||
pci_read_config_byte(gx_params->cs55x0, PCI_SUSCFG, &suscfg);
|
||||
|
||||
local_irq_restore(flags);
|
||||
local_irq_restore(flags);
|
||||
|
||||
gx_params->pci_suscfg = suscfg;
|
||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
||||
|
||||
dprintk("suspend modulation w/ duration of ON:%d us, OFF:%d us\n",
|
||||
gx_params->on_duration * 32, gx_params->off_duration * 32);
|
||||
dprintk("suspend modulation w/ duration of ON:%d us, OFF:%d us\n",
|
||||
gx_params->on_duration * 32, gx_params->off_duration * 32);
|
||||
dprintk("suspend modulation w/ clock speed: %d kHz.\n", freqs.new);
|
||||
}
|
||||
|
||||
@ -333,8 +331,8 @@ static int cpufreq_gx_verify(struct cpufreq_policy *policy)
|
||||
unsigned int tmp_freq = 0;
|
||||
u8 tmp1, tmp2;
|
||||
|
||||
if (!stock_freq || !policy)
|
||||
return -EINVAL;
|
||||
if (!stock_freq || !policy)
|
||||
return -EINVAL;
|
||||
|
||||
policy->cpu = 0;
|
||||
cpufreq_verify_within_limits(policy, (stock_freq / max_duration), stock_freq);
|
||||
@ -373,8 +371,8 @@ static int cpufreq_gx_target(struct cpufreq_policy *policy,
|
||||
u8 tmp1, tmp2;
|
||||
unsigned int tmp_freq;
|
||||
|
||||
if (!stock_freq || !policy)
|
||||
return -EINVAL;
|
||||
if (!stock_freq || !policy)
|
||||
return -EINVAL;
|
||||
|
||||
policy->cpu = 0;
|
||||
|
||||
|
||||
@ -298,7 +298,7 @@ static struct freq_attr* p4clockmod_attr[] = {
|
||||
};
|
||||
|
||||
static struct cpufreq_driver p4clockmod_driver = {
|
||||
.verify = cpufreq_p4_verify,
|
||||
.verify = cpufreq_p4_verify,
|
||||
.target = cpufreq_p4_target,
|
||||
.init = cpufreq_p4_cpu_init,
|
||||
.exit = cpufreq_p4_cpu_exit,
|
||||
|
||||
@ -152,7 +152,7 @@ static int powernow_k6_cpu_init(struct cpufreq_policy *policy)
|
||||
busfreq = cpu_khz / max_multiplier;
|
||||
|
||||
/* table init */
|
||||
for (i=0; (clock_ratio[i].frequency != CPUFREQ_TABLE_END); i++) {
|
||||
for (i=0; (clock_ratio[i].frequency != CPUFREQ_TABLE_END); i++) {
|
||||
if (clock_ratio[i].index > max_multiplier)
|
||||
clock_ratio[i].frequency = CPUFREQ_ENTRY_INVALID;
|
||||
else
|
||||
@ -182,7 +182,7 @@ static int powernow_k6_cpu_exit(struct cpufreq_policy *policy)
|
||||
powernow_k6_set_state(i);
|
||||
}
|
||||
cpufreq_frequency_table_put_attr(policy->cpu);
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int powernow_k6_get(unsigned int cpu)
|
||||
@ -196,8 +196,8 @@ static struct freq_attr* powernow_k6_attr[] = {
|
||||
};
|
||||
|
||||
static struct cpufreq_driver powernow_k6_driver = {
|
||||
.verify = powernow_k6_verify,
|
||||
.target = powernow_k6_target,
|
||||
.verify = powernow_k6_verify,
|
||||
.target = powernow_k6_target,
|
||||
.init = powernow_k6_cpu_init,
|
||||
.exit = powernow_k6_cpu_exit,
|
||||
.get = powernow_k6_get,
|
||||
|
||||
@ -83,11 +83,10 @@ static u32 find_millivolts_from_vid(struct powernow_k8_data *data, u32 vid)
|
||||
*/
|
||||
static u32 convert_fid_to_vco_fid(u32 fid)
|
||||
{
|
||||
if (fid < HI_FID_TABLE_BOTTOM) {
|
||||
if (fid < HI_FID_TABLE_BOTTOM)
|
||||
return 8 + (2 * fid);
|
||||
} else {
|
||||
else
|
||||
return fid;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
@ -782,9 +781,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
|
||||
/* verify only 1 entry from the lo frequency table */
|
||||
if (fid < HI_FID_TABLE_BOTTOM) {
|
||||
if (cntlofreq) {
|
||||
/* if both entries are the same, ignore this
|
||||
* one...
|
||||
*/
|
||||
/* if both entries are the same, ignore this one ... */
|
||||
if ((powernow_table[i].frequency != powernow_table[cntlofreq].frequency) ||
|
||||
(powernow_table[i].index != powernow_table[cntlofreq].index)) {
|
||||
printk(KERN_ERR PFX "Too many lo freq table entries\n");
|
||||
|
||||
@ -63,7 +63,7 @@ struct powernow_k8_data {
|
||||
#define MSR_C_LO_VID_SHIFT 8
|
||||
|
||||
/* Field definitions within the FID VID High Control MSR : */
|
||||
#define MSR_C_HI_STP_GNT_TO 0x000fffff
|
||||
#define MSR_C_HI_STP_GNT_TO 0x000fffff
|
||||
|
||||
/* Field definitions within the FID VID Low Status MSR : */
|
||||
#define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */
|
||||
|
||||
@ -36,8 +36,8 @@ static unsigned int pentium3_get_frequency (unsigned int processor)
|
||||
/* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
|
||||
struct {
|
||||
unsigned int ratio; /* Frequency Multiplier (x10) */
|
||||
u8 bitmap; /* power on configuration bits
|
||||
[27, 25:22] (in MSR 0x2a) */
|
||||
u8 bitmap; /* power on configuration bits
|
||||
[27, 25:22] (in MSR 0x2a) */
|
||||
} msr_decode_mult [] = {
|
||||
{ 30, 0x01 },
|
||||
{ 35, 0x05 },
|
||||
@ -58,9 +58,9 @@ static unsigned int pentium3_get_frequency (unsigned int processor)
|
||||
|
||||
/* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
|
||||
struct {
|
||||
unsigned int value; /* Front Side Bus speed in MHz */
|
||||
u8 bitmap; /* power on configuration bits [18: 19]
|
||||
(in MSR 0x2a) */
|
||||
unsigned int value; /* Front Side Bus speed in MHz */
|
||||
u8 bitmap; /* power on configuration bits [18: 19]
|
||||
(in MSR 0x2a) */
|
||||
} msr_decode_fsb [] = {
|
||||
{ 66, 0x0 },
|
||||
{ 100, 0x2 },
|
||||
@ -68,8 +68,8 @@ static unsigned int pentium3_get_frequency (unsigned int processor)
|
||||
{ 0, 0xff}
|
||||
};
|
||||
|
||||
u32 msr_lo, msr_tmp;
|
||||
int i = 0, j = 0;
|
||||
u32 msr_lo, msr_tmp;
|
||||
int i = 0, j = 0;
|
||||
|
||||
/* read MSR 0x2a - we only need the low 32 bits */
|
||||
rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
|
||||
@ -106,7 +106,7 @@ static unsigned int pentium3_get_frequency (unsigned int processor)
|
||||
|
||||
static unsigned int pentiumM_get_frequency(void)
|
||||
{
|
||||
u32 msr_lo, msr_tmp;
|
||||
u32 msr_lo, msr_tmp;
|
||||
|
||||
rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
|
||||
dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
|
||||
@ -198,7 +198,7 @@ EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency);
|
||||
unsigned int speedstep_detect_processor (void)
|
||||
{
|
||||
struct cpuinfo_x86 *c = cpu_data;
|
||||
u32 ebx, msr_lo, msr_hi;
|
||||
u32 ebx, msr_lo, msr_hi;
|
||||
|
||||
dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);
|
||||
|
||||
@ -253,7 +253,7 @@ unsigned int speedstep_detect_processor (void)
|
||||
* also, M-P4M HTs have ebx=0x8, too
|
||||
* For now, they are distinguished by the model_id string
|
||||
*/
|
||||
if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL))
|
||||
if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL))
|
||||
return SPEEDSTEP_PROCESSOR_P4M;
|
||||
break;
|
||||
default:
|
||||
@ -264,8 +264,7 @@ unsigned int speedstep_detect_processor (void)
|
||||
|
||||
switch (c->x86_model) {
|
||||
case 0x0B: /* Intel PIII [Tualatin] */
|
||||
/* cpuid_ebx(1) is 0x04 for desktop PIII,
|
||||
0x06 for mobile PIII-M */
|
||||
/* cpuid_ebx(1) is 0x04 for desktop PIII, 0x06 for mobile PIII-M */
|
||||
ebx = cpuid_ebx(0x00000001);
|
||||
dprintk("ebx is %x\n", ebx);
|
||||
|
||||
@ -277,7 +276,6 @@ unsigned int speedstep_detect_processor (void)
|
||||
/* So far all PIII-M processors support SpeedStep. See
|
||||
* Intel's 24540640.pdf of June 2003
|
||||
*/
|
||||
|
||||
return SPEEDSTEP_PROCESSOR_PIII_T;
|
||||
|
||||
case 0x08: /* Intel PIII [Coppermine] */
|
||||
@ -399,7 +397,7 @@ unsigned int speedstep_get_freqs(unsigned int processor,
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
out:
|
||||
local_irq_restore(flags);
|
||||
return (ret);
|
||||
}
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
|
||||
#define SPEEDSTEP_PROCESSOR_PIII_C_EARLY 0x00000001 /* Coppermine core */
|
||||
#define SPEEDSTEP_PROCESSOR_PIII_C 0x00000002 /* Coppermine core */
|
||||
#define SPEEDSTEP_PROCESSOR_PIII_T 0x00000003 /* Tualatin core */
|
||||
#define SPEEDSTEP_PROCESSOR_PIII_T 0x00000003 /* Tualatin core */
|
||||
#define SPEEDSTEP_PROCESSOR_P4M 0x00000004 /* P4-M */
|
||||
|
||||
/* the following processors are not speedstep-capable and are not auto-detected
|
||||
@ -25,8 +25,8 @@
|
||||
|
||||
/* speedstep states -- only two of them */
|
||||
|
||||
#define SPEEDSTEP_HIGH 0x00000000
|
||||
#define SPEEDSTEP_LOW 0x00000001
|
||||
#define SPEEDSTEP_HIGH 0x00000000
|
||||
#define SPEEDSTEP_LOW 0x00000001
|
||||
|
||||
|
||||
/* detect a speedstep-capable processor */
|
||||
@ -42,7 +42,7 @@ extern unsigned int speedstep_get_processor_frequency(unsigned int processor);
|
||||
* cpufreq_notify_transition calls are initiated.
|
||||
*/
|
||||
extern unsigned int speedstep_get_freqs(unsigned int processor,
|
||||
unsigned int *low_speed,
|
||||
unsigned int *high_speed,
|
||||
unsigned int *transition_latency,
|
||||
void (*set_state) (unsigned int state));
|
||||
unsigned int *low_speed,
|
||||
unsigned int *high_speed,
|
||||
unsigned int *transition_latency,
|
||||
void (*set_state) (unsigned int state));
|
||||
|
||||
@ -30,19 +30,19 @@
|
||||
* If user gives it, these are used.
|
||||
*
|
||||
*/
|
||||
static int smi_port = 0;
|
||||
static int smi_cmd = 0;
|
||||
static unsigned int smi_sig = 0;
|
||||
static int smi_port = 0;
|
||||
static int smi_cmd = 0;
|
||||
static unsigned int smi_sig = 0;
|
||||
|
||||
/* info about the processor */
|
||||
static unsigned int speedstep_processor = 0;
|
||||
static unsigned int speedstep_processor = 0;
|
||||
|
||||
/*
|
||||
* There are only two frequency states for each processor. Values
|
||||
* There are only two frequency states for each processor. Values
|
||||
* are in kHz for the time being.
|
||||
*/
|
||||
static struct cpufreq_frequency_table speedstep_freqs[] = {
|
||||
{SPEEDSTEP_HIGH, 0},
|
||||
{SPEEDSTEP_HIGH, 0},
|
||||
{SPEEDSTEP_LOW, 0},
|
||||
{0, CPUFREQ_TABLE_END},
|
||||
};
|
||||
@ -296,7 +296,7 @@ static int speedstep_cpu_init(struct cpufreq_policy *policy)
|
||||
if (result)
|
||||
return (result);
|
||||
|
||||
cpufreq_frequency_table_get_attr(speedstep_freqs, policy->cpu);
|
||||
cpufreq_frequency_table_get_attr(speedstep_freqs, policy->cpu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -332,8 +332,8 @@ static struct freq_attr* speedstep_attr[] = {
|
||||
|
||||
static struct cpufreq_driver speedstep_driver = {
|
||||
.name = "speedstep-smi",
|
||||
.verify = speedstep_verify,
|
||||
.target = speedstep_target,
|
||||
.verify = speedstep_verify,
|
||||
.target = speedstep_target,
|
||||
.init = speedstep_cpu_init,
|
||||
.exit = speedstep_cpu_exit,
|
||||
.get = speedstep_get,
|
||||
@ -373,7 +373,6 @@ static int __init speedstep_init(void)
|
||||
dprintk("signature:0x%.8lx, command:0x%.8lx, event:0x%.8lx, perf_level:0x%.8lx.\n",
|
||||
ist_info.signature, ist_info.command, ist_info.event, ist_info.perf_level);
|
||||
|
||||
|
||||
/* Error if no IST-SMI BIOS or no PARM
|
||||
sig= 'ISGE' aka 'Intel Speedstep Gate E' */
|
||||
if ((ist_info.signature != 0x47534943) && (
|
||||
@ -386,17 +385,15 @@ static int __init speedstep_init(void)
|
||||
smi_sig = ist_info.signature;
|
||||
|
||||
/* setup smi_port from MODLULE_PARM or BIOS */
|
||||
if ((smi_port > 0xff) || (smi_port < 0)) {
|
||||
if ((smi_port > 0xff) || (smi_port < 0))
|
||||
return -EINVAL;
|
||||
} else if (smi_port == 0) {
|
||||
else if (smi_port == 0)
|
||||
smi_port = ist_info.command & 0xff;
|
||||
}
|
||||
|
||||
if ((smi_cmd > 0xff) || (smi_cmd < 0)) {
|
||||
if ((smi_cmd > 0xff) || (smi_cmd < 0))
|
||||
return -EINVAL;
|
||||
} else if (smi_cmd == 0) {
|
||||
else if (smi_cmd == 0)
|
||||
smi_cmd = (ist_info.command >> 16) & 0xff;
|
||||
}
|
||||
|
||||
return cpufreq_register_driver(&speedstep_driver);
|
||||
}
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
* (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
|
||||
*
|
||||
* Oct 2005 - Ashok Raj <ashok.raj@intel.com>
|
||||
* Added handling for CPU hotplug
|
||||
* Added handling for CPU hotplug
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
@ -335,11 +335,11 @@ extern struct sysdev_class cpu_sysdev_class;
|
||||
* "unsigned int".
|
||||
*/
|
||||
|
||||
#define show_one(file_name, object) \
|
||||
static ssize_t show_##file_name \
|
||||
(struct cpufreq_policy * policy, char *buf) \
|
||||
{ \
|
||||
return sprintf (buf, "%u\n", policy->object); \
|
||||
#define show_one(file_name, object) \
|
||||
static ssize_t show_##file_name \
|
||||
(struct cpufreq_policy * policy, char *buf) \
|
||||
{ \
|
||||
return sprintf (buf, "%u\n", policy->object); \
|
||||
}
|
||||
|
||||
show_one(cpuinfo_min_freq, cpuinfo.min_freq);
|
||||
@ -740,7 +740,7 @@ static int cpufreq_remove_dev (struct sys_device * sys_dev)
|
||||
if (!kobject_get(&data->kobj)) {
|
||||
spin_unlock_irqrestore(&cpufreq_driver_lock, flags);
|
||||
cpufreq_debug_enable_ratelimit();
|
||||
return -EFAULT;
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
@ -1234,7 +1234,7 @@ int cpufreq_register_governor(struct cpufreq_governor *governor)
|
||||
}
|
||||
list_add(&governor->governor_list, &cpufreq_governor_list);
|
||||
|
||||
mutex_unlock(&cpufreq_governor_mutex);
|
||||
mutex_unlock(&cpufreq_governor_mutex);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cpufreq_register_governor);
|
||||
|
||||
@ -48,7 +48,7 @@
|
||||
* this governor will not work.
|
||||
* All times here are in uS.
|
||||
*/
|
||||
static unsigned int def_sampling_rate;
|
||||
static unsigned int def_sampling_rate;
|
||||
#define MIN_SAMPLING_RATE_RATIO (2)
|
||||
/* for correct statistics, we need at least 10 ticks between each measure */
|
||||
#define MIN_STAT_SAMPLING_RATE (MIN_SAMPLING_RATE_RATIO * jiffies_to_usecs(10))
|
||||
@ -62,28 +62,28 @@ static unsigned int def_sampling_rate;
|
||||
static void do_dbs_timer(void *data);
|
||||
|
||||
struct cpu_dbs_info_s {
|
||||
struct cpufreq_policy *cur_policy;
|
||||
unsigned int prev_cpu_idle_up;
|
||||
unsigned int prev_cpu_idle_down;
|
||||
unsigned int enable;
|
||||
struct cpufreq_policy *cur_policy;
|
||||
unsigned int prev_cpu_idle_up;
|
||||
unsigned int prev_cpu_idle_down;
|
||||
unsigned int enable;
|
||||
};
|
||||
static DEFINE_PER_CPU(struct cpu_dbs_info_s, cpu_dbs_info);
|
||||
|
||||
static unsigned int dbs_enable; /* number of CPUs using this policy */
|
||||
|
||||
static DEFINE_MUTEX (dbs_mutex);
|
||||
static DEFINE_MUTEX (dbs_mutex);
|
||||
static DECLARE_WORK (dbs_work, do_dbs_timer, NULL);
|
||||
|
||||
struct dbs_tuners {
|
||||
unsigned int sampling_rate;
|
||||
unsigned int sampling_down_factor;
|
||||
unsigned int up_threshold;
|
||||
unsigned int ignore_nice;
|
||||
unsigned int sampling_rate;
|
||||
unsigned int sampling_down_factor;
|
||||
unsigned int up_threshold;
|
||||
unsigned int ignore_nice;
|
||||
};
|
||||
|
||||
static struct dbs_tuners dbs_tuners_ins = {
|
||||
.up_threshold = DEF_FREQUENCY_UP_THRESHOLD,
|
||||
.sampling_down_factor = DEF_SAMPLING_DOWN_FACTOR,
|
||||
.up_threshold = DEF_FREQUENCY_UP_THRESHOLD,
|
||||
.sampling_down_factor = DEF_SAMPLING_DOWN_FACTOR,
|
||||
};
|
||||
|
||||
static inline unsigned int get_cpu_idle_time(unsigned int cpu)
|
||||
@ -106,8 +106,8 @@ static ssize_t show_sampling_rate_min(struct cpufreq_policy *policy, char *buf)
|
||||
return sprintf (buf, "%u\n", MIN_SAMPLING_RATE);
|
||||
}
|
||||
|
||||
#define define_one_ro(_name) \
|
||||
static struct freq_attr _name = \
|
||||
#define define_one_ro(_name) \
|
||||
static struct freq_attr _name = \
|
||||
__ATTR(_name, 0444, show_##_name, NULL)
|
||||
|
||||
define_one_ro(sampling_rate_max);
|
||||
@ -460,11 +460,11 @@ static int cpufreq_governor_dbs(struct cpufreq_policy *policy,
|
||||
if (policy->max < this_dbs_info->cur_policy->cur)
|
||||
__cpufreq_driver_target(
|
||||
this_dbs_info->cur_policy,
|
||||
policy->max, CPUFREQ_RELATION_H);
|
||||
policy->max, CPUFREQ_RELATION_H);
|
||||
else if (policy->min > this_dbs_info->cur_policy->cur)
|
||||
__cpufreq_driver_target(
|
||||
this_dbs_info->cur_policy,
|
||||
policy->min, CPUFREQ_RELATION_L);
|
||||
policy->min, CPUFREQ_RELATION_L);
|
||||
mutex_unlock(&dbs_mutex);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
* drivers/cpufreq/cpufreq_stats.c
|
||||
*
|
||||
* Copyright (C) 2003-2004 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>.
|
||||
* (C) 2004 Zou Nan hai <nanhai.zou@intel.com>.
|
||||
* (C) 2004 Zou Nan hai <nanhai.zou@intel.com>.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
||||
@ -60,8 +60,7 @@ int cpufreq_frequency_table_verify(struct cpufreq_policy *policy,
|
||||
return -EINVAL;
|
||||
|
||||
cpufreq_verify_within_limits(policy,
|
||||
policy->cpuinfo.min_freq,
|
||||
policy->cpuinfo.max_freq);
|
||||
policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
|
||||
|
||||
for (i=0; (table[i].frequency != CPUFREQ_TABLE_END); i++) {
|
||||
unsigned int freq = table[i].frequency;
|
||||
@ -77,8 +76,7 @@ int cpufreq_frequency_table_verify(struct cpufreq_policy *policy,
|
||||
policy->max = next_larger;
|
||||
|
||||
cpufreq_verify_within_limits(policy,
|
||||
policy->cpuinfo.min_freq,
|
||||
policy->cpuinfo.max_freq);
|
||||
policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
|
||||
|
||||
dprintk("verification lead to (%u - %u kHz) for cpu %u\n", policy->min, policy->max, policy->cpu);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user