leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[CPUFREQ] Lots of whitespace & CodingStyle cleanup.

Browse Source 
Signed-off-by: Dave Jones <davej@redhat.com>
This commit is contained in:
Dave Jones 2006-02-28 00:43:23 -05:00
parent 8ad5496d23
commit 32ee8c3e47
20 changed files with 343 additions and 371 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/i386/kernel/cpu/cpufreq/Kconfig
View File

@ -96,7 +96,6 @@ config X86_POWERNOW_K8_ACPI
config X86_GX_SUSPMOD config X86_GX_SUSPMOD
tristate "Cyrix MediaGX/NatSemi Geode Suspend Modulation" tristate "Cyrix MediaGX/NatSemi Geode Suspend Modulation"
depends on PCI
help help
This add the CPUFreq driver for NatSemi Geode processors which This add the CPUFreq driver for NatSemi Geode processors which
support suspend modulation. support suspend modulation.

38
arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
View File

@ -57,7 +57,7 @@ MODULE_PARM_DESC(min_fsb,
#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg) #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)
/* /**
* nforce2_calc_fsb - calculate FSB * nforce2_calc_fsb - calculate FSB
* @pll: PLL value * @pll: PLL value
* *
@ -76,7 +76,7 @@ static int nforce2_calc_fsb(int pll)
return 0; return 0;
} }
/* /**
* nforce2_calc_pll - calculate PLL value * nforce2_calc_pll - calculate PLL value
* @fsb: FSB * @fsb: FSB
* *
@ -106,7 +106,7 @@ static int nforce2_calc_pll(unsigned int fsb)
return NFORCE2_PLL(mul, div); return NFORCE2_PLL(mul, div);
} }
/* /**
* nforce2_write_pll - write PLL value to chipset * nforce2_write_pll - write PLL value to chipset
* @pll: PLL value * @pll: PLL value
* *
@ -121,15 +121,13 @@ static void nforce2_write_pll(int pll)
pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp); pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);
/* Now write the value in all 64 registers */ /* Now write the value in all 64 registers */
for (temp = 0; temp <= 0x3f; temp++) { for (temp = 0; temp <= 0x3f; temp++)
pci_write_config_dword(nforce2_chipset_dev, pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLREG, pll);
NFORCE2_PLLREG, pll);
}
return; return;
} }
/* /**
* nforce2_fsb_read - Read FSB * nforce2_fsb_read - Read FSB
* *
* Read FSB from chipset * Read FSB from chipset
@ -140,14 +138,9 @@ static unsigned int nforce2_fsb_read(int bootfsb)
struct pci_dev *nforce2_sub5; struct pci_dev *nforce2_sub5;
u32 fsb, temp = 0; u32 fsb, temp = 0;
/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */ /* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
0x01EF, 0x01EF,PCI_ANY_ID,PCI_ANY_ID,NULL);
PCI_ANY_ID,
PCI_ANY_ID,
NULL);
if (!nforce2_sub5) if (!nforce2_sub5)
return 0; return 0;
@ -155,21 +148,19 @@ static unsigned int nforce2_fsb_read(int bootfsb)
fsb /= 1000000; fsb /= 1000000;
/* Check if PLL register is already set */ /* Check if PLL register is already set */
pci_read_config_byte(nforce2_chipset_dev, pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
NFORCE2_PLLENABLE, (u8 *)&temp);
if(bootfsb || !temp) if(bootfsb || !temp)
return fsb; return fsb;
/* Use PLL register FSB value */ /* Use PLL register FSB value */
pci_read_config_dword(nforce2_chipset_dev, pci_read_config_dword(nforce2_chipset_dev,NFORCE2_PLLREG, &temp);
NFORCE2_PLLREG, &temp);
fsb = nforce2_calc_fsb(temp); fsb = nforce2_calc_fsb(temp);
return fsb; return fsb;
} }
/* /**
* nforce2_set_fsb - set new FSB * nforce2_set_fsb - set new FSB
* @fsb: New FSB * @fsb: New FSB
* *
@ -194,8 +185,7 @@ static int nforce2_set_fsb(unsigned int fsb)
} }
/* First write? Then set actual value */ /* First write? Then set actual value */
pci_read_config_byte(nforce2_chipset_dev, pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
NFORCE2_PLLENABLE, (u8 *)&temp);
if (!temp) { if (!temp) {
pll = nforce2_calc_pll(tfsb); pll = nforce2_calc_pll(tfsb);
@ -405,10 +395,8 @@ static unsigned int nforce2_detect_chipset(void)
u8 revision; u8 revision;
nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_NFORCE2, PCI_DEVICE_ID_NVIDIA_NFORCE2,
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, NULL);
PCI_ANY_ID,
NULL);
if (nforce2_chipset_dev == NULL) if (nforce2_chipset_dev == NULL)
return -ENODEV; return -ENODEV;

63
arch/i386/kernel/cpu/cpufreq/elanfreq.c
View File

@ -1,5 +1,5 @@
/* /*
* elanfreq: cpufreq driver for the AMD ELAN family * elanfreq: cpufreq driver for the AMD ELAN family
* *
* (c) Copyright 2002 Robert Schwebel <r.schwebel@pengutronix.de> * (c) Copyright 2002 Robert Schwebel <r.schwebel@pengutronix.de>
* *
@ -28,7 +28,7 @@
#include <asm/timex.h> #include <asm/timex.h>
#include <asm/io.h> #include <asm/io.h>
#define REG_CSCIR 0x22 /* Chip Setup and Control Index Register */ #define REG_CSCIR 0x22 /* Chip Setup and Control Index Register */
#define REG_CSCDR 0x23 /* Chip Setup and Control Data Register */ #define REG_CSCDR 0x23 /* Chip Setup and Control Data Register */
/* Module parameter */ /* Module parameter */
@ -79,46 +79,46 @@ static struct cpufreq_frequency_table elanfreq_table[] = {
static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu) static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu)
{ {
u8 clockspeed_reg; /* Clock Speed Register */ u8 clockspeed_reg; /* Clock Speed Register */
local_irq_disable(); local_irq_disable();
outb_p(0x80,REG_CSCIR); outb_p(0x80,REG_CSCIR);
clockspeed_reg = inb_p(REG_CSCDR); clockspeed_reg = inb_p(REG_CSCDR);
local_irq_enable(); local_irq_enable();
if ((clockspeed_reg & 0xE0) == 0xE0) { return 0; } if ((clockspeed_reg & 0xE0) == 0xE0)
return 0;
/* Are we in CPU clock multiplied mode (66/99 MHz)? */ /* Are we in CPU clock multiplied mode (66/99 MHz)? */
if ((clockspeed_reg & 0xE0) == 0xC0) { if ((clockspeed_reg & 0xE0) == 0xC0) {
if ((clockspeed_reg & 0x01) == 0) { if ((clockspeed_reg & 0x01) == 0)
return 66000; return 66000;
} else { else
return 99000; return 99000;
} }
}
/* 33 MHz is not 32 MHz... */ /* 33 MHz is not 32 MHz... */
if ((clockspeed_reg & 0xE0)==0xA0) if ((clockspeed_reg & 0xE0)==0xA0)
return 33000; return 33000;
return ((1<<((clockspeed_reg & 0xE0) >> 5)) * 1000); return ((1<<((clockspeed_reg & 0xE0) >> 5)) * 1000);
} }
/** /**
* elanfreq_set_cpu_frequency: Change the CPU core frequency * elanfreq_set_cpu_frequency: Change the CPU core frequency
* @cpu: cpu number * @cpu: cpu number
* @freq: frequency in kHz * @freq: frequency in kHz
* *
* This function takes a frequency value and changes the CPU frequency * This function takes a frequency value and changes the CPU frequency
* according to this. Note that the frequency has to be checked by * according to this. Note that the frequency has to be checked by
* elanfreq_validatespeed() for correctness! * elanfreq_validatespeed() for correctness!
* *
* There is no return value. * There is no return value.
*/ */
static void elanfreq_set_cpu_state (unsigned int state) { static void elanfreq_set_cpu_state (unsigned int state)
{
struct cpufreq_freqs freqs; struct cpufreq_freqs freqs;
freqs.old = elanfreq_get_cpu_frequency(0); freqs.old = elanfreq_get_cpu_frequency(0);
@ -127,7 +127,8 @@ static void elanfreq_set_cpu_state (unsigned int state) {
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
printk(KERN_INFO "elanfreq: attempting to set frequency to %i kHz\n",elan_multiplier[state].clock); printk(KERN_INFO "elanfreq: attempting to set frequency to %i kHz\n",
elan_multiplier[state].clock);
/* /*
@ -143,7 +144,7 @@ static void elanfreq_set_cpu_state (unsigned int state) {
*/ */
local_irq_disable(); local_irq_disable();
outb_p(0x40,REG_CSCIR); /* Disable hyperspeed mode */ outb_p(0x40,REG_CSCIR); /* Disable hyperspeed mode */
outb_p(0x00,REG_CSCDR); outb_p(0x00,REG_CSCDR);
local_irq_enable(); /* wait till internal pipelines and */ local_irq_enable(); /* wait till internal pipelines and */
udelay(1000); /* buffers have cleaned up */ udelay(1000); /* buffers have cleaned up */
@ -166,10 +167,10 @@ static void elanfreq_set_cpu_state (unsigned int state) {
/** /**
* elanfreq_validatespeed: test if frequency range is valid * elanfreq_validatespeed: test if frequency range is valid
* @policy: the policy to validate * @policy: the policy to validate
* *
* This function checks if a given frequency range in kHz is valid * This function checks if a given frequency range in kHz is valid
* for the hardware supported by the driver. * for the hardware supported by the driver.
*/ */
static int elanfreq_verify (struct cpufreq_policy *policy) static int elanfreq_verify (struct cpufreq_policy *policy)
@ -181,7 +182,7 @@ static int elanfreq_target (struct cpufreq_policy *policy,
unsigned int target_freq, unsigned int target_freq,
unsigned int relation) unsigned int relation)
{ {
unsigned int newstate = 0; unsigned int newstate = 0;
if (cpufreq_frequency_table_target(policy, &elanfreq_table[0], target_freq, relation, &newstate)) if (cpufreq_frequency_table_target(policy, &elanfreq_table[0], target_freq, relation, &newstate))
return -EINVAL; return -EINVAL;
@ -212,7 +213,7 @@ static int elanfreq_cpu_init(struct cpufreq_policy *policy)
max_freq = elanfreq_get_cpu_frequency(0); max_freq = elanfreq_get_cpu_frequency(0);
/* table init */ /* table init */
for (i=0; (elanfreq_table[i].frequency != CPUFREQ_TABLE_END); i++) { for (i=0; (elanfreq_table[i].frequency != CPUFREQ_TABLE_END); i++) {
if (elanfreq_table[i].frequency > max_freq) if (elanfreq_table[i].frequency > max_freq)
elanfreq_table[i].frequency = CPUFREQ_ENTRY_INVALID; elanfreq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
} }
@ -226,8 +227,7 @@ static int elanfreq_cpu_init(struct cpufreq_policy *policy)
if (result) if (result)
return (result); return (result);
cpufreq_frequency_table_get_attr(elanfreq_table, policy->cpu); cpufreq_frequency_table_get_attr(elanfreq_table, policy->cpu);
return 0; return 0;
} }
@ -268,9 +268,9 @@ static struct freq_attr* elanfreq_attr[] = {
static struct cpufreq_driver elanfreq_driver = { static struct cpufreq_driver elanfreq_driver = {
.get = elanfreq_get_cpu_frequency, .get = elanfreq_get_cpu_frequency,
.verify = elanfreq_verify, .verify = elanfreq_verify,
.target = elanfreq_target, .target = elanfreq_target,
.init = elanfreq_cpu_init, .init = elanfreq_cpu_init,
.exit = elanfreq_cpu_exit, .exit = elanfreq_cpu_exit,
.name = "elanfreq", .name = "elanfreq",
@ -285,12 +285,10 @@ static int __init elanfreq_init(void)
/* Test if we have the right hardware */ /* Test if we have the right hardware */
if ((c->x86_vendor != X86_VENDOR_AMD) || if ((c->x86_vendor != X86_VENDOR_AMD) ||
(c->x86 != 4) || (c->x86_model!=10)) (c->x86 != 4) || (c->x86_model!=10)) {
{
printk(KERN_INFO "elanfreq: error: no Elan processor found!\n"); printk(KERN_INFO "elanfreq: error: no Elan processor found!\n");
return -ENODEV; return -ENODEV;
} }
return cpufreq_register_driver(&elanfreq_driver); return cpufreq_register_driver(&elanfreq_driver);
} }
@ -309,4 +307,3 @@ MODULE_DESCRIPTION("cpufreq driver for AMD's Elan CPUs");
module_init(elanfreq_init); module_init(elanfreq_init);
module_exit(elanfreq_exit); module_exit(elanfreq_exit);

116
arch/i386/kernel/cpu/cpufreq/gx-suspmod.c
View File

@ -32,7 +32,7 @@
* to the processor. * to the processor.
* *
* These counters define a ratio which is the effective frequency * These counters define a ratio which is the effective frequency
* of operation of the system. * of operation of the system.
* *
* OFF Count * OFF Count
* F_eff = Fgx * ---------------------- * F_eff = Fgx * ----------------------
@ -52,11 +52,11 @@
*--------------------------------------------------------------------------- *---------------------------------------------------------------------------
* *
* ChangeLog: * ChangeLog:
* Dec. 12, 2003 Hiroshi Miura <miura@da-cha.org> * Dec. 12, 2003 Hiroshi Miura <miura@da-cha.org>
* - fix on/off register mistake * - fix on/off register mistake
* - fix cpu_khz calc when it stops cpu modulation. * - fix cpu_khz calc when it stops cpu modulation.
* *
* Dec. 11, 2002 Hiroshi Miura <miura@da-cha.org> * Dec. 11, 2002 Hiroshi Miura <miura@da-cha.org>
* - rewrite for Cyrix MediaGX Cx5510/5520 and * - rewrite for Cyrix MediaGX Cx5510/5520 and
* NatSemi Geode Cs5530(A). * NatSemi Geode Cs5530(A).
* *
@ -83,31 +83,31 @@
#include <asm/errno.h> #include <asm/errno.h>
/* PCI config registers, all at F0 */ /* PCI config registers, all at F0 */
#define PCI_PMER1 0x80 /* power management enable register 1 */ #define PCI_PMER1 0x80 /* power management enable register 1 */
#define PCI_PMER2 0x81 /* power management enable register 2 */ #define PCI_PMER2 0x81 /* power management enable register 2 */
#define PCI_PMER3 0x82 /* power management enable register 3 */ #define PCI_PMER3 0x82 /* power management enable register 3 */
#define PCI_IRQTC 0x8c /* irq speedup timer counter register:typical 2 to 4ms */ #define PCI_IRQTC 0x8c /* irq speedup timer counter register:typical 2 to 4ms */
#define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */ #define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */
#define PCI_MODOFF 0x94 /* suspend modulation OFF counter register, 1 = 32us */ #define PCI_MODOFF 0x94 /* suspend modulation OFF counter register, 1 = 32us */
#define PCI_MODON 0x95 /* suspend modulation ON counter register */ #define PCI_MODON 0x95 /* suspend modulation ON counter register */
#define PCI_SUSCFG 0x96 /* suspend configuration register */ #define PCI_SUSCFG 0x96 /* suspend configuration register */
/* PMER1 bits */ /* PMER1 bits */
#define GPM (1<<0) /* global power management */ #define GPM (1<<0) /* global power management */
#define GIT (1<<1) /* globally enable PM device idle timers */ #define GIT (1<<1) /* globally enable PM device idle timers */
#define GTR (1<<2) /* globally enable IO traps */ #define GTR (1<<2) /* globally enable IO traps */
#define IRQ_SPDUP (1<<3) /* disable clock throttle during interrupt handling */ #define IRQ_SPDUP (1<<3) /* disable clock throttle during interrupt handling */
#define VID_SPDUP (1<<4) /* disable clock throttle during vga video handling */ #define VID_SPDUP (1<<4) /* disable clock throttle during vga video handling */
/* SUSCFG bits */ /* SUSCFG bits */
#define SUSMOD (1<<0) /* enable/disable suspend modulation */ #define SUSMOD (1<<0) /* enable/disable suspend modulation */
/* the belows support only with cs5530 (after rev.1.2)/cs5530A */ /* the belows support only with cs5530 (after rev.1.2)/cs5530A */
#define SMISPDUP (1<<1) /* select how SMI re-enable suspend modulation: */ #define SMISPDUP (1<<1) /* select how SMI re-enable suspend modulation: */
/* IRQTC timer or read SMI speedup disable reg.(F1BAR[08-09h]) */ /* IRQTC timer or read SMI speedup disable reg.(F1BAR[08-09h]) */
#define SUSCFG (1<<2) /* enable powering down a GXLV processor. "Special 3Volt Suspend" mode */ #define SUSCFG (1<<2) /* enable powering down a GXLV processor. "Special 3Volt Suspend" mode */
/* the belows support only with cs5530A */ /* the belows support only with cs5530A */
#define PWRSVE_ISA (1<<3) /* stop ISA clock */ #define PWRSVE_ISA (1<<3) /* stop ISA clock */
#define PWRSVE (1<<4) /* active idle */ #define PWRSVE (1<<4) /* active idle */
struct gxfreq_params { struct gxfreq_params {
u8 on_duration; u8 on_duration;
@ -144,17 +144,17 @@ module_param (max_duration, int, 0444);
#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "gx-suspmod", msg) #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "gx-suspmod", msg)
/** /**
* we can detect a core multipiler from dir0_lsb * we can detect a core multipiler from dir0_lsb
* from GX1 datasheet p.56, * from GX1 datasheet p.56,
* MULT[3:0]: * MULT[3:0]:
* 0000 = SYSCLK multiplied by 4 (test only) * 0000 = SYSCLK multiplied by 4 (test only)
* 0001 = SYSCLK multiplied by 10 * 0001 = SYSCLK multiplied by 10
* 0010 = SYSCLK multiplied by 4 * 0010 = SYSCLK multiplied by 4
* 0011 = SYSCLK multiplied by 6 * 0011 = SYSCLK multiplied by 6
* 0100 = SYSCLK multiplied by 9 * 0100 = SYSCLK multiplied by 9
* 0101 = SYSCLK multiplied by 5 * 0101 = SYSCLK multiplied by 5
* 0110 = SYSCLK multiplied by 7 * 0110 = SYSCLK multiplied by 7
* 0111 = SYSCLK multiplied by 8 * 0111 = SYSCLK multiplied by 8
* of 33.3MHz * of 33.3MHz
**/ **/
static int gx_freq_mult[16] = { static int gx_freq_mult[16] = {
@ -164,17 +164,17 @@ static int gx_freq_mult[16] = {
/**************************************************************** /****************************************************************
* Low Level chipset interface * * Low Level chipset interface *
****************************************************************/ ****************************************************************/
static struct pci_device_id gx_chipset_tbl[] __initdata = { static struct pci_device_id gx_chipset_tbl[] __initdata = {
{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, PCI_ANY_ID, PCI_ANY_ID }, { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, PCI_ANY_ID, PCI_ANY_ID },
{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID }, { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID },
{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID }, { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID },
{ 0, }, { 0, },
}; };
/** /**
* gx_detect_chipset: * gx_detect_chipset:
* *
**/ **/
static __init struct pci_dev *gx_detect_chipset(void) static __init struct pci_dev *gx_detect_chipset(void)
@ -182,7 +182,7 @@ static __init struct pci_dev *gx_detect_chipset(void)
struct pci_dev *gx_pci = NULL; struct pci_dev *gx_pci = NULL;
/* check if CPU is a MediaGX or a Geode. */ /* check if CPU is a MediaGX or a Geode. */
if ((current_cpu_data.x86_vendor != X86_VENDOR_NSC) && if ((current_cpu_data.x86_vendor != X86_VENDOR_NSC) &&
(current_cpu_data.x86_vendor != X86_VENDOR_CYRIX)) { (current_cpu_data.x86_vendor != X86_VENDOR_CYRIX)) {
dprintk("error: no MediaGX/Geode processor found!\n"); dprintk("error: no MediaGX/Geode processor found!\n");
return NULL; return NULL;
@ -190,9 +190,8 @@ static __init struct pci_dev *gx_detect_chipset(void)
/* detect which companion chip is used */ /* detect which companion chip is used */
while ((gx_pci = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, gx_pci)) != NULL) { while ((gx_pci = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, gx_pci)) != NULL) {
if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL) { if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL)
return gx_pci; return gx_pci;
}
} }
dprintk("error: no supported chipset found!\n"); dprintk("error: no supported chipset found!\n");
@ -200,7 +199,7 @@ static __init struct pci_dev *gx_detect_chipset(void)
} }
/** /**
* gx_get_cpuspeed: * gx_get_cpuspeed:
* *
* Finds out at which efficient frequency the Cyrix MediaGX/NatSemi Geode CPU runs. * Finds out at which efficient frequency the Cyrix MediaGX/NatSemi Geode CPU runs.
*/ */
@ -217,7 +216,7 @@ static unsigned int gx_get_cpuspeed(unsigned int cpu)
* gx_validate_speed: * gx_validate_speed:
* determine current cpu speed * determine current cpu speed
* *
**/ **/
static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, u8 *off_duration) static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, u8 *off_duration)
{ {
@ -247,18 +246,17 @@ static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, u8 *off
/** /**
* gx_set_cpuspeed: * gx_set_cpuspeed:
* set cpu speed in khz. * set cpu speed in khz.
**/ **/
static void gx_set_cpuspeed(unsigned int khz) static void gx_set_cpuspeed(unsigned int khz)
{ {
u8 suscfg, pmer1; u8 suscfg, pmer1;
unsigned int new_khz; unsigned int new_khz;
unsigned long flags; unsigned long flags;
struct cpufreq_freqs freqs; struct cpufreq_freqs freqs;
freqs.cpu = 0; freqs.cpu = 0;
freqs.old = gx_get_cpuspeed(0); freqs.old = gx_get_cpuspeed(0);
@ -303,17 +301,17 @@ static void gx_set_cpuspeed(unsigned int khz)
pci_write_config_byte(gx_params->cs55x0, PCI_MODOFF, gx_params->off_duration); pci_write_config_byte(gx_params->cs55x0, PCI_MODOFF, gx_params->off_duration);
pci_write_config_byte(gx_params->cs55x0, PCI_MODON, gx_params->on_duration); pci_write_config_byte(gx_params->cs55x0, PCI_MODON, gx_params->on_duration);
pci_write_config_byte(gx_params->cs55x0, PCI_SUSCFG, suscfg); pci_write_config_byte(gx_params->cs55x0, PCI_SUSCFG, suscfg);
pci_read_config_byte(gx_params->cs55x0, PCI_SUSCFG, &suscfg); pci_read_config_byte(gx_params->cs55x0, PCI_SUSCFG, &suscfg);
local_irq_restore(flags); local_irq_restore(flags);
gx_params->pci_suscfg = suscfg; gx_params->pci_suscfg = suscfg;
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
dprintk("suspend modulation w/ duration of ON:%d us, OFF:%d us\n", dprintk("suspend modulation w/ duration of ON:%d us, OFF:%d us\n",
gx_params->on_duration * 32, gx_params->off_duration * 32); gx_params->on_duration * 32, gx_params->off_duration * 32);
dprintk("suspend modulation w/ clock speed: %d kHz.\n", freqs.new); dprintk("suspend modulation w/ clock speed: %d kHz.\n", freqs.new);
} }
@ -333,8 +331,8 @@ static int cpufreq_gx_verify(struct cpufreq_policy *policy)
unsigned int tmp_freq = 0; unsigned int tmp_freq = 0;
u8 tmp1, tmp2; u8 tmp1, tmp2;
if (!stock_freq || !policy) if (!stock_freq || !policy)
return -EINVAL; return -EINVAL;
policy->cpu = 0; policy->cpu = 0;
cpufreq_verify_within_limits(policy, (stock_freq / max_duration), stock_freq); cpufreq_verify_within_limits(policy, (stock_freq / max_duration), stock_freq);
@ -373,8 +371,8 @@ static int cpufreq_gx_target(struct cpufreq_policy *policy,
u8 tmp1, tmp2; u8 tmp1, tmp2;
unsigned int tmp_freq; unsigned int tmp_freq;
if (!stock_freq || !policy) if (!stock_freq || !policy)
return -EINVAL; return -EINVAL;
policy->cpu = 0; policy->cpu = 0;

2
arch/i386/kernel/cpu/cpufreq/p4-clockmod.c
View File

@ -298,7 +298,7 @@ static struct freq_attr* p4clockmod_attr[] = {
}; };
static struct cpufreq_driver p4clockmod_driver = { static struct cpufreq_driver p4clockmod_driver = {
.verify = cpufreq_p4_verify, .verify = cpufreq_p4_verify,
.target = cpufreq_p4_target, .target = cpufreq_p4_target,
.init = cpufreq_p4_cpu_init, .init = cpufreq_p4_cpu_init,
.exit = cpufreq_p4_cpu_exit, .exit = cpufreq_p4_cpu_exit,

8
arch/i386/kernel/cpu/cpufreq/powernow-k6.c
View File

@ -152,7 +152,7 @@ static int powernow_k6_cpu_init(struct cpufreq_policy *policy)
busfreq = cpu_khz / max_multiplier; busfreq = cpu_khz / max_multiplier;
/* table init */ /* table init */
for (i=0; (clock_ratio[i].frequency != CPUFREQ_TABLE_END); i++) { for (i=0; (clock_ratio[i].frequency != CPUFREQ_TABLE_END); i++) {
if (clock_ratio[i].index > max_multiplier) if (clock_ratio[i].index > max_multiplier)
clock_ratio[i].frequency = CPUFREQ_ENTRY_INVALID; clock_ratio[i].frequency = CPUFREQ_ENTRY_INVALID;
else else
@ -182,7 +182,7 @@ static int powernow_k6_cpu_exit(struct cpufreq_policy *policy)
powernow_k6_set_state(i); powernow_k6_set_state(i);
} }
cpufreq_frequency_table_put_attr(policy->cpu); cpufreq_frequency_table_put_attr(policy->cpu);
return 0; return 0;
} }
static unsigned int powernow_k6_get(unsigned int cpu) static unsigned int powernow_k6_get(unsigned int cpu)
@ -196,8 +196,8 @@ static struct freq_attr* powernow_k6_attr[] = {
}; };
static struct cpufreq_driver powernow_k6_driver = { static struct cpufreq_driver powernow_k6_driver = {
.verify = powernow_k6_verify, .verify = powernow_k6_verify,
.target = powernow_k6_target, .target = powernow_k6_target,
.init = powernow_k6_cpu_init, .init = powernow_k6_cpu_init,
.exit = powernow_k6_cpu_exit, .exit = powernow_k6_cpu_exit,
.get = powernow_k6_get, .get = powernow_k6_get,

9
arch/i386/kernel/cpu/cpufreq/powernow-k8.c
View File

@ -83,11 +83,10 @@ static u32 find_millivolts_from_vid(struct powernow_k8_data *data, u32 vid)
*/ */
static u32 convert_fid_to_vco_fid(u32 fid) static u32 convert_fid_to_vco_fid(u32 fid)
{ {
if (fid < HI_FID_TABLE_BOTTOM) { if (fid < HI_FID_TABLE_BOTTOM)
return 8 + (2 * fid); return 8 + (2 * fid);
} else { else
return fid; return fid;
}
} }
/* /*
@ -782,9 +781,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
/* verify only 1 entry from the lo frequency table */ /* verify only 1 entry from the lo frequency table */
if (fid < HI_FID_TABLE_BOTTOM) { if (fid < HI_FID_TABLE_BOTTOM) {
if (cntlofreq) { if (cntlofreq) {
/* if both entries are the same, ignore this /* if both entries are the same, ignore this one ... */
* one...
*/
if ((powernow_table[i].frequency != powernow_table[cntlofreq].frequency) || if ((powernow_table[i].frequency != powernow_table[cntlofreq].frequency) ||
(powernow_table[i].index != powernow_table[cntlofreq].index)) { (powernow_table[i].index != powernow_table[cntlofreq].index)) {
printk(KERN_ERR PFX "Too many lo freq table entries\n"); printk(KERN_ERR PFX "Too many lo freq table entries\n");

2
arch/i386/kernel/cpu/cpufreq/powernow-k8.h
View File

@ -63,7 +63,7 @@ struct powernow_k8_data {
#define MSR_C_LO_VID_SHIFT 8 #define MSR_C_LO_VID_SHIFT 8
/* Field definitions within the FID VID High Control MSR : */ /* Field definitions within the FID VID High Control MSR : */
#define MSR_C_HI_STP_GNT_TO 0x000fffff #define MSR_C_HI_STP_GNT_TO 0x000fffff
/* Field definitions within the FID VID Low Status MSR : */ /* Field definitions within the FID VID Low Status MSR : */
#define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */ #define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */

26
arch/i386/kernel/cpu/cpufreq/speedstep-lib.c
View File

@ -36,8 +36,8 @@ static unsigned int pentium3_get_frequency (unsigned int processor)
/* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */ /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
struct { struct {
unsigned int ratio; /* Frequency Multiplier (x10) */ unsigned int ratio; /* Frequency Multiplier (x10) */
u8 bitmap; /* power on configuration bits u8 bitmap; /* power on configuration bits
[27, 25:22] (in MSR 0x2a) */ [27, 25:22] (in MSR 0x2a) */
} msr_decode_mult [] = { } msr_decode_mult [] = {
{ 30, 0x01 }, { 30, 0x01 },
{ 35, 0x05 }, { 35, 0x05 },
@ -58,9 +58,9 @@ static unsigned int pentium3_get_frequency (unsigned int processor)
/* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */ /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
struct { struct {
unsigned int value; /* Front Side Bus speed in MHz */ unsigned int value; /* Front Side Bus speed in MHz */
u8 bitmap; /* power on configuration bits [18: 19] u8 bitmap; /* power on configuration bits [18: 19]
(in MSR 0x2a) */ (in MSR 0x2a) */
} msr_decode_fsb [] = { } msr_decode_fsb [] = {
{ 66, 0x0 }, { 66, 0x0 },
{ 100, 0x2 }, { 100, 0x2 },
@ -68,8 +68,8 @@ static unsigned int pentium3_get_frequency (unsigned int processor)
{ 0, 0xff} { 0, 0xff}
}; };
u32 msr_lo, msr_tmp; u32 msr_lo, msr_tmp;
int i = 0, j = 0; int i = 0, j = 0;
/* read MSR 0x2a - we only need the low 32 bits */ /* read MSR 0x2a - we only need the low 32 bits */
rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
@ -106,7 +106,7 @@ static unsigned int pentium3_get_frequency (unsigned int processor)
static unsigned int pentiumM_get_frequency(void) static unsigned int pentiumM_get_frequency(void)
{ {
u32 msr_lo, msr_tmp; u32 msr_lo, msr_tmp;
rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
@ -198,7 +198,7 @@ EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency);
unsigned int speedstep_detect_processor (void) unsigned int speedstep_detect_processor (void)
{ {
struct cpuinfo_x86 *c = cpu_data; struct cpuinfo_x86 *c = cpu_data;
u32 ebx, msr_lo, msr_hi; u32 ebx, msr_lo, msr_hi;
dprintk("x86: %x, model: %x\n", c->x86, c->x86_model); dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);
@ -253,7 +253,7 @@ unsigned int speedstep_detect_processor (void)
* also, M-P4M HTs have ebx=0x8, too * also, M-P4M HTs have ebx=0x8, too
* For now, they are distinguished by the model_id string * For now, they are distinguished by the model_id string
*/ */
if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL)) if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL))
return SPEEDSTEP_PROCESSOR_P4M; return SPEEDSTEP_PROCESSOR_P4M;
break; break;
default: default:
@ -264,8 +264,7 @@ unsigned int speedstep_detect_processor (void)
switch (c->x86_model) { switch (c->x86_model) {
case 0x0B: /* Intel PIII [Tualatin] */ case 0x0B: /* Intel PIII [Tualatin] */
/* cpuid_ebx(1) is 0x04 for desktop PIII, /* cpuid_ebx(1) is 0x04 for desktop PIII, 0x06 for mobile PIII-M */
0x06 for mobile PIII-M */
ebx = cpuid_ebx(0x00000001); ebx = cpuid_ebx(0x00000001);
dprintk("ebx is %x\n", ebx); dprintk("ebx is %x\n", ebx);
@ -277,7 +276,6 @@ unsigned int speedstep_detect_processor (void)
/* So far all PIII-M processors support SpeedStep. See /* So far all PIII-M processors support SpeedStep. See
* Intel's 24540640.pdf of June 2003 * Intel's 24540640.pdf of June 2003
*/ */
return SPEEDSTEP_PROCESSOR_PIII_T; return SPEEDSTEP_PROCESSOR_PIII_T;
case 0x08: /* Intel PIII [Coppermine] */ case 0x08: /* Intel PIII [Coppermine] */
@ -399,7 +397,7 @@ unsigned int speedstep_get_freqs(unsigned int processor,
} }
} }
out: out:
local_irq_restore(flags); local_irq_restore(flags);
return (ret); return (ret);
} }

14
arch/i386/kernel/cpu/cpufreq/speedstep-lib.h
View File

@ -14,7 +14,7 @@
#define SPEEDSTEP_PROCESSOR_PIII_C_EARLY 0x00000001 /* Coppermine core */ #define SPEEDSTEP_PROCESSOR_PIII_C_EARLY 0x00000001 /* Coppermine core */
#define SPEEDSTEP_PROCESSOR_PIII_C 0x00000002 /* Coppermine core */ #define SPEEDSTEP_PROCESSOR_PIII_C 0x00000002 /* Coppermine core */
#define SPEEDSTEP_PROCESSOR_PIII_T 0x00000003 /* Tualatin core */ #define SPEEDSTEP_PROCESSOR_PIII_T 0x00000003 /* Tualatin core */
#define SPEEDSTEP_PROCESSOR_P4M 0x00000004 /* P4-M */ #define SPEEDSTEP_PROCESSOR_P4M 0x00000004 /* P4-M */
/* the following processors are not speedstep-capable and are not auto-detected /* the following processors are not speedstep-capable and are not auto-detected
@ -25,8 +25,8 @@
/* speedstep states -- only two of them */ /* speedstep states -- only two of them */
#define SPEEDSTEP_HIGH 0x00000000 #define SPEEDSTEP_HIGH 0x00000000
#define SPEEDSTEP_LOW 0x00000001 #define SPEEDSTEP_LOW 0x00000001
/* detect a speedstep-capable processor */ /* detect a speedstep-capable processor */
@ -42,7 +42,7 @@ extern unsigned int speedstep_get_processor_frequency(unsigned int processor);
* cpufreq_notify_transition calls are initiated. * cpufreq_notify_transition calls are initiated.
*/ */
extern unsigned int speedstep_get_freqs(unsigned int processor, extern unsigned int speedstep_get_freqs(unsigned int processor,
unsigned int *low_speed, unsigned int *low_speed,
unsigned int *high_speed, unsigned int *high_speed,
unsigned int *transition_latency, unsigned int *transition_latency,
void (*set_state) (unsigned int state)); void (*set_state) (unsigned int state));

29
arch/i386/kernel/cpu/cpufreq/speedstep-smi.c
View File

@ -30,19 +30,19 @@
* If user gives it, these are used. * If user gives it, these are used.
* *
*/ */
static int smi_port = 0; static int smi_port = 0;
static int smi_cmd = 0; static int smi_cmd = 0;
static unsigned int smi_sig = 0; static unsigned int smi_sig = 0;
/* info about the processor */ /* info about the processor */
static unsigned int speedstep_processor = 0; static unsigned int speedstep_processor = 0;
/* /*
* There are only two frequency states for each processor. Values * There are only two frequency states for each processor. Values
* are in kHz for the time being. * are in kHz for the time being.
*/ */
static struct cpufreq_frequency_table speedstep_freqs[] = { static struct cpufreq_frequency_table speedstep_freqs[] = {
{SPEEDSTEP_HIGH, 0}, {SPEEDSTEP_HIGH, 0},
{SPEEDSTEP_LOW, 0}, {SPEEDSTEP_LOW, 0},
{0, CPUFREQ_TABLE_END}, {0, CPUFREQ_TABLE_END},
}; };
@ -296,7 +296,7 @@ static int speedstep_cpu_init(struct cpufreq_policy *policy)
if (result) if (result)
return (result); return (result);
cpufreq_frequency_table_get_attr(speedstep_freqs, policy->cpu); cpufreq_frequency_table_get_attr(speedstep_freqs, policy->cpu);
return 0; return 0;
} }
@ -332,8 +332,8 @@ static struct freq_attr* speedstep_attr[] = {
static struct cpufreq_driver speedstep_driver = { static struct cpufreq_driver speedstep_driver = {
.name = "speedstep-smi", .name = "speedstep-smi",
.verify = speedstep_verify, .verify = speedstep_verify,
.target = speedstep_target, .target = speedstep_target,
.init = speedstep_cpu_init, .init = speedstep_cpu_init,
.exit = speedstep_cpu_exit, .exit = speedstep_cpu_exit,
.get = speedstep_get, .get = speedstep_get,
@ -373,7 +373,6 @@ static int __init speedstep_init(void)
dprintk("signature:0x%.8lx, command:0x%.8lx, event:0x%.8lx, perf_level:0x%.8lx.\n", dprintk("signature:0x%.8lx, command:0x%.8lx, event:0x%.8lx, perf_level:0x%.8lx.\n",
ist_info.signature, ist_info.command, ist_info.event, ist_info.perf_level); ist_info.signature, ist_info.command, ist_info.event, ist_info.perf_level);
/* Error if no IST-SMI BIOS or no PARM /* Error if no IST-SMI BIOS or no PARM
sig= 'ISGE' aka 'Intel Speedstep Gate E' */ sig= 'ISGE' aka 'Intel Speedstep Gate E' */
if ((ist_info.signature != 0x47534943) && ( if ((ist_info.signature != 0x47534943) && (
@ -386,17 +385,15 @@ static int __init speedstep_init(void)
smi_sig = ist_info.signature; smi_sig = ist_info.signature;
/* setup smi_port from MODLULE_PARM or BIOS */ /* setup smi_port from MODLULE_PARM or BIOS */
if ((smi_port > 0xff) || (smi_port < 0)) { if ((smi_port > 0xff) || (smi_port < 0))
return -EINVAL; return -EINVAL;
} else if (smi_port == 0) { else if (smi_port == 0)
smi_port = ist_info.command & 0xff; smi_port = ist_info.command & 0xff;
}
if ((smi_cmd > 0xff) || (smi_cmd < 0)) { if ((smi_cmd > 0xff) || (smi_cmd < 0))
return -EINVAL; return -EINVAL;
} else if (smi_cmd == 0) { else if (smi_cmd == 0)
smi_cmd = (ist_info.command >> 16) & 0xff; smi_cmd = (ist_info.command >> 16) & 0xff;
}
return cpufreq_register_driver(&speedstep_driver); return cpufreq_register_driver(&speedstep_driver);
} }

16
drivers/cpufreq/cpufreq.c
View File

@ -5,7 +5,7 @@
* (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de> * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
* *
* Oct 2005 - Ashok Raj <ashok.raj@intel.com> * Oct 2005 - Ashok Raj <ashok.raj@intel.com>
* Added handling for CPU hotplug * Added handling for CPU hotplug
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
@ -335,11 +335,11 @@ extern struct sysdev_class cpu_sysdev_class;
* "unsigned int". * "unsigned int".
*/ */
#define show_one(file_name, object) \ #define show_one(file_name, object) \
static ssize_t show_##file_name \ static ssize_t show_##file_name \
(struct cpufreq_policy * policy, char *buf) \ (struct cpufreq_policy * policy, char *buf) \
{ \ { \
return sprintf (buf, "%u\n", policy->object); \ return sprintf (buf, "%u\n", policy->object); \
} }
show_one(cpuinfo_min_freq, cpuinfo.min_freq); show_one(cpuinfo_min_freq, cpuinfo.min_freq);
@ -740,7 +740,7 @@ static int cpufreq_remove_dev (struct sys_device * sys_dev)
if (!kobject_get(&data->kobj)) { if (!kobject_get(&data->kobj)) {
spin_unlock_irqrestore(&cpufreq_driver_lock, flags); spin_unlock_irqrestore(&cpufreq_driver_lock, flags);
cpufreq_debug_enable_ratelimit(); cpufreq_debug_enable_ratelimit();
return -EFAULT; return -EFAULT;
} }
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
@ -1234,7 +1234,7 @@ int cpufreq_register_governor(struct cpufreq_governor *governor)
} }
list_add(&governor->governor_list, &cpufreq_governor_list); list_add(&governor->governor_list, &cpufreq_governor_list);
mutex_unlock(&cpufreq_governor_mutex); mutex_unlock(&cpufreq_governor_mutex);
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(cpufreq_register_governor); EXPORT_SYMBOL_GPL(cpufreq_register_governor);

32
drivers/cpufreq/cpufreq_ondemand.c
View File

@ -48,7 +48,7 @@
* this governor will not work. * this governor will not work.
* All times here are in uS. * All times here are in uS.
*/ */
static unsigned int def_sampling_rate; static unsigned int def_sampling_rate;
#define MIN_SAMPLING_RATE_RATIO (2) #define MIN_SAMPLING_RATE_RATIO (2)
/* for correct statistics, we need at least 10 ticks between each measure */ /* for correct statistics, we need at least 10 ticks between each measure */
#define MIN_STAT_SAMPLING_RATE (MIN_SAMPLING_RATE_RATIO * jiffies_to_usecs(10)) #define MIN_STAT_SAMPLING_RATE (MIN_SAMPLING_RATE_RATIO * jiffies_to_usecs(10))
@ -62,28 +62,28 @@ static unsigned int def_sampling_rate;
static void do_dbs_timer(void *data); static void do_dbs_timer(void *data);
struct cpu_dbs_info_s { struct cpu_dbs_info_s {
struct cpufreq_policy *cur_policy; struct cpufreq_policy *cur_policy;
unsigned int prev_cpu_idle_up; unsigned int prev_cpu_idle_up;
unsigned int prev_cpu_idle_down; unsigned int prev_cpu_idle_down;
unsigned int enable; unsigned int enable;
}; };
static DEFINE_PER_CPU(struct cpu_dbs_info_s, cpu_dbs_info); static DEFINE_PER_CPU(struct cpu_dbs_info_s, cpu_dbs_info);
static unsigned int dbs_enable; /* number of CPUs using this policy */ static unsigned int dbs_enable; /* number of CPUs using this policy */
static DEFINE_MUTEX (dbs_mutex); static DEFINE_MUTEX (dbs_mutex);
static DECLARE_WORK (dbs_work, do_dbs_timer, NULL); static DECLARE_WORK (dbs_work, do_dbs_timer, NULL);
struct dbs_tuners { struct dbs_tuners {
unsigned int sampling_rate; unsigned int sampling_rate;
unsigned int sampling_down_factor; unsigned int sampling_down_factor;
unsigned int up_threshold; unsigned int up_threshold;
unsigned int ignore_nice; unsigned int ignore_nice;
}; };
static struct dbs_tuners dbs_tuners_ins = { static struct dbs_tuners dbs_tuners_ins = {
.up_threshold = DEF_FREQUENCY_UP_THRESHOLD, .up_threshold = DEF_FREQUENCY_UP_THRESHOLD,
.sampling_down_factor = DEF_SAMPLING_DOWN_FACTOR, .sampling_down_factor = DEF_SAMPLING_DOWN_FACTOR,
}; };
static inline unsigned int get_cpu_idle_time(unsigned int cpu) static inline unsigned int get_cpu_idle_time(unsigned int cpu)
@ -106,8 +106,8 @@ static ssize_t show_sampling_rate_min(struct cpufreq_policy *policy, char *buf)
return sprintf (buf, "%u\n", MIN_SAMPLING_RATE); return sprintf (buf, "%u\n", MIN_SAMPLING_RATE);
} }
#define define_one_ro(_name) \ #define define_one_ro(_name) \
static struct freq_attr _name = \ static struct freq_attr _name = \
__ATTR(_name, 0444, show_##_name, NULL) __ATTR(_name, 0444, show_##_name, NULL)
define_one_ro(sampling_rate_max); define_one_ro(sampling_rate_max);
@ -460,11 +460,11 @@ static int cpufreq_governor_dbs(struct cpufreq_policy *policy,
if (policy->max < this_dbs_info->cur_policy->cur) if (policy->max < this_dbs_info->cur_policy->cur)
__cpufreq_driver_target( __cpufreq_driver_target(
this_dbs_info->cur_policy, this_dbs_info->cur_policy,
policy->max, CPUFREQ_RELATION_H); policy->max, CPUFREQ_RELATION_H);
else if (policy->min > this_dbs_info->cur_policy->cur) else if (policy->min > this_dbs_info->cur_policy->cur)
__cpufreq_driver_target( __cpufreq_driver_target(
this_dbs_info->cur_policy, this_dbs_info->cur_policy,
policy->min, CPUFREQ_RELATION_L); policy->min, CPUFREQ_RELATION_L);
mutex_unlock(&dbs_mutex); mutex_unlock(&dbs_mutex);
break; break;
} }

2
drivers/cpufreq/cpufreq_stats.c
View File

@ -2,7 +2,7 @@
* drivers/cpufreq/cpufreq_stats.c * drivers/cpufreq/cpufreq_stats.c
* *
* Copyright (C) 2003-2004 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>. * Copyright (C) 2003-2004 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>.
* (C) 2004 Zou Nan hai <nanhai.zou@intel.com>. * (C) 2004 Zou Nan hai <nanhai.zou@intel.com>.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as

6
drivers/cpufreq/freq_table.c
View File

@ -60,8 +60,7 @@ int cpufreq_frequency_table_verify(struct cpufreq_policy *policy,
return -EINVAL; return -EINVAL;
cpufreq_verify_within_limits(policy, cpufreq_verify_within_limits(policy,
policy->cpuinfo.min_freq, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
policy->cpuinfo.max_freq);
for (i=0; (table[i].frequency != CPUFREQ_TABLE_END); i++) { for (i=0; (table[i].frequency != CPUFREQ_TABLE_END); i++) {
unsigned int freq = table[i].frequency; unsigned int freq = table[i].frequency;
@ -77,8 +76,7 @@ int cpufreq_frequency_table_verify(struct cpufreq_policy *policy,
policy->max = next_larger; policy->max = next_larger;
cpufreq_verify_within_limits(policy, cpufreq_verify_within_limits(policy,
policy->cpuinfo.min_freq, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
policy->cpuinfo.max_freq);
dprintk("verification lead to (%u - %u kHz) for cpu %u\n", policy->min, policy->max, policy->cpu); dprintk("verification lead to (%u - %u kHz) for cpu %u\n", policy->min, policy->max, policy->cpu);