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net: sparx5: use phylink_generic_validate()

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Sparx5 has no special behaviour in its validation implementation, so can
be switched to phylink_generic_validate().

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King (Oracle)
2021-11-16 10:02:11 +00:00
committed by David S. Miller
parent 9b5cc05fd9
commit 319faa90b7
2 changed files with 4 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/net/ethernet/microchip/sparx5/sparx5_main.c
View File

@@ -292,6 +292,9 @@ static int sparx5_create_port(struct sparx5 *sparx5,
spx5_port->phylink_config.dev = &spx5_port->ndev->dev; spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
spx5_port->phylink_config.type = PHYLINK_NETDEV; spx5_port->phylink_config.type = PHYLINK_NETDEV;
spx5_port->phylink_config.pcs_poll = true; spx5_port->phylink_config.pcs_poll = true;
spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD |
MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD;
__set_bit(PHY_INTERFACE_MODE_SGMII, __set_bit(PHY_INTERFACE_MODE_SGMII,
spx5_port->phylink_config.supported_interfaces); spx5_port->phylink_config.supported_interfaces);

60
drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c
View File

@@ -26,64 +26,6 @@ static bool port_conf_has_changed(struct sparx5_port_config *a, struct sparx5_po
return false; return false;
} }
static void sparx5_phylink_validate(struct phylink_config *config,
unsigned long *supported,
struct phylink_link_state *state)
{
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
phylink_set(mask, Autoneg);
phylink_set_port_modes(mask);
phylink_set(mask, Pause);
phylink_set(mask, Asym_Pause);
switch (state->interface) {
case PHY_INTERFACE_MODE_5GBASER:
phylink_set(mask, 5000baseT_Full);
break;
case PHY_INTERFACE_MODE_10GBASER:
phylink_set(mask, 10000baseT_Full);
phylink_set(mask, 10000baseCR_Full);
phylink_set(mask, 10000baseSR_Full);
phylink_set(mask, 10000baseLR_Full);
phylink_set(mask, 10000baseLRM_Full);
phylink_set(mask, 10000baseER_Full);
break;
case PHY_INTERFACE_MODE_25GBASER:
phylink_set(mask, 25000baseCR_Full);
phylink_set(mask, 25000baseSR_Full);
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_QSGMII:
phylink_set(mask, 10baseT_Half);
phylink_set(mask, 10baseT_Full);
phylink_set(mask, 100baseT_Half);
phylink_set(mask, 100baseT_Full);
phylink_set(mask, 1000baseT_Full);
phylink_set(mask, 1000baseX_Full);
break;
case PHY_INTERFACE_MODE_1000BASEX:
phylink_set(mask, 1000baseT_Full);
phylink_set(mask, 1000baseX_Full);
break;
case PHY_INTERFACE_MODE_2500BASEX:
phylink_set(mask, 2500baseT_Full);
phylink_set(mask, 2500baseX_Full);
break;
default:
linkmode_zero(supported);
return;
}
linkmode_and(supported, supported, mask);
linkmode_and(state->advertising, state->advertising, mask);
}
static void sparx5_phylink_mac_config(struct phylink_config *config, static void sparx5_phylink_mac_config(struct phylink_config *config,
unsigned int mode, unsigned int mode,
const struct phylink_link_state *state) const struct phylink_link_state *state)
@@ -187,7 +129,7 @@ const struct phylink_pcs_ops sparx5_phylink_pcs_ops = {
}; };
const struct phylink_mac_ops sparx5_phylink_mac_ops = { const struct phylink_mac_ops sparx5_phylink_mac_ops = {
.validate = sparx5_phylink_validate, .validate = phylink_generic_validate,
.mac_config = sparx5_phylink_mac_config, .mac_config = sparx5_phylink_mac_config,
.mac_link_down = sparx5_phylink_mac_link_down, .mac_link_down = sparx5_phylink_mac_link_down,
.mac_link_up = sparx5_phylink_mac_link_up, .mac_link_up = sparx5_phylink_mac_link_up,